Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /**************************************************************************
0003  * Copyright (c) 2007-2011, Intel Corporation.
0004  * All Rights Reserved.
0005  *
0006  **************************************************************************/
0007 
0008 #ifndef _PSB_DRV_H_
0009 #define _PSB_DRV_H_
0010 
0011 #include <linux/kref.h>
0012 #include <linux/mm_types.h>
0013 
0014 #include <drm/drm_device.h>
0015 
0016 #include "gtt.h"
0017 #include "intel_bios.h"
0018 #include "mmu.h"
0019 #include "oaktrail.h"
0020 #include "opregion.h"
0021 #include "power.h"
0022 #include "psb_intel_drv.h"
0023 #include "psb_reg.h"
0024 
0025 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
0026 
0027 #define DRIVER_NAME "gma500"
0028 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
0029 #define DRIVER_DATE "20140314"
0030 
0031 #define DRIVER_MAJOR 1
0032 #define DRIVER_MINOR 0
0033 #define DRIVER_PATCHLEVEL 0
0034 
0035 /* Append new drm mode definition here, align with libdrm definition */
0036 #define DRM_MODE_SCALE_NO_SCALE     2
0037 
0038 #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
0039 #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
0040 #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
0041 
0042 /* Hardware offsets */
0043 #define PSB_VDC_OFFSET       0x00000000
0044 #define PSB_VDC_SIZE         0x000080000
0045 #define MRST_MMIO_SIZE       0x0000C0000
0046 #define PSB_SGX_SIZE         0x8000
0047 #define PSB_SGX_OFFSET       0x00040000
0048 #define MRST_SGX_OFFSET      0x00080000
0049 
0050 /* PCI resource identifiers */
0051 #define PSB_MMIO_RESOURCE    0
0052 #define PSB_AUX_RESOURCE     0
0053 #define PSB_GATT_RESOURCE    2
0054 #define PSB_GTT_RESOURCE     3
0055 
0056 /* PCI configuration */
0057 #define PSB_GMCH_CTRL        0x52
0058 #define PSB_BSM          0x5C
0059 #define _PSB_GMCH_ENABLED    0x4
0060 #define PSB_PGETBL_CTL       0x2020
0061 #define _PSB_PGETBL_ENABLED  0x00000001
0062 #define PSB_SGX_2D_SLAVE_PORT    0x4000
0063 #define PSB_LPC_GBA      0x44
0064 
0065 /* TODO: To get rid of */
0066 #define PSB_TT_PRIV0_LIMIT   (256*1024*1024)
0067 #define PSB_TT_PRIV0_PLIMIT  (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
0068 
0069 /* SGX side MMU definitions (these can probably go) */
0070 
0071 /* Flags for external memory type field */
0072 #define PSB_MMU_CACHED_MEMORY     0x0001    /* Bind to MMU only */
0073 #define PSB_MMU_RO_MEMORY     0x0002    /* MMU RO memory */
0074 #define PSB_MMU_WO_MEMORY     0x0004    /* MMU WO memory */
0075 
0076 /* PTE's and PDE's */
0077 #define PSB_PDE_MASK          0x003FFFFF
0078 #define PSB_PDE_SHIFT         22
0079 #define PSB_PTE_SHIFT         12
0080 
0081 /* Cache control */
0082 #define PSB_PTE_VALID         0x0001    /* PTE / PDE valid */
0083 #define PSB_PTE_WO        0x0002    /* Write only */
0084 #define PSB_PTE_RO        0x0004    /* Read only */
0085 #define PSB_PTE_CACHED        0x0008    /* CPU cache coherent */
0086 
0087 /* VDC registers and bits */
0088 #define PSB_MSVDX_CLOCKGATING     0x2064
0089 #define PSB_TOPAZ_CLOCKGATING     0x2068
0090 #define PSB_HWSTAM        0x2098
0091 #define PSB_INSTPM        0x20C0
0092 #define PSB_INT_IDENTITY_R        0x20A4
0093 #define _PSB_IRQ_ASLE         (1<<0)
0094 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
0095 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
0096 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
0097 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
0098 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
0099 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
0100 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
0101 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
0102 #define _PSB_IRQ_DISP_HOTSYNC     (1<<17)
0103 #define _PSB_IRQ_SGX_FLAG     (1<<18)
0104 #define _PSB_IRQ_MSVDX_FLAG   (1<<19)
0105 #define _LNC_IRQ_TOPAZ_FLAG   (1<<20)
0106 
0107 #define _PSB_PIPE_EVENT_FLAG    (_PSB_VSYNC_PIPEA_FLAG | \
0108                  _PSB_VSYNC_PIPEB_FLAG)
0109 
0110 #define PSB_INT_IDENTITY_R    0x20A4
0111 #define PSB_INT_MASK_R        0x20A8
0112 #define PSB_INT_ENABLE_R      0x20A0
0113 
0114 #define _PSB_MMU_ER_MASK      0x0001FF00
0115 #define _PSB_MMU_ER_HOST      (1 << 16)
0116 #define GPIOA           0x5010
0117 #define GPIOB           0x5014
0118 #define GPIOC           0x5018
0119 #define GPIOD           0x501c
0120 #define GPIOE           0x5020
0121 #define GPIOF           0x5024
0122 #define GPIOG           0x5028
0123 #define GPIOH           0x502c
0124 #define GPIO_CLOCK_DIR_MASK     (1 << 0)
0125 #define GPIO_CLOCK_DIR_IN       (0 << 1)
0126 #define GPIO_CLOCK_DIR_OUT      (1 << 1)
0127 #define GPIO_CLOCK_VAL_MASK     (1 << 2)
0128 #define GPIO_CLOCK_VAL_OUT      (1 << 3)
0129 #define GPIO_CLOCK_VAL_IN       (1 << 4)
0130 #define GPIO_CLOCK_PULLUP_DISABLE   (1 << 5)
0131 #define GPIO_DATA_DIR_MASK      (1 << 8)
0132 #define GPIO_DATA_DIR_IN        (0 << 9)
0133 #define GPIO_DATA_DIR_OUT       (1 << 9)
0134 #define GPIO_DATA_VAL_MASK      (1 << 10)
0135 #define GPIO_DATA_VAL_OUT       (1 << 11)
0136 #define GPIO_DATA_VAL_IN        (1 << 12)
0137 #define GPIO_DATA_PULLUP_DISABLE    (1 << 13)
0138 
0139 #define VCLK_DIVISOR_VGA0   0x6000
0140 #define VCLK_DIVISOR_VGA1   0x6004
0141 #define VCLK_POST_DIV       0x6010
0142 
0143 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
0144 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
0145 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
0146 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
0147 #define PSB_COMM_USER_IRQ (1024 >> 2)
0148 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
0149 #define PSB_COMM_FW (2048 >> 2)
0150 
0151 #define PSB_UIRQ_VISTEST           1
0152 #define PSB_UIRQ_OOM_REPLY         2
0153 #define PSB_UIRQ_FIRE_TA_REPLY         3
0154 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
0155 
0156 #define PSB_2D_SIZE (256*1024*1024)
0157 #define PSB_MAX_RELOC_PAGES 1024
0158 
0159 #define PSB_LOW_REG_OFFS 0x0204
0160 #define PSB_HIGH_REG_OFFS 0x0600
0161 
0162 #define PSB_NUM_VBLANKS 2
0163 
0164 
0165 #define PSB_2D_SIZE (256*1024*1024)
0166 #define PSB_MAX_RELOC_PAGES 1024
0167 
0168 #define PSB_LOW_REG_OFFS 0x0204
0169 #define PSB_HIGH_REG_OFFS 0x0600
0170 
0171 #define PSB_NUM_VBLANKS 2
0172 #define PSB_WATCHDOG_DELAY (HZ * 2)
0173 #define PSB_LID_DELAY (HZ / 10)
0174 
0175 #define PSB_PWR_STATE_ON        1
0176 #define PSB_PWR_STATE_OFF       2
0177 
0178 #define PSB_PMPOLICY_NOPM       0
0179 #define PSB_PMPOLICY_CLOCKGATING    1
0180 #define PSB_PMPOLICY_POWERDOWN      2
0181 
0182 #define PSB_PMSTATE_POWERUP     0
0183 #define PSB_PMSTATE_CLOCKGATED      1
0184 #define PSB_PMSTATE_POWERDOWN       2
0185 #define PSB_PCIx_MSI_ADDR_LOC       0x94
0186 #define PSB_PCIx_MSI_DATA_LOC       0x98
0187 
0188 /* Medfield crystal settings */
0189 #define KSEL_CRYSTAL_19 1
0190 #define KSEL_BYPASS_19 5
0191 #define KSEL_BYPASS_25 6
0192 #define KSEL_BYPASS_83_100 7
0193 
0194 struct drm_fb_helper;
0195 
0196 struct opregion_header;
0197 struct opregion_acpi;
0198 struct opregion_swsci;
0199 struct opregion_asle;
0200 
0201 struct psb_intel_opregion {
0202     struct opregion_header *header;
0203     struct opregion_acpi *acpi;
0204     struct opregion_swsci *swsci;
0205     struct opregion_asle *asle;
0206     void *vbt;
0207     u32 __iomem *lid_state;
0208     struct work_struct asle_work;
0209 };
0210 
0211 struct sdvo_device_mapping {
0212     u8 initialized;
0213     u8 dvo_port;
0214     u8 slave_addr;
0215     u8 dvo_wiring;
0216     u8 i2c_pin;
0217     u8 i2c_speed;
0218     u8 ddc_pin;
0219 };
0220 
0221 struct intel_gmbus {
0222     struct i2c_adapter adapter;
0223     struct i2c_adapter *force_bit;
0224     u32 reg0;
0225 };
0226 
0227 /* Register offset maps */
0228 struct psb_offset {
0229     u32 fp0;
0230     u32 fp1;
0231     u32 cntr;
0232     u32 conf;
0233     u32 src;
0234     u32 dpll;
0235     u32 dpll_md;
0236     u32 htotal;
0237     u32 hblank;
0238     u32 hsync;
0239     u32 vtotal;
0240     u32 vblank;
0241     u32 vsync;
0242     u32 stride;
0243     u32 size;
0244     u32 pos;
0245     u32 surf;
0246     u32 addr;
0247     u32 base;
0248     u32 status;
0249     u32 linoff;
0250     u32 tileoff;
0251     u32 palette;
0252 };
0253 
0254 /*
0255  *  Register save state. This is used to hold the context when the
0256  *  device is powered off. In the case of Oaktrail this can (but does not
0257  *  yet) include screen blank. Operations occuring during the save
0258  *  update the register cache instead.
0259  */
0260 
0261 /* Common status for pipes */
0262 struct psb_pipe {
0263     u32 fp0;
0264     u32 fp1;
0265     u32 cntr;
0266     u32 conf;
0267     u32 src;
0268     u32 dpll;
0269     u32 dpll_md;
0270     u32 htotal;
0271     u32 hblank;
0272     u32 hsync;
0273     u32 vtotal;
0274     u32 vblank;
0275     u32 vsync;
0276     u32 stride;
0277     u32 size;
0278     u32 pos;
0279     u32 base;
0280     u32 surf;
0281     u32 addr;
0282     u32 status;
0283     u32 linoff;
0284     u32 tileoff;
0285     u32 palette[256];
0286 };
0287 
0288 struct psb_state {
0289     uint32_t saveVCLK_DIVISOR_VGA0;
0290     uint32_t saveVCLK_DIVISOR_VGA1;
0291     uint32_t saveVCLK_POST_DIV;
0292     uint32_t saveVGACNTRL;
0293     uint32_t saveADPA;
0294     uint32_t saveLVDS;
0295     uint32_t saveDVOA;
0296     uint32_t saveDVOB;
0297     uint32_t saveDVOC;
0298     uint32_t savePP_ON;
0299     uint32_t savePP_OFF;
0300     uint32_t savePP_CONTROL;
0301     uint32_t savePP_CYCLE;
0302     uint32_t savePFIT_CONTROL;
0303     uint32_t saveCLOCKGATING;
0304     uint32_t saveDSPARB;
0305     uint32_t savePFIT_AUTO_RATIOS;
0306     uint32_t savePFIT_PGM_RATIOS;
0307     uint32_t savePP_ON_DELAYS;
0308     uint32_t savePP_OFF_DELAYS;
0309     uint32_t savePP_DIVISOR;
0310     uint32_t saveBCLRPAT_A;
0311     uint32_t saveBCLRPAT_B;
0312     uint32_t savePERF_MODE;
0313     uint32_t saveDSPFW1;
0314     uint32_t saveDSPFW2;
0315     uint32_t saveDSPFW3;
0316     uint32_t saveDSPFW4;
0317     uint32_t saveDSPFW5;
0318     uint32_t saveDSPFW6;
0319     uint32_t saveCHICKENBIT;
0320     uint32_t saveDSPACURSOR_CTRL;
0321     uint32_t saveDSPBCURSOR_CTRL;
0322     uint32_t saveDSPACURSOR_BASE;
0323     uint32_t saveDSPBCURSOR_BASE;
0324     uint32_t saveDSPACURSOR_POS;
0325     uint32_t saveDSPBCURSOR_POS;
0326     uint32_t saveOV_OVADD;
0327     uint32_t saveOV_OGAMC0;
0328     uint32_t saveOV_OGAMC1;
0329     uint32_t saveOV_OGAMC2;
0330     uint32_t saveOV_OGAMC3;
0331     uint32_t saveOV_OGAMC4;
0332     uint32_t saveOV_OGAMC5;
0333     uint32_t saveOVC_OVADD;
0334     uint32_t saveOVC_OGAMC0;
0335     uint32_t saveOVC_OGAMC1;
0336     uint32_t saveOVC_OGAMC2;
0337     uint32_t saveOVC_OGAMC3;
0338     uint32_t saveOVC_OGAMC4;
0339     uint32_t saveOVC_OGAMC5;
0340 
0341     /* DPST register save */
0342     uint32_t saveHISTOGRAM_INT_CONTROL_REG;
0343     uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
0344     uint32_t savePWM_CONTROL_LOGIC;
0345 };
0346 
0347 struct cdv_state {
0348     uint32_t saveDSPCLK_GATE_D;
0349     uint32_t saveRAMCLK_GATE_D;
0350     uint32_t saveDSPARB;
0351     uint32_t saveDSPFW[6];
0352     uint32_t saveADPA;
0353     uint32_t savePP_CONTROL;
0354     uint32_t savePFIT_PGM_RATIOS;
0355     uint32_t saveLVDS;
0356     uint32_t savePFIT_CONTROL;
0357     uint32_t savePP_ON_DELAYS;
0358     uint32_t savePP_OFF_DELAYS;
0359     uint32_t savePP_CYCLE;
0360     uint32_t saveVGACNTRL;
0361     uint32_t saveIER;
0362     uint32_t saveIMR;
0363     u8   saveLBB;
0364 };
0365 
0366 struct psb_save_area {
0367     struct psb_pipe pipe[3];
0368     uint32_t saveBSM;
0369     uint32_t saveVBT;
0370     union {
0371             struct psb_state psb;
0372         struct cdv_state cdv;
0373     };
0374     uint32_t saveBLC_PWM_CTL2;
0375     uint32_t saveBLC_PWM_CTL;
0376 };
0377 
0378 struct psb_ops;
0379 
0380 #define PSB_NUM_PIPE        3
0381 
0382 struct intel_scu_ipc_dev;
0383 
0384 struct drm_psb_private {
0385     struct drm_device dev;
0386 
0387     struct pci_dev *aux_pdev; /* Currently only used by mrst */
0388     struct pci_dev *lpc_pdev; /* Currently only used by mrst */
0389     const struct psb_ops *ops;
0390     const struct psb_offset *regmap;
0391 
0392     struct child_device_config *child_dev;
0393     int child_dev_num;
0394 
0395     struct psb_gtt gtt;
0396 
0397     /* GTT Memory manager */
0398     struct psb_gtt_mm *gtt_mm;
0399     struct page *scratch_page;
0400     u32 __iomem *gtt_map;
0401     uint32_t stolen_base;
0402     u8 __iomem *vram_addr;
0403     unsigned long vram_stolen_size;
0404     u16 gmch_ctrl;      /* Saved GTT setup */
0405     u32 pge_ctl;
0406 
0407     struct mutex gtt_mutex;
0408     struct resource *gtt_mem;   /* Our PCI resource */
0409 
0410     struct mutex mmap_mutex;
0411 
0412     struct psb_mmu_driver *mmu;
0413     struct psb_mmu_pd *pf_pd;
0414 
0415     /* Register base */
0416     uint8_t __iomem *sgx_reg;
0417     uint8_t __iomem *vdc_reg;
0418     uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
0419     uint16_t lpc_gpio_base;
0420     uint32_t gatt_free_offset;
0421 
0422     /* Fencing / irq */
0423     uint32_t vdc_irq_mask;
0424     uint32_t pipestat[PSB_NUM_PIPE];
0425 
0426     spinlock_t irqmask_lock;
0427 
0428     /* Power */
0429     bool suspended;
0430     bool display_power;
0431     int display_count;
0432 
0433     /* Modesetting */
0434     struct psb_intel_mode_device mode_dev;
0435     bool modeset;   /* true if we have done the mode_device setup */
0436 
0437     struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
0438     struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
0439     uint32_t num_pipe;
0440 
0441     /* OSPM info (Power management base) (TODO: can go ?) */
0442     uint32_t ospm_base;
0443 
0444     /* Sizes info */
0445     u32 fuse_reg_value;
0446     u32 video_device_fuse;
0447 
0448     /* PCI revision ID for B0:D2:F0 */
0449     uint8_t platform_rev_id;
0450 
0451     /* gmbus */
0452     struct intel_gmbus *gmbus;
0453     uint8_t __iomem *gmbus_reg;
0454 
0455     /* Used by SDVO */
0456     int crt_ddc_pin;
0457     /* FIXME: The mappings should be parsed from bios but for now we can
0458           pretend there are no mappings available */
0459     struct sdvo_device_mapping sdvo_mappings[2];
0460     u32 hotplug_supported_mask;
0461     struct drm_property *broadcast_rgb_property;
0462     struct drm_property *force_audio_property;
0463 
0464     /* LVDS info */
0465     int backlight_duty_cycle;   /* restore backlight to this value */
0466     bool panel_wants_dither;
0467     struct drm_display_mode *panel_fixed_mode;
0468     struct drm_display_mode *lfp_lvds_vbt_mode;
0469     struct drm_display_mode *sdvo_lvds_vbt_mode;
0470 
0471     struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
0472     struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
0473 
0474     /* Feature bits from the VBIOS */
0475     unsigned int int_tv_support:1;
0476     unsigned int lvds_dither:1;
0477     unsigned int lvds_vbt:1;
0478     unsigned int int_crt_support:1;
0479     unsigned int lvds_use_ssc:1;
0480     int lvds_ssc_freq;
0481     bool is_lvds_on;
0482     bool is_mipi_on;
0483     bool lvds_enabled_in_vbt;
0484     u32 mipi_ctrl_display;
0485 
0486     unsigned int core_freq;
0487     uint32_t iLVDS_enable;
0488 
0489     /* Runtime PM state */
0490     int rpm_enabled;
0491 
0492     /* MID specific */
0493     bool use_msi;
0494     bool has_gct;
0495     struct oaktrail_gct_data gct_data;
0496 
0497     /* Oaktrail HDMI state */
0498     struct oaktrail_hdmi_dev *hdmi_priv;
0499 
0500     /* Register state */
0501     struct psb_save_area regs;
0502 
0503     /* Hotplug handling */
0504     struct work_struct hotplug_work;
0505 
0506     /* LID-Switch */
0507     spinlock_t lid_lock;
0508     struct timer_list lid_timer;
0509     struct psb_intel_opregion opregion;
0510     u32 lid_last_state;
0511 
0512     /* Watchdog */
0513     uint32_t apm_reg;
0514     uint16_t apm_base;
0515 
0516     /*
0517      * Used for modifying backlight from
0518      * xrandr -- consider removing and using HAL instead
0519      */
0520     struct intel_scu_ipc_dev *scu;
0521     struct backlight_device *backlight_device;
0522     struct drm_property *backlight_property;
0523     bool backlight_enabled;
0524     int backlight_level;
0525     uint32_t blc_adj1;
0526     uint32_t blc_adj2;
0527 
0528     struct drm_fb_helper *fb_helper;
0529 
0530     /* Panel brightness */
0531     int brightness;
0532     int brightness_adjusted;
0533 
0534     bool dsr_enable;
0535     u32 dsr_fb_update;
0536     bool dpi_panel_on[3];
0537     void *dsi_configs[2];
0538     u32 bpp;
0539     u32 bpp2;
0540 
0541     u32 pipeconf[3];
0542     u32 dspcntr[3];
0543 
0544     bool dplla_96mhz;   /* DPLL data from the VBT */
0545 
0546     struct {
0547         int rate;
0548         int lanes;
0549         int preemphasis;
0550         int vswing;
0551 
0552         bool initialized;
0553         bool support;
0554         int bpp;
0555         struct edp_power_seq pps;
0556     } edp;
0557     uint8_t panel_type;
0558 };
0559 
0560 static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev)
0561 {
0562     return container_of(dev, struct drm_psb_private, dev);
0563 }
0564 
0565 /* Operations for each board type */
0566 struct psb_ops {
0567     const char *name;
0568     int pipes;      /* Number of output pipes */
0569     int crtcs;      /* Number of CRTCs */
0570     int sgx_offset;     /* Base offset of SGX device */
0571     int hdmi_mask;      /* Mask of HDMI CRTCs */
0572     int lvds_mask;      /* Mask of LVDS CRTCs */
0573     int sdvo_mask;      /* Mask of SDVO CRTCs */
0574     int cursor_needs_phys;  /* If cursor base reg need physical address */
0575 
0576     /* Sub functions */
0577     struct drm_crtc_helper_funcs const *crtc_helper;
0578     const struct gma_clock_funcs *clock_funcs;
0579 
0580     /* Setup hooks */
0581     int (*chip_setup)(struct drm_device *dev);
0582     void (*chip_teardown)(struct drm_device *dev);
0583     /* Optional helper caller after modeset */
0584     void (*errata)(struct drm_device *dev);
0585 
0586     /* Display management hooks */
0587     int (*output_init)(struct drm_device *dev);
0588     int (*hotplug)(struct drm_device *dev);
0589     void (*hotplug_enable)(struct drm_device *dev, bool on);
0590     /* Power management hooks */
0591     void (*init_pm)(struct drm_device *dev);
0592     int (*save_regs)(struct drm_device *dev);
0593     int (*restore_regs)(struct drm_device *dev);
0594     void (*save_crtc)(struct drm_crtc *crtc);
0595     void (*restore_crtc)(struct drm_crtc *crtc);
0596     int (*power_up)(struct drm_device *dev);
0597     int (*power_down)(struct drm_device *dev);
0598     void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
0599     void (*disable_sr)(struct drm_device *dev);
0600 
0601     void (*lvds_bl_power)(struct drm_device *dev, bool on);
0602 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
0603     /* Backlight */
0604     int (*backlight_init)(struct drm_device *dev);
0605 #endif
0606     int i2c_bus;        /* I2C bus identifier for Moorestown */
0607 };
0608 
0609 /* psb_lid.c */
0610 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
0611 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
0612 
0613 /* modesetting */
0614 extern void psb_modeset_init(struct drm_device *dev);
0615 extern void psb_modeset_cleanup(struct drm_device *dev);
0616 extern int psb_fbdev_init(struct drm_device *dev);
0617 
0618 /* backlight.c */
0619 int gma_backlight_init(struct drm_device *dev);
0620 void gma_backlight_exit(struct drm_device *dev);
0621 void gma_backlight_disable(struct drm_device *dev);
0622 void gma_backlight_enable(struct drm_device *dev);
0623 void gma_backlight_set(struct drm_device *dev, int v);
0624 
0625 /* oaktrail_crtc.c */
0626 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
0627 
0628 /* oaktrail_lvds.c */
0629 extern void oaktrail_lvds_init(struct drm_device *dev,
0630             struct psb_intel_mode_device *mode_dev);
0631 
0632 /* psb_intel_display.c */
0633 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
0634 
0635 /* psb_intel_lvds.c */
0636 extern const struct drm_connector_helper_funcs
0637                     psb_intel_lvds_connector_helper_funcs;
0638 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
0639 
0640 /* gem.c */
0641 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
0642             struct drm_mode_create_dumb *args);
0643 
0644 /* psb_device.c */
0645 extern const struct psb_ops psb_chip_ops;
0646 
0647 /* oaktrail_device.c */
0648 extern const struct psb_ops oaktrail_chip_ops;
0649 
0650 /* cdv_device.c */
0651 extern const struct psb_ops cdv_chip_ops;
0652 
0653 /* Utilities */
0654 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
0655 {
0656     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0657     return ioread32(dev_priv->vdc_reg + reg);
0658 }
0659 
0660 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
0661 {
0662     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0663     return ioread32(dev_priv->aux_reg + reg);
0664 }
0665 
0666 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
0667 #define REG_READ_AUX(reg)      REGISTER_READ_AUX(dev, (reg))
0668 
0669 /* Useful for post reads */
0670 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
0671                           uint32_t reg, int aux)
0672 {
0673     uint32_t val;
0674 
0675     if (aux)
0676         val = REG_READ_AUX(reg);
0677     else
0678         val = REG_READ(reg);
0679 
0680     return val;
0681 }
0682 
0683 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
0684 
0685 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
0686                   uint32_t val)
0687 {
0688     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0689     iowrite32((val), dev_priv->vdc_reg + (reg));
0690 }
0691 
0692 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
0693                       uint32_t val)
0694 {
0695     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0696     iowrite32((val), dev_priv->aux_reg + (reg));
0697 }
0698 
0699 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
0700 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
0701 
0702 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
0703                       uint32_t val, int aux)
0704 {
0705     if (aux)
0706         REG_WRITE_AUX(reg, val);
0707     else
0708         REG_WRITE(reg, val);
0709 }
0710 
0711 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
0712 
0713 static inline void REGISTER_WRITE16(struct drm_device *dev,
0714                     uint32_t reg, uint32_t val)
0715 {
0716     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0717     iowrite16((val), dev_priv->vdc_reg + (reg));
0718 }
0719 
0720 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
0721 
0722 static inline void REGISTER_WRITE8(struct drm_device *dev,
0723                        uint32_t reg, uint32_t val)
0724 {
0725     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0726     iowrite8((val), dev_priv->vdc_reg + (reg));
0727 }
0728 
0729 #define REG_WRITE8(reg, val)        REGISTER_WRITE8(dev, (reg), (val))
0730 
0731 #define PSB_WVDC32(_val, _offs)     iowrite32(_val, dev_priv->vdc_reg + (_offs))
0732 #define PSB_RVDC32(_offs)       ioread32(dev_priv->vdc_reg + (_offs))
0733 
0734 #define PSB_RSGX32(_offs)       ioread32(dev_priv->sgx_reg + (_offs))
0735 #define PSB_WSGX32(_val, _offs)     iowrite32(_val, dev_priv->sgx_reg + (_offs))
0736 
0737 #define PSB_WMSVDX32(_val, _offs)   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
0738 #define PSB_RMSVDX32(_offs)     ioread32(dev_priv->msvdx_reg + (_offs))
0739 
0740 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!