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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright © 2006-2009 Intel Corporation
0004  *
0005  * Authors:
0006  *  Eric Anholt <eric@anholt.net>
0007  *  Dave Airlie <airlied@linux.ie>
0008  *  Jesse Barnes <jesse.barnes@intel.com>
0009  */
0010 
0011 #include <linux/i2c.h>
0012 #include <linux/pm_runtime.h>
0013 
0014 #include <asm/intel-mid.h>
0015 
0016 #include <drm/drm_edid.h>
0017 #include <drm/drm_simple_kms_helper.h>
0018 
0019 #include "intel_bios.h"
0020 #include "power.h"
0021 #include "psb_drv.h"
0022 #include "psb_intel_drv.h"
0023 #include "psb_intel_reg.h"
0024 
0025 /* The max/min PWM frequency in BPCR[31:17] - */
0026 /* The smallest number is 1 (not 0) that can fit in the
0027  * 15-bit field of the and then*/
0028 /* shifts to the left by one bit to get the actual 16-bit
0029  * value that the 15-bits correspond to.*/
0030 #define MRST_BLC_MAX_PWM_REG_FREQ       0xFFFF
0031 #define BRIGHTNESS_MAX_LEVEL 100
0032 
0033 /*
0034  * Sets the power state for the panel.
0035  */
0036 static void oaktrail_lvds_set_power(struct drm_device *dev,
0037                 struct gma_encoder *gma_encoder,
0038                 bool on)
0039 {
0040     u32 pp_status;
0041     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0042 
0043     if (!gma_power_begin(dev, true))
0044         return;
0045 
0046     if (on) {
0047         REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
0048               POWER_TARGET_ON);
0049         do {
0050             pp_status = REG_READ(PP_STATUS);
0051         } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
0052         dev_priv->is_lvds_on = true;
0053         if (dev_priv->ops->lvds_bl_power)
0054             dev_priv->ops->lvds_bl_power(dev, true);
0055     } else {
0056         if (dev_priv->ops->lvds_bl_power)
0057             dev_priv->ops->lvds_bl_power(dev, false);
0058         REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
0059               ~POWER_TARGET_ON);
0060         do {
0061             pp_status = REG_READ(PP_STATUS);
0062         } while (pp_status & PP_ON);
0063         dev_priv->is_lvds_on = false;
0064         pm_request_idle(dev->dev);
0065     }
0066     gma_power_end(dev);
0067 }
0068 
0069 static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
0070 {
0071     struct drm_device *dev = encoder->dev;
0072     struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
0073 
0074     if (mode == DRM_MODE_DPMS_ON)
0075         oaktrail_lvds_set_power(dev, gma_encoder, true);
0076     else
0077         oaktrail_lvds_set_power(dev, gma_encoder, false);
0078 
0079     /* XXX: We never power down the LVDS pairs. */
0080 }
0081 
0082 static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
0083                    struct drm_display_mode *mode,
0084                    struct drm_display_mode *adjusted_mode)
0085 {
0086     struct drm_device *dev = encoder->dev;
0087     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0088     struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
0089     struct drm_connector_list_iter conn_iter;
0090     struct drm_connector *connector = NULL;
0091     struct drm_crtc *crtc = encoder->crtc;
0092     u32 lvds_port;
0093     uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
0094 
0095     if (!gma_power_begin(dev, true))
0096         return;
0097 
0098     /*
0099      * The LVDS pin pair will already have been turned on in the
0100      * psb_intel_crtc_mode_set since it has a large impact on the DPLL
0101      * settings.
0102      */
0103     lvds_port = (REG_READ(LVDS) &
0104             (~LVDS_PIPEB_SELECT)) |
0105             LVDS_PORT_EN |
0106             LVDS_BORDER_EN;
0107 
0108     /* If the firmware says dither on Moorestown, or the BIOS does
0109        on Oaktrail then enable dithering */
0110     if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
0111         lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
0112 
0113     REG_WRITE(LVDS, lvds_port);
0114 
0115     /* Find the connector we're trying to set up */
0116     drm_connector_list_iter_begin(dev, &conn_iter);
0117     drm_for_each_connector_iter(connector, &conn_iter) {
0118         if (connector->encoder && connector->encoder->crtc == crtc)
0119             break;
0120     }
0121 
0122     if (!connector) {
0123         drm_connector_list_iter_end(&conn_iter);
0124         DRM_ERROR("Couldn't find connector when setting mode");
0125         gma_power_end(dev);
0126         return;
0127     }
0128 
0129     drm_object_property_get_value( &connector->base,
0130         dev->mode_config.scaling_mode_property, &v);
0131     drm_connector_list_iter_end(&conn_iter);
0132 
0133     if (v == DRM_MODE_SCALE_NO_SCALE)
0134         REG_WRITE(PFIT_CONTROL, 0);
0135     else if (v == DRM_MODE_SCALE_ASPECT) {
0136         if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
0137             (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
0138             if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
0139                 (mode->hdisplay * adjusted_mode->crtc_vdisplay))
0140                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
0141             else if ((adjusted_mode->crtc_hdisplay *
0142                 mode->vdisplay) > (mode->hdisplay *
0143                 adjusted_mode->crtc_vdisplay))
0144                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
0145                       PFIT_SCALING_MODE_PILLARBOX);
0146             else
0147                 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
0148                       PFIT_SCALING_MODE_LETTERBOX);
0149         } else
0150             REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
0151     } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
0152         REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
0153 
0154     gma_power_end(dev);
0155 }
0156 
0157 static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
0158 {
0159     struct drm_device *dev = encoder->dev;
0160     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0161     struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
0162     struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
0163 
0164     if (!gma_power_begin(dev, true))
0165         return;
0166 
0167     mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
0168     mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
0169                       BACKLIGHT_DUTY_CYCLE_MASK);
0170     oaktrail_lvds_set_power(dev, gma_encoder, false);
0171     gma_power_end(dev);
0172 }
0173 
0174 static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
0175 {
0176     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0177     u32 ret;
0178 
0179     if (gma_power_begin(dev, false)) {
0180         ret = ((REG_READ(BLC_PWM_CTL) &
0181               BACKLIGHT_MODULATION_FREQ_MASK) >>
0182               BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
0183 
0184         gma_power_end(dev);
0185     } else
0186         ret = ((dev_priv->regs.saveBLC_PWM_CTL &
0187               BACKLIGHT_MODULATION_FREQ_MASK) >>
0188               BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
0189 
0190     return ret;
0191 }
0192 
0193 static void oaktrail_lvds_commit(struct drm_encoder *encoder)
0194 {
0195     struct drm_device *dev = encoder->dev;
0196     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0197     struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
0198     struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
0199 
0200     if (mode_dev->backlight_duty_cycle == 0)
0201         mode_dev->backlight_duty_cycle =
0202                     oaktrail_lvds_get_max_backlight(dev);
0203     oaktrail_lvds_set_power(dev, gma_encoder, true);
0204 }
0205 
0206 static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
0207     .dpms = oaktrail_lvds_dpms,
0208     .mode_fixup = psb_intel_lvds_mode_fixup,
0209     .prepare = oaktrail_lvds_prepare,
0210     .mode_set = oaktrail_lvds_mode_set,
0211     .commit = oaktrail_lvds_commit,
0212 };
0213 
0214 /* Returns the panel fixed mode from configuration. */
0215 
0216 static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
0217                     struct psb_intel_mode_device *mode_dev)
0218 {
0219     struct drm_display_mode *mode = NULL;
0220     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0221     struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
0222 
0223     mode_dev->panel_fixed_mode = NULL;
0224 
0225     /* Use the firmware provided data on Moorestown */
0226     if (dev_priv->has_gct) {
0227         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
0228         if (!mode)
0229             return;
0230 
0231         mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
0232         mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
0233         mode->hsync_start = mode->hdisplay + \
0234                 ((ti->hsync_offset_hi << 8) | \
0235                 ti->hsync_offset_lo);
0236         mode->hsync_end = mode->hsync_start + \
0237                 ((ti->hsync_pulse_width_hi << 8) | \
0238                 ti->hsync_pulse_width_lo);
0239         mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
0240                             ti->hblank_lo);
0241         mode->vsync_start = \
0242             mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
0243                         ti->vsync_offset_lo);
0244         mode->vsync_end = \
0245             mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
0246                         ti->vsync_pulse_width_lo);
0247         mode->vtotal = mode->vdisplay + \
0248                 ((ti->vblank_hi << 8) | ti->vblank_lo);
0249         mode->clock = ti->pixel_clock * 10;
0250 #if 0
0251         pr_info("hdisplay is %d\n", mode->hdisplay);
0252         pr_info("vdisplay is %d\n", mode->vdisplay);
0253         pr_info("HSS is %d\n", mode->hsync_start);
0254         pr_info("HSE is %d\n", mode->hsync_end);
0255         pr_info("htotal is %d\n", mode->htotal);
0256         pr_info("VSS is %d\n", mode->vsync_start);
0257         pr_info("VSE is %d\n", mode->vsync_end);
0258         pr_info("vtotal is %d\n", mode->vtotal);
0259         pr_info("clock is %d\n", mode->clock);
0260 #endif
0261         mode_dev->panel_fixed_mode = mode;
0262     }
0263 
0264     /* Use the BIOS VBT mode if available */
0265     if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
0266         mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
0267                         mode_dev->vbt_mode);
0268 
0269     /* Then try the LVDS VBT mode */
0270     if (mode_dev->panel_fixed_mode == NULL)
0271         if (dev_priv->lfp_lvds_vbt_mode)
0272             mode_dev->panel_fixed_mode =
0273                 drm_mode_duplicate(dev,
0274                     dev_priv->lfp_lvds_vbt_mode);
0275 
0276     /* If we still got no mode then bail */
0277     if (mode_dev->panel_fixed_mode == NULL)
0278         return;
0279 
0280     drm_mode_set_name(mode_dev->panel_fixed_mode);
0281     drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
0282 }
0283 
0284 /**
0285  * oaktrail_lvds_init - setup LVDS connectors on this device
0286  * @dev: drm device
0287  * @mode_dev: PSB mode device
0288  *
0289  * Create the connector, register the LVDS DDC bus, and try to figure out what
0290  * modes we can display on the LVDS panel (if present).
0291  */
0292 void oaktrail_lvds_init(struct drm_device *dev,
0293             struct psb_intel_mode_device *mode_dev)
0294 {
0295     struct gma_encoder *gma_encoder;
0296     struct gma_connector *gma_connector;
0297     struct gma_i2c_chan *ddc_bus;
0298     struct drm_connector *connector;
0299     struct drm_encoder *encoder;
0300     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0301     struct edid *edid;
0302     struct i2c_adapter *i2c_adap;
0303     struct drm_display_mode *scan;  /* *modes, *bios_mode; */
0304     int ret;
0305 
0306     gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
0307     if (!gma_encoder)
0308         return;
0309 
0310     gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
0311     if (!gma_connector)
0312         goto err_free_encoder;
0313 
0314     connector = &gma_connector->base;
0315     encoder = &gma_encoder->base;
0316     dev_priv->is_lvds_on = true;
0317     ret = drm_connector_init(dev, connector,
0318                  &psb_intel_lvds_connector_funcs,
0319                  DRM_MODE_CONNECTOR_LVDS);
0320     if (ret)
0321         goto err_free_connector;
0322 
0323     ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
0324     if (ret)
0325         goto err_connector_cleanup;
0326 
0327     gma_connector_attach_encoder(gma_connector, gma_encoder);
0328     gma_encoder->type = INTEL_OUTPUT_LVDS;
0329 
0330     drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
0331     drm_connector_helper_add(connector,
0332                  &psb_intel_lvds_connector_helper_funcs);
0333     connector->display_info.subpixel_order = SubPixelHorizontalRGB;
0334     connector->interlace_allowed = false;
0335     connector->doublescan_allowed = false;
0336 
0337     drm_object_attach_property(&connector->base,
0338                     dev->mode_config.scaling_mode_property,
0339                     DRM_MODE_SCALE_FULLSCREEN);
0340     drm_object_attach_property(&connector->base,
0341                     dev_priv->backlight_property,
0342                     BRIGHTNESS_MAX_LEVEL);
0343 
0344     mode_dev->panel_wants_dither = false;
0345     if (dev_priv->has_gct)
0346         mode_dev->panel_wants_dither = (dev_priv->gct_data.
0347             Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
0348         if (dev_priv->lvds_dither)
0349                 mode_dev->panel_wants_dither = 1;
0350 
0351     /*
0352      * LVDS discovery:
0353      * 1) check for EDID on DDC
0354      * 2) check for VBT data
0355      * 3) check to see if LVDS is already on
0356      *    if none of the above, no panel
0357      * 4) make sure lid is open
0358      *    if closed, act like it's not there for now
0359      */
0360 
0361     edid = NULL;
0362     mutex_lock(&dev->mode_config.mutex);
0363 
0364     i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
0365     if (i2c_adap)
0366         edid = drm_get_edid(connector, i2c_adap);
0367 
0368     if (edid == NULL && dev_priv->lpc_gpio_base) {
0369         ddc_bus = oaktrail_lvds_i2c_init(dev);
0370         if (!IS_ERR(ddc_bus)) {
0371             i2c_adap = &ddc_bus->base;
0372             edid = drm_get_edid(connector, i2c_adap);
0373         }
0374     }
0375 
0376     /*
0377      * Due to the logic in probing for i2c buses above we do not know the
0378      * i2c_adap until now. Hence we cannot use drm_connector_init_with_ddc()
0379      * but must instead set connector->ddc manually here.
0380      */
0381     connector->ddc = i2c_adap;
0382 
0383     /*
0384      * Attempt to get the fixed panel mode from DDC.  Assume that the
0385      * preferred mode is the right one.
0386      */
0387     if (edid) {
0388         drm_connector_update_edid_property(connector, edid);
0389         drm_add_edid_modes(connector, edid);
0390         kfree(edid);
0391 
0392         list_for_each_entry(scan, &connector->probed_modes, head) {
0393             if (scan->type & DRM_MODE_TYPE_PREFERRED) {
0394                 mode_dev->panel_fixed_mode =
0395                     drm_mode_duplicate(dev, scan);
0396                 goto out;   /* FIXME: check for quirks */
0397             }
0398         }
0399     } else
0400         dev_err(dev->dev, "No ddc adapter available!\n");
0401     /*
0402      * If we didn't get EDID, try geting panel timing
0403      * from configuration data
0404      */
0405     oaktrail_lvds_get_configuration_mode(dev, mode_dev);
0406 
0407     if (mode_dev->panel_fixed_mode) {
0408         mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
0409         goto out;   /* FIXME: check for quirks */
0410     }
0411 
0412     /* If we still don't have a mode after all that, give up. */
0413     if (!mode_dev->panel_fixed_mode) {
0414         dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
0415         goto err_unlock;
0416     }
0417 
0418 out:
0419     mutex_unlock(&dev->mode_config.mutex);
0420 
0421     return;
0422 
0423 err_unlock:
0424     mutex_unlock(&dev->mode_config.mutex);
0425     gma_i2c_destroy(to_gma_i2c_chan(connector->ddc));
0426     drm_encoder_cleanup(encoder);
0427 err_connector_cleanup:
0428     drm_connector_cleanup(connector);
0429 err_free_connector:
0430     kfree(gma_connector);
0431 err_free_encoder:
0432     kfree(gma_encoder);
0433 }
0434
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