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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**************************************************************************
0003  * Copyright (c) 2011, Intel Corporation.
0004  * All Rights Reserved.
0005  *
0006  **************************************************************************/
0007 
0008 #include <linux/backlight.h>
0009 #include <linux/delay.h>
0010 #include <linux/dmi.h>
0011 #include <linux/module.h>
0012 
0013 #include <drm/drm.h>
0014 
0015 #include "intel_bios.h"
0016 #include "mid_bios.h"
0017 #include "psb_drv.h"
0018 #include "psb_intel_reg.h"
0019 #include "psb_reg.h"
0020 
0021 static int oaktrail_output_init(struct drm_device *dev)
0022 {
0023     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0024     if (dev_priv->iLVDS_enable)
0025         oaktrail_lvds_init(dev, &dev_priv->mode_dev);
0026     else
0027         dev_err(dev->dev, "DSI is not supported\n");
0028     if (dev_priv->hdmi_priv)
0029         oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
0030 
0031     psb_intel_sdvo_init(dev, SDVOB);
0032 
0033     return 0;
0034 }
0035 
0036 /*
0037  *  Provide the low level interfaces for the Moorestown backlight
0038  */
0039 
0040 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
0041 
0042 #define MRST_BLC_MAX_PWM_REG_FREQ       0xFFFF
0043 #define BLC_PWM_PRECISION_FACTOR 100    /* 10000000 */
0044 #define BLC_PWM_FREQ_CALC_CONSTANT 32
0045 #define MHz 1000000
0046 #define BLC_ADJUSTMENT_MAX 100
0047 
0048 static struct backlight_device *oaktrail_backlight_device;
0049 static int oaktrail_brightness;
0050 
0051 static int oaktrail_set_brightness(struct backlight_device *bd)
0052 {
0053     struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
0054     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0055     int level = bd->props.brightness;
0056     u32 blc_pwm_ctl;
0057     u32 max_pwm_blc;
0058 
0059     /* Percentage 1-100% being valid */
0060     if (level < 1)
0061         level = 1;
0062 
0063     if (gma_power_begin(dev, 0)) {
0064         /* Calculate and set the brightness value */
0065         max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
0066         blc_pwm_ctl = level * max_pwm_blc / 100;
0067 
0068         /* Adjust the backlight level with the percent in
0069          * dev_priv->blc_adj1;
0070          */
0071         blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
0072         blc_pwm_ctl = blc_pwm_ctl / 100;
0073 
0074         /* Adjust the backlight level with the percent in
0075          * dev_priv->blc_adj2;
0076          */
0077         blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
0078         blc_pwm_ctl = blc_pwm_ctl / 100;
0079 
0080         /* force PWM bit on */
0081         REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
0082         REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
0083         gma_power_end(dev);
0084     }
0085     oaktrail_brightness = level;
0086     return 0;
0087 }
0088 
0089 static int oaktrail_get_brightness(struct backlight_device *bd)
0090 {
0091     /* return locally cached var instead of HW read (due to DPST etc.) */
0092     /* FIXME: ideally return actual value in case firmware fiddled with
0093        it */
0094     return oaktrail_brightness;
0095 }
0096 
0097 static int device_backlight_init(struct drm_device *dev)
0098 {
0099     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0100     unsigned long core_clock;
0101     u16 bl_max_freq;
0102     uint32_t value;
0103     uint32_t blc_pwm_precision_factor;
0104 
0105     dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
0106     dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
0107     bl_max_freq = 256;
0108     /* this needs to be set elsewhere */
0109     blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
0110 
0111     core_clock = dev_priv->core_freq;
0112 
0113     value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
0114     value *= blc_pwm_precision_factor;
0115     value /= bl_max_freq;
0116     value /= blc_pwm_precision_factor;
0117 
0118     if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
0119             return -ERANGE;
0120 
0121     if (gma_power_begin(dev, false)) {
0122         REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
0123         REG_WRITE(BLC_PWM_CTL, value | (value << 16));
0124         gma_power_end(dev);
0125     }
0126     return 0;
0127 }
0128 
0129 static const struct backlight_ops oaktrail_ops = {
0130     .get_brightness = oaktrail_get_brightness,
0131     .update_status  = oaktrail_set_brightness,
0132 };
0133 
0134 static int oaktrail_backlight_init(struct drm_device *dev)
0135 {
0136     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0137     int ret;
0138     struct backlight_properties props;
0139 
0140     memset(&props, 0, sizeof(struct backlight_properties));
0141     props.max_brightness = 100;
0142     props.type = BACKLIGHT_PLATFORM;
0143 
0144     oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
0145                 NULL, (void *)dev, &oaktrail_ops, &props);
0146 
0147     if (IS_ERR(oaktrail_backlight_device))
0148         return PTR_ERR(oaktrail_backlight_device);
0149 
0150     ret = device_backlight_init(dev);
0151     if (ret < 0) {
0152         backlight_device_unregister(oaktrail_backlight_device);
0153         return ret;
0154     }
0155     oaktrail_backlight_device->props.brightness = 100;
0156     oaktrail_backlight_device->props.max_brightness = 100;
0157     backlight_update_status(oaktrail_backlight_device);
0158     dev_priv->backlight_device = oaktrail_backlight_device;
0159     return 0;
0160 }
0161 
0162 #endif
0163 
0164 /*
0165  *  Provide the Moorestown specific chip logic and low level methods
0166  *  for power management
0167  */
0168 
0169 /**
0170  *  oaktrail_save_display_registers -   save registers lost on suspend
0171  *  @dev: our DRM device
0172  *
0173  *  Save the state we need in order to be able to restore the interface
0174  *  upon resume from suspend
0175  */
0176 static int oaktrail_save_display_registers(struct drm_device *dev)
0177 {
0178     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0179     struct psb_save_area *regs = &dev_priv->regs;
0180     struct psb_pipe *p = &regs->pipe[0];
0181     int i;
0182     u32 pp_stat;
0183 
0184     /* Display arbitration control + watermarks */
0185     regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
0186     regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
0187     regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
0188     regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
0189     regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
0190     regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
0191     regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
0192     regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
0193 
0194     /* Pipe & plane A info */
0195     p->conf = PSB_RVDC32(PIPEACONF);
0196     p->src = PSB_RVDC32(PIPEASRC);
0197     p->fp0 = PSB_RVDC32(MRST_FPA0);
0198     p->fp1 = PSB_RVDC32(MRST_FPA1);
0199     p->dpll = PSB_RVDC32(MRST_DPLL_A);
0200     p->htotal = PSB_RVDC32(HTOTAL_A);
0201     p->hblank = PSB_RVDC32(HBLANK_A);
0202     p->hsync = PSB_RVDC32(HSYNC_A);
0203     p->vtotal = PSB_RVDC32(VTOTAL_A);
0204     p->vblank = PSB_RVDC32(VBLANK_A);
0205     p->vsync = PSB_RVDC32(VSYNC_A);
0206     regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
0207     p->cntr = PSB_RVDC32(DSPACNTR);
0208     p->stride = PSB_RVDC32(DSPASTRIDE);
0209     p->addr = PSB_RVDC32(DSPABASE);
0210     p->surf = PSB_RVDC32(DSPASURF);
0211     p->linoff = PSB_RVDC32(DSPALINOFF);
0212     p->tileoff = PSB_RVDC32(DSPATILEOFF);
0213 
0214     /* Save cursor regs */
0215     regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
0216     regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
0217     regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
0218 
0219     /* Save palette (gamma) */
0220     for (i = 0; i < 256; i++)
0221         p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
0222 
0223     if (dev_priv->hdmi_priv)
0224         oaktrail_hdmi_save(dev);
0225 
0226     /* Save performance state */
0227     regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
0228 
0229     /* LVDS state */
0230     regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
0231     regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
0232     regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
0233     regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
0234     regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
0235     regs->psb.saveLVDS = PSB_RVDC32(LVDS);
0236     regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
0237     regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
0238     regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
0239     regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
0240 
0241     /* HW overlay */
0242     regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
0243     regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
0244     regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
0245     regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
0246     regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
0247     regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
0248     regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
0249 
0250     /* DPST registers */
0251     regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
0252                     PSB_RVDC32(HISTOGRAM_INT_CONTROL);
0253     regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
0254                     PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
0255     regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
0256 
0257     if (dev_priv->iLVDS_enable) {
0258         /* Shut down the panel */
0259         PSB_WVDC32(0, PP_CONTROL);
0260 
0261         do {
0262             pp_stat = PSB_RVDC32(PP_STATUS);
0263         } while (pp_stat & 0x80000000);
0264 
0265         /* Turn off the plane */
0266         PSB_WVDC32(0x58000000, DSPACNTR);
0267         /* Trigger the plane disable */
0268         PSB_WVDC32(0, DSPASURF);
0269 
0270         /* Wait ~4 ticks */
0271         msleep(4);
0272 
0273         /* Turn off pipe */
0274         PSB_WVDC32(0x0, PIPEACONF);
0275         /* Wait ~8 ticks */
0276         msleep(8);
0277 
0278         /* Turn off PLLs */
0279         PSB_WVDC32(0, MRST_DPLL_A);
0280     }
0281     return 0;
0282 }
0283 
0284 /**
0285  *  oaktrail_restore_display_registers  -   restore lost register state
0286  *  @dev: our DRM device
0287  *
0288  *  Restore register state that was lost during suspend and resume.
0289  */
0290 static int oaktrail_restore_display_registers(struct drm_device *dev)
0291 {
0292     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0293     struct psb_save_area *regs = &dev_priv->regs;
0294     struct psb_pipe *p = &regs->pipe[0];
0295     u32 pp_stat;
0296     int i;
0297 
0298     /* Display arbitration + watermarks */
0299     PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
0300     PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
0301     PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
0302     PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
0303     PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
0304     PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
0305     PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
0306     PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
0307 
0308     /* Make sure VGA plane is off. it initializes to on after reset!*/
0309     PSB_WVDC32(0x80000000, VGACNTRL);
0310 
0311     /* set the plls */
0312     PSB_WVDC32(p->fp0, MRST_FPA0);
0313     PSB_WVDC32(p->fp1, MRST_FPA1);
0314 
0315     /* Actually enable it */
0316     PSB_WVDC32(p->dpll, MRST_DPLL_A);
0317     udelay(150);
0318 
0319     /* Restore mode */
0320     PSB_WVDC32(p->htotal, HTOTAL_A);
0321     PSB_WVDC32(p->hblank, HBLANK_A);
0322     PSB_WVDC32(p->hsync, HSYNC_A);
0323     PSB_WVDC32(p->vtotal, VTOTAL_A);
0324     PSB_WVDC32(p->vblank, VBLANK_A);
0325     PSB_WVDC32(p->vsync, VSYNC_A);
0326     PSB_WVDC32(p->src, PIPEASRC);
0327     PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
0328 
0329     /* Restore performance mode*/
0330     PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
0331 
0332     /* Enable the pipe*/
0333     if (dev_priv->iLVDS_enable)
0334         PSB_WVDC32(p->conf, PIPEACONF);
0335 
0336     /* Set up the plane*/
0337     PSB_WVDC32(p->linoff, DSPALINOFF);
0338     PSB_WVDC32(p->stride, DSPASTRIDE);
0339     PSB_WVDC32(p->tileoff, DSPATILEOFF);
0340 
0341     /* Enable the plane */
0342     PSB_WVDC32(p->cntr, DSPACNTR);
0343     PSB_WVDC32(p->surf, DSPASURF);
0344 
0345     /* Enable Cursor A */
0346     PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
0347     PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
0348     PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
0349 
0350     /* Restore palette (gamma) */
0351     for (i = 0; i < 256; i++)
0352         PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
0353 
0354     if (dev_priv->hdmi_priv)
0355         oaktrail_hdmi_restore(dev);
0356 
0357     if (dev_priv->iLVDS_enable) {
0358         PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
0359         PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
0360         PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
0361         PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
0362         PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
0363         PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
0364         PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
0365         PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
0366         PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
0367         PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
0368     }
0369 
0370     /* Wait for cycle delay */
0371     do {
0372         pp_stat = PSB_RVDC32(PP_STATUS);
0373     } while (pp_stat & 0x08000000);
0374 
0375     /* Wait for panel power up */
0376     do {
0377         pp_stat = PSB_RVDC32(PP_STATUS);
0378     } while (pp_stat & 0x10000000);
0379 
0380     /* Restore HW overlay */
0381     PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
0382     PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
0383     PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
0384     PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
0385     PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
0386     PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
0387     PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
0388 
0389     /* DPST registers */
0390     PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
0391                         HISTOGRAM_INT_CONTROL);
0392     PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
0393                         HISTOGRAM_LOGIC_CONTROL);
0394     PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
0395 
0396     return 0;
0397 }
0398 
0399 /**
0400  *  oaktrail_power_down -   power down the display island
0401  *  @dev: our DRM device
0402  *
0403  *  Power down the display interface of our device
0404  */
0405 static int oaktrail_power_down(struct drm_device *dev)
0406 {
0407     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0408     u32 pwr_mask ;
0409     u32 pwr_sts;
0410 
0411     pwr_mask = PSB_PWRGT_DISPLAY_MASK;
0412     outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
0413 
0414     while (true) {
0415         pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
0416         if ((pwr_sts & pwr_mask) == pwr_mask)
0417             break;
0418         else
0419             udelay(10);
0420     }
0421     return 0;
0422 }
0423 
0424 /*
0425  * oaktrail_power_up
0426  *
0427  * Restore power to the specified island(s) (powergating)
0428  */
0429 static int oaktrail_power_up(struct drm_device *dev)
0430 {
0431     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0432     u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
0433     u32 pwr_sts, pwr_cnt;
0434 
0435     pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
0436     pwr_cnt &= ~pwr_mask;
0437     outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
0438 
0439     while (true) {
0440         pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
0441         if ((pwr_sts & pwr_mask) == 0)
0442             break;
0443         else
0444             udelay(10);
0445     }
0446     return 0;
0447 }
0448 
0449 /* Oaktrail */
0450 static const struct psb_offset oaktrail_regmap[2] = {
0451     {
0452         .fp0 = MRST_FPA0,
0453         .fp1 = MRST_FPA1,
0454         .cntr = DSPACNTR,
0455         .conf = PIPEACONF,
0456         .src = PIPEASRC,
0457         .dpll = MRST_DPLL_A,
0458         .htotal = HTOTAL_A,
0459         .hblank = HBLANK_A,
0460         .hsync = HSYNC_A,
0461         .vtotal = VTOTAL_A,
0462         .vblank = VBLANK_A,
0463         .vsync = VSYNC_A,
0464         .stride = DSPASTRIDE,
0465         .size = DSPASIZE,
0466         .pos = DSPAPOS,
0467         .surf = DSPASURF,
0468         .addr = MRST_DSPABASE,
0469         .base = MRST_DSPABASE,
0470         .status = PIPEASTAT,
0471         .linoff = DSPALINOFF,
0472         .tileoff = DSPATILEOFF,
0473         .palette = PALETTE_A,
0474     },
0475     {
0476         .fp0 = FPB0,
0477         .fp1 = FPB1,
0478         .cntr = DSPBCNTR,
0479         .conf = PIPEBCONF,
0480         .src = PIPEBSRC,
0481         .dpll = DPLL_B,
0482         .htotal = HTOTAL_B,
0483         .hblank = HBLANK_B,
0484         .hsync = HSYNC_B,
0485         .vtotal = VTOTAL_B,
0486         .vblank = VBLANK_B,
0487         .vsync = VSYNC_B,
0488         .stride = DSPBSTRIDE,
0489         .size = DSPBSIZE,
0490         .pos = DSPBPOS,
0491         .surf = DSPBSURF,
0492         .addr = DSPBBASE,
0493         .base = DSPBBASE,
0494         .status = PIPEBSTAT,
0495         .linoff = DSPBLINOFF,
0496         .tileoff = DSPBTILEOFF,
0497         .palette = PALETTE_B,
0498     },
0499 };
0500 
0501 static int oaktrail_chip_setup(struct drm_device *dev)
0502 {
0503     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0504     int ret;
0505 
0506     dev_priv->use_msi = true;
0507     dev_priv->regmap = oaktrail_regmap;
0508 
0509     ret = mid_chip_setup(dev);
0510     if (ret < 0)
0511         return ret;
0512     if (!dev_priv->has_gct) {
0513         /* Now pull the BIOS data */
0514         psb_intel_opregion_init(dev);
0515         psb_intel_init_bios(dev);
0516     }
0517     gma_intel_setup_gmbus(dev);
0518     oaktrail_hdmi_setup(dev);
0519     return 0;
0520 }
0521 
0522 static void oaktrail_teardown(struct drm_device *dev)
0523 {
0524     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0525 
0526     gma_intel_teardown_gmbus(dev);
0527     oaktrail_hdmi_teardown(dev);
0528     if (!dev_priv->has_gct)
0529         psb_intel_destroy_bios(dev);
0530 }
0531 
0532 const struct psb_ops oaktrail_chip_ops = {
0533     .name = "Oaktrail",
0534     .pipes = 2,
0535     .crtcs = 2,
0536     .hdmi_mask = (1 << 1),
0537     .lvds_mask = (1 << 0),
0538     .sdvo_mask = (1 << 1),
0539     .cursor_needs_phys = 0,
0540     .sgx_offset = MRST_SGX_OFFSET,
0541 
0542     .chip_setup = oaktrail_chip_setup,
0543     .chip_teardown = oaktrail_teardown,
0544     .crtc_helper = &oaktrail_helper_funcs,
0545 
0546     .output_init = oaktrail_output_init,
0547 
0548 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
0549     .backlight_init = oaktrail_backlight_init,
0550 #endif
0551 
0552     .save_regs = oaktrail_save_display_registers,
0553     .restore_regs = oaktrail_restore_display_registers,
0554     .save_crtc = gma_crtc_save,
0555     .restore_crtc = gma_crtc_restore,
0556     .power_down = oaktrail_power_down,
0557     .power_up = oaktrail_power_up,
0558 
0559     .i2c_bus = 1,
0560 };
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