drm/gma500/oaktrail.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /**************************************************************************
0003  * Copyright (c) 2007-2011, Intel Corporation.
0004  * All Rights Reserved.
0005  *
0006  **************************************************************************/
0007
0008 struct psb_intel_mode_device;
0009
0010 /* MID device specific descriptors */
0011
0012 struct oaktrail_timing_info {
0013     u16 pixel_clock;
0014     u8 hactive_lo;
0015     u8 hblank_lo;
0016     u8 hblank_hi:4;
0017     u8 hactive_hi:4;
0018     u8 vactive_lo;
0019     u8 vblank_lo;
0020     u8 vblank_hi:4;
0021     u8 vactive_hi:4;
0022     u8 hsync_offset_lo;
0023     u8 hsync_pulse_width_lo;
0024     u8 vsync_pulse_width_lo:4;
0025     u8 vsync_offset_lo:4;
0026     u8 vsync_pulse_width_hi:2;
0027     u8 vsync_offset_hi:2;
0028     u8 hsync_pulse_width_hi:2;
0029     u8 hsync_offset_hi:2;
0030     u8 width_mm_lo;
0031     u8 height_mm_lo;
0032     u8 height_mm_hi:4;
0033     u8 width_mm_hi:4;
0034     u8 hborder;
0035     u8 vborder;
0036     u8 unknown0:1;
0037     u8 hsync_positive:1;
0038     u8 vsync_positive:1;
0039     u8 separate_sync:2;
0040     u8 stereo:1;
0041     u8 unknown6:1;
0042     u8 interlaced:1;
0043 } __packed;
0044
0045 struct gct_r10_timing_info {
0046     u16 pixel_clock;
0047     u32 hactive_lo:8;
0048     u32 hactive_hi:4;
0049     u32 hblank_lo:8;
0050     u32 hblank_hi:4;
0051     u32 hsync_offset_lo:8;
0052     u16 hsync_offset_hi:2;
0053     u16 hsync_pulse_width_lo:8;
0054     u16 hsync_pulse_width_hi:2;
0055     u16 hsync_positive:1;
0056     u16 rsvd_1:3;
0057     u8  vactive_lo:8;
0058     u16 vactive_hi:4;
0059     u16 vblank_lo:8;
0060     u16 vblank_hi:4;
0061     u16 vsync_offset_lo:4;
0062     u16 vsync_offset_hi:2;
0063     u16 vsync_pulse_width_lo:4;
0064     u16 vsync_pulse_width_hi:2;
0065     u16 vsync_positive:1;
0066     u16 rsvd_2:3;
0067 } __packed;
0068
0069 struct oaktrail_panel_descriptor_v1 {
0070     u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
0071                 /* 0x61190 if MIPI */
0072     u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
0073     u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
0074     u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
0075                         /* Register 0x61210 */
0076     struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
0077     u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
0078                 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
0079             /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
0080     u16 Panel_MIPI_Display_Descriptor;
0081             /*16 bits, Defined as follows: */
0082             /* if MIPI, 0x0000 if LVDS */
0083             /* Bit 0, Type, 2 bits, */
0084             /* 0: Type-1, */
0085             /* 1: Type-2, */
0086             /* 2: Type-3, */
0087             /* 3: Type-4 */
0088             /* Bit 2, Pixel Format, 4 bits */
0089             /* Bit0: 16bpp (not supported in LNC), */
0090             /* Bit1: 18bpp loosely packed, */
0091             /* Bit2: 18bpp packed, */
0092             /* Bit3: 24bpp */
0093             /* Bit 6, Reserved, 2 bits, 00b */
0094             /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
0095             /* Bit 14, Reserved, 2 bits, 00b */
0096 } __packed;
0097
0098 struct oaktrail_panel_descriptor_v2 {
0099     u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
0100                 /* 0x61190 if MIPI */
0101     u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
0102     u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
0103     u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
0104                         /* Register 0x61210 */
0105     struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
0106     u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
0107                 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
0108     u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
0109             /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
0110     u16 Panel_MIPI_Display_Descriptor;
0111             /*16 bits, Defined as follows: */
0112             /* if MIPI, 0x0000 if LVDS */
0113             /* Bit 0, Type, 2 bits, */
0114             /* 0: Type-1, */
0115             /* 1: Type-2, */
0116             /* 2: Type-3, */
0117             /* 3: Type-4 */
0118             /* Bit 2, Pixel Format, 4 bits */
0119             /* Bit0: 16bpp (not supported in LNC), */
0120             /* Bit1: 18bpp loosely packed, */
0121             /* Bit2: 18bpp packed, */
0122             /* Bit3: 24bpp */
0123             /* Bit 6, Reserved, 2 bits, 00b */
0124             /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
0125             /* Bit 14, Reserved, 2 bits, 00b */
0126 } __packed;
0127
0128 union oaktrail_panel_rx {
0129     struct {
0130         u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
0131             /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
0132         u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
0133         /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
0134         u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
0135                     /* 1: Burst and non-burst */
0136                     /* 2/3: Reserved */
0137         u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
0138         u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
0139         u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
0140         u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
0141         u16 Rsvd:5;/*5 bits,00000b */
0142     } panelrx;
0143     u16 panel_receiver;
0144 } __packed;
0145
0146 struct gct_r0 {
0147     union { /*8 bits,Defined as follows: */
0148         struct {
0149             u8 PanelType:4; /*4 bits, Bit field for panels*/
0150                     /* 0 - 3: 0 = LVDS, 1 = MIPI*/
0151                     /*2 bits,Specifies which of the*/
0152             u8 BootPanelIndex:2;
0153                     /* 4 panels to use by default*/
0154             u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
0155                     /* the 4 MIPI DSI receivers to use*/
0156         } PD;
0157         u8 PanelDescriptor;
0158     };
0159     struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
0160     union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
0161 } __packed;
0162
0163 struct gct_r1 {
0164     union { /*8 bits,Defined as follows: */
0165         struct {
0166             u8 PanelType:4; /*4 bits, Bit field for panels*/
0167                     /* 0 - 3: 0 = LVDS, 1 = MIPI*/
0168                     /*2 bits,Specifies which of the*/
0169             u8 BootPanelIndex:2;
0170                     /* 4 panels to use by default*/
0171             u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
0172                     /* the 4 MIPI DSI receivers to use*/
0173         } PD;
0174         u8 PanelDescriptor;
0175     };
0176     struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
0177     union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
0178 } __packed;
0179
0180 struct gct_r10 {
0181     struct gct_r10_timing_info DTD;
0182     u16 Panel_MIPI_Display_Descriptor;
0183     u16 Panel_MIPI_Receiver_Descriptor;
0184     u16 Panel_Backlight_Inverter_Descriptor;
0185     u8 Panel_Initial_Brightness;
0186     u32 MIPI_Ctlr_Init_ptr;
0187     u32 MIPI_Panel_Init_ptr;
0188 } __packed;
0189
0190 struct oaktrail_gct_data {
0191     u8 bpi; /* boot panel index, number of panel used during boot */
0192     u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
0193     struct oaktrail_timing_info DTD; /* timing info for the selected panel */
0194     u32 Panel_Port_Control;
0195     u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
0196     u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
0197     u32 PP_Cycle_Delay;
0198     u16 Panel_Backlight_Inverter_Descriptor;
0199     u16 Panel_MIPI_Display_Descriptor;
0200 } __packed;
0201
0202 #define MODE_SETTING_IN_CRTC        0x1
0203 #define MODE_SETTING_IN_ENCODER     0x2
0204 #define MODE_SETTING_ON_GOING       0x3
0205 #define MODE_SETTING_IN_DSR     0x4
0206 #define MODE_SETTING_ENCODER_DONE   0x8
0207
0208 /*
0209  *  Moorestown HDMI interfaces
0210  */
0211
0212 struct oaktrail_hdmi_dev {
0213     struct pci_dev *dev;
0214     void __iomem *regs;
0215     unsigned int mmio, mmio_len;
0216     int dpms_mode;
0217     struct hdmi_i2c_dev *i2c_dev;
0218
0219     /* register state */
0220     u32 saveDPLL_CTRL;
0221     u32 saveDPLL_DIV_CTRL;
0222     u32 saveDPLL_ADJUST;
0223     u32 saveDPLL_UPDATE;
0224     u32 saveDPLL_CLK_ENABLE;
0225     u32 savePCH_HTOTAL_B;
0226     u32 savePCH_HBLANK_B;
0227     u32 savePCH_HSYNC_B;
0228     u32 savePCH_VTOTAL_B;
0229     u32 savePCH_VBLANK_B;
0230     u32 savePCH_VSYNC_B;
0231     u32 savePCH_PIPEBCONF;
0232     u32 savePCH_PIPEBSRC;
0233 };
0234
0235 extern void oaktrail_hdmi_setup(struct drm_device *dev);
0236 extern void oaktrail_hdmi_teardown(struct drm_device *dev);
0237 extern int  oaktrail_hdmi_i2c_init(struct pci_dev *dev);
0238 extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
0239 extern void oaktrail_hdmi_save(struct drm_device *dev);
0240 extern void oaktrail_hdmi_restore(struct drm_device *dev);
0241 extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);
0242 extern int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
0243                         struct drm_display_mode *adjusted_mode, int x, int y,
0244                         struct drm_framebuffer *old_fb);
0245 extern void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode);
0246
0247