drm/gma500/mid_bios.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**************************************************************************
0003  * Copyright (c) 2011, Intel Corporation.
0004  * All Rights Reserved.
0005  *
0006  **************************************************************************/
0007
0008 /* TODO
0009  * - Split functions by vbt type
0010  * - Make them all take drm_device
0011  * - Check ioremap failures
0012  */
0013
0014 #include <drm/drm.h>
0015
0016 #include "mid_bios.h"
0017 #include "psb_drv.h"
0018
0019 static void mid_get_fuse_settings(struct drm_device *dev)
0020 {
0021     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0022     struct pci_dev *pdev = to_pci_dev(dev->dev);
0023     struct pci_dev *pci_root =
0024         pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
0025                         0, 0);
0026     uint32_t fuse_value = 0;
0027     uint32_t fuse_value_tmp = 0;
0028
0029 #define FB_REG06 0xD0810600
0030 #define FB_MIPI_DISABLE  (1 << 11)
0031 #define FB_REG09 0xD0810900
0032 #define FB_SKU_MASK  0x7000
0033 #define FB_SKU_SHIFT 12
0034 #define FB_SKU_100 0
0035 #define FB_SKU_100L 1
0036 #define FB_SKU_83 2
0037     if (pci_root == NULL) {
0038         WARN_ON(1);
0039         return;
0040     }
0041
0042
0043     pci_write_config_dword(pci_root, 0xD0, FB_REG06);
0044     pci_read_config_dword(pci_root, 0xD4, &fuse_value);
0045
0046     /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
0047     if (IS_MRST(dev))
0048         dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
0049
0050     DRM_INFO("internal display is %s\n",
0051          dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
0052
0053      /* Prevent runtime suspend at start*/
0054      if (dev_priv->iLVDS_enable) {
0055         dev_priv->is_lvds_on = true;
0056         dev_priv->is_mipi_on = false;
0057     } else {
0058         dev_priv->is_mipi_on = true;
0059         dev_priv->is_lvds_on = false;
0060     }
0061
0062     dev_priv->video_device_fuse = fuse_value;
0063
0064     pci_write_config_dword(pci_root, 0xD0, FB_REG09);
0065     pci_read_config_dword(pci_root, 0xD4, &fuse_value);
0066
0067     dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
0068     fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
0069
0070     dev_priv->fuse_reg_value = fuse_value;
0071
0072     switch (fuse_value_tmp) {
0073     case FB_SKU_100:
0074         dev_priv->core_freq = 200;
0075         break;
0076     case FB_SKU_100L:
0077         dev_priv->core_freq = 100;
0078         break;
0079     case FB_SKU_83:
0080         dev_priv->core_freq = 166;
0081         break;
0082     default:
0083         dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
0084                                 fuse_value_tmp);
0085         dev_priv->core_freq = 0;
0086     }
0087     dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
0088     pci_dev_put(pci_root);
0089 }
0090
0091 /*
0092  *  Get the revison ID, B0:D2:F0;0x08
0093  */
0094 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
0095 {
0096     uint32_t platform_rev_id = 0;
0097     struct pci_dev *pdev = to_pci_dev(dev_priv->dev.dev);
0098     int domain = pci_domain_nr(pdev->bus);
0099     struct pci_dev *pci_gfx_root =
0100         pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
0101
0102     if (pci_gfx_root == NULL) {
0103         WARN_ON(1);
0104         return;
0105     }
0106     pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
0107     dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
0108     pci_dev_put(pci_gfx_root);
0109     dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id);
0110 }
0111
0112 struct mid_vbt_header {
0113     u32 signature;
0114     u8 revision;
0115 } __packed;
0116
0117 /* The same for r0 and r1 */
0118 struct vbt_r0 {
0119     struct mid_vbt_header vbt_header;
0120     u8 size;
0121     u8 checksum;
0122 } __packed;
0123
0124 struct vbt_r10 {
0125     struct mid_vbt_header vbt_header;
0126     u8 checksum;
0127     u16 size;
0128     u8 panel_count;
0129     u8 primary_panel_idx;
0130     u8 secondary_panel_idx;
0131     u8 __reserved[5];
0132 } __packed;
0133
0134 static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
0135 {
0136     void __iomem *vbt_virtual;
0137
0138     vbt_virtual = ioremap(addr, sizeof(*vbt));
0139     if (vbt_virtual == NULL)
0140         return -1;
0141
0142     memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
0143     iounmap(vbt_virtual);
0144
0145     return 0;
0146 }
0147
0148 static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
0149 {
0150     void __iomem *vbt_virtual;
0151
0152     vbt_virtual = ioremap(addr, sizeof(*vbt));
0153     if (!vbt_virtual)
0154         return -1;
0155
0156     memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
0157     iounmap(vbt_virtual);
0158
0159     return 0;
0160 }
0161
0162 static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
0163 {
0164     struct vbt_r0 vbt;
0165     void __iomem *gct_virtual;
0166     struct gct_r0 gct;
0167     u8 bpi;
0168
0169     if (read_vbt_r0(addr, &vbt))
0170         return -1;
0171
0172     gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
0173     if (!gct_virtual)
0174         return -1;
0175     memcpy_fromio(&gct, gct_virtual, sizeof(gct));
0176     iounmap(gct_virtual);
0177
0178     bpi = gct.PD.BootPanelIndex;
0179     dev_priv->gct_data.bpi = bpi;
0180     dev_priv->gct_data.pt = gct.PD.PanelType;
0181     dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
0182     dev_priv->gct_data.Panel_Port_Control =
0183         gct.panel[bpi].Panel_Port_Control;
0184     dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
0185         gct.panel[bpi].Panel_MIPI_Display_Descriptor;
0186
0187     return 0;
0188 }
0189
0190 static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
0191 {
0192     struct vbt_r0 vbt;
0193     void __iomem *gct_virtual;
0194     struct gct_r1 gct;
0195     u8 bpi;
0196
0197     if (read_vbt_r0(addr, &vbt))
0198         return -1;
0199
0200     gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
0201     if (!gct_virtual)
0202         return -1;
0203     memcpy_fromio(&gct, gct_virtual, sizeof(gct));
0204     iounmap(gct_virtual);
0205
0206     bpi = gct.PD.BootPanelIndex;
0207     dev_priv->gct_data.bpi = bpi;
0208     dev_priv->gct_data.pt = gct.PD.PanelType;
0209     dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
0210     dev_priv->gct_data.Panel_Port_Control =
0211         gct.panel[bpi].Panel_Port_Control;
0212     dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
0213         gct.panel[bpi].Panel_MIPI_Display_Descriptor;
0214
0215     return 0;
0216 }
0217
0218 static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
0219 {
0220     struct vbt_r10 vbt;
0221     void __iomem *gct_virtual;
0222     struct gct_r10 *gct;
0223     struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
0224     struct gct_r10_timing_info *ti;
0225     int ret = -1;
0226
0227     if (read_vbt_r10(addr, &vbt))
0228         return -1;
0229
0230     gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
0231     if (!gct)
0232         return -ENOMEM;
0233
0234     gct_virtual = ioremap(addr + sizeof(vbt),
0235             sizeof(*gct) * vbt.panel_count);
0236     if (!gct_virtual)
0237         goto out;
0238     memcpy_fromio(gct, gct_virtual, sizeof(*gct));
0239     iounmap(gct_virtual);
0240
0241     dev_priv->gct_data.bpi = vbt.primary_panel_idx;
0242     dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
0243         gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
0244
0245     ti = &gct[vbt.primary_panel_idx].DTD;
0246     dp_ti->pixel_clock = ti->pixel_clock;
0247     dp_ti->hactive_hi = ti->hactive_hi;
0248     dp_ti->hactive_lo = ti->hactive_lo;
0249     dp_ti->hblank_hi = ti->hblank_hi;
0250     dp_ti->hblank_lo = ti->hblank_lo;
0251     dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
0252     dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
0253     dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
0254     dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
0255     dp_ti->vactive_hi = ti->vactive_hi;
0256     dp_ti->vactive_lo = ti->vactive_lo;
0257     dp_ti->vblank_hi = ti->vblank_hi;
0258     dp_ti->vblank_lo = ti->vblank_lo;
0259     dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
0260     dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
0261     dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
0262     dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
0263
0264     ret = 0;
0265 out:
0266     kfree(gct);
0267     return ret;
0268 }
0269
0270 static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
0271 {
0272     struct drm_device *dev = &dev_priv->dev;
0273     struct pci_dev *pdev = to_pci_dev(dev->dev);
0274     u32 addr;
0275     u8 __iomem *vbt_virtual;
0276     struct mid_vbt_header vbt_header;
0277     struct pci_dev *pci_gfx_root =
0278         pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
0279                         0, PCI_DEVFN(2, 0));
0280     int ret = -1;
0281
0282     /* Get the address of the platform config vbt */
0283     pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
0284     pci_dev_put(pci_gfx_root);
0285
0286     dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
0287
0288     if (!addr)
0289         goto out;
0290
0291     /* get the virtual address of the vbt */
0292     vbt_virtual = ioremap(addr, sizeof(vbt_header));
0293     if (!vbt_virtual)
0294         goto out;
0295
0296     memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
0297     iounmap(vbt_virtual);
0298
0299     if (memcmp(&vbt_header.signature, "$GCT", 4))
0300         goto out;
0301
0302     dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
0303
0304     switch (vbt_header.revision) {
0305     case 0x00:
0306         ret = mid_get_vbt_data_r0(dev_priv, addr);
0307         break;
0308     case 0x01:
0309         ret = mid_get_vbt_data_r1(dev_priv, addr);
0310         break;
0311     case 0x10:
0312         ret = mid_get_vbt_data_r10(dev_priv, addr);
0313         break;
0314     default:
0315         dev_err(dev->dev, "Unknown revision of GCT!\n");
0316     }
0317
0318 out:
0319     if (ret)
0320         dev_err(dev->dev, "Unable to read GCT!");
0321     else
0322         dev_priv->has_gct = true;
0323 }
0324
0325 int mid_chip_setup(struct drm_device *dev)
0326 {
0327     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0328     mid_get_fuse_settings(dev);
0329     mid_get_vbt_data(dev_priv);
0330     mid_get_pci_revID(dev_priv);
0331     return 0;
0332 }