drm/gma500/intel_gmbus.c

0001 /*
0002  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
0003  * Copyright © 2006-2008,2010 Intel Corporation
0004  *   Jesse Barnes <jesse.barnes@intel.com>
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the next
0014  * paragraph) shall be included in all copies or substantial portions of the
0015  * Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0018  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0019  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0020  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0021  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0022  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0023  * DEALINGS IN THE SOFTWARE.
0024  *
0025  * Authors:
0026  *  Eric Anholt <eric@anholt.net>
0027  *  Chris Wilson <chris@chris-wilson.co.uk>
0028  */
0029
0030 #include <linux/delay.h>
0031 #include <linux/i2c-algo-bit.h>
0032 #include <linux/i2c.h>
0033 #include <linux/module.h>
0034
0035 #include "psb_drv.h"
0036 #include "psb_intel_drv.h"
0037 #include "psb_intel_reg.h"
0038
0039 #define _wait_for(COND, MS, W) ({ \
0040     unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);   \
0041     int ret__ = 0;                          \
0042     while (! (COND)) {                      \
0043         if (time_after(jiffies, timeout__)) {           \
0044             ret__ = -ETIMEDOUT;             \
0045             break;                      \
0046         }                           \
0047         if (W && !(in_dbg_master()))                \
0048             msleep(W);                  \
0049     }                               \
0050     ret__;                              \
0051 })
0052
0053 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
0054
0055 #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
0056 #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
0057
0058 /* Intel GPIO access functions */
0059
0060 #define I2C_RISEFALL_TIME 20
0061
0062 static inline struct intel_gmbus *
0063 to_intel_gmbus(struct i2c_adapter *i2c)
0064 {
0065     return container_of(i2c, struct intel_gmbus, adapter);
0066 }
0067
0068 struct intel_gpio {
0069     struct i2c_adapter adapter;
0070     struct i2c_algo_bit_data algo;
0071     struct drm_psb_private *dev_priv;
0072     u32 reg;
0073 };
0074
0075 void
0076 gma_intel_i2c_reset(struct drm_device *dev)
0077 {
0078     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0079     GMBUS_REG_WRITE(GMBUS0, 0);
0080 }
0081
0082 static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
0083 {
0084     /* When using bit bashing for I2C, this bit needs to be set to 1 */
0085     /* FIXME: We are never Pineview, right?
0086
0087     u32 val;
0088
0089     if (!IS_PINEVIEW(dev_priv->dev))
0090         return;
0091
0092     val = REG_READ(DSPCLK_GATE_D);
0093     if (enable)
0094         val |= DPCUNIT_CLOCK_GATE_DISABLE;
0095     else
0096         val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
0097     REG_WRITE(DSPCLK_GATE_D, val);
0098
0099     return;
0100     */
0101 }
0102
0103 static u32 get_reserved(struct intel_gpio *gpio)
0104 {
0105     struct drm_psb_private *dev_priv = gpio->dev_priv;
0106     u32 reserved = 0;
0107
0108     /* On most chips, these bits must be preserved in software. */
0109     reserved = GMBUS_REG_READ(gpio->reg) &
0110                      (GPIO_DATA_PULLUP_DISABLE |
0111                       GPIO_CLOCK_PULLUP_DISABLE);
0112
0113     return reserved;
0114 }
0115
0116 static int get_clock(void *data)
0117 {
0118     struct intel_gpio *gpio = data;
0119     struct drm_psb_private *dev_priv = gpio->dev_priv;
0120     u32 reserved = get_reserved(gpio);
0121     GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
0122     GMBUS_REG_WRITE(gpio->reg, reserved);
0123     return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
0124 }
0125
0126 static int get_data(void *data)
0127 {
0128     struct intel_gpio *gpio = data;
0129     struct drm_psb_private *dev_priv = gpio->dev_priv;
0130     u32 reserved = get_reserved(gpio);
0131     GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
0132     GMBUS_REG_WRITE(gpio->reg, reserved);
0133     return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
0134 }
0135
0136 static void set_clock(void *data, int state_high)
0137 {
0138     struct intel_gpio *gpio = data;
0139     struct drm_psb_private *dev_priv = gpio->dev_priv;
0140     u32 reserved = get_reserved(gpio);
0141     u32 clock_bits;
0142
0143     if (state_high)
0144         clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
0145     else
0146         clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
0147             GPIO_CLOCK_VAL_MASK;
0148
0149     GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
0150     GMBUS_REG_READ(gpio->reg); /* Posting */
0151 }
0152
0153 static void set_data(void *data, int state_high)
0154 {
0155     struct intel_gpio *gpio = data;
0156     struct drm_psb_private *dev_priv = gpio->dev_priv;
0157     u32 reserved = get_reserved(gpio);
0158     u32 data_bits;
0159
0160     if (state_high)
0161         data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
0162     else
0163         data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
0164             GPIO_DATA_VAL_MASK;
0165
0166     GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
0167     GMBUS_REG_READ(gpio->reg);
0168 }
0169
0170 static struct i2c_adapter *
0171 intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
0172 {
0173     static const int map_pin_to_reg[] = {
0174         0,
0175         GPIOB,
0176         GPIOA,
0177         GPIOC,
0178         GPIOD,
0179         GPIOE,
0180         0,
0181         GPIOF,
0182     };
0183     struct intel_gpio *gpio;
0184
0185     if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
0186         return NULL;
0187
0188     gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
0189     if (gpio == NULL)
0190         return NULL;
0191
0192     gpio->reg = map_pin_to_reg[pin];
0193     gpio->dev_priv = dev_priv;
0194
0195     snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
0196          "gma500 GPIO%c", "?BACDE?F"[pin]);
0197     gpio->adapter.owner = THIS_MODULE;
0198     gpio->adapter.algo_data = &gpio->algo;
0199     gpio->adapter.dev.parent = dev_priv->dev.dev;
0200     gpio->algo.setsda = set_data;
0201     gpio->algo.setscl = set_clock;
0202     gpio->algo.getsda = get_data;
0203     gpio->algo.getscl = get_clock;
0204     gpio->algo.udelay = I2C_RISEFALL_TIME;
0205     gpio->algo.timeout = usecs_to_jiffies(2200);
0206     gpio->algo.data = gpio;
0207
0208     if (i2c_bit_add_bus(&gpio->adapter))
0209         goto out_free;
0210
0211     return &gpio->adapter;
0212
0213 out_free:
0214     kfree(gpio);
0215     return NULL;
0216 }
0217
0218 static int
0219 intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
0220              struct i2c_adapter *adapter,
0221              struct i2c_msg *msgs,
0222              int num)
0223 {
0224     struct intel_gpio *gpio = container_of(adapter,
0225                            struct intel_gpio,
0226                            adapter);
0227     int ret;
0228
0229     gma_intel_i2c_reset(&dev_priv->dev);
0230
0231     intel_i2c_quirk_set(dev_priv, true);
0232     set_data(gpio, 1);
0233     set_clock(gpio, 1);
0234     udelay(I2C_RISEFALL_TIME);
0235
0236     ret = adapter->algo->master_xfer(adapter, msgs, num);
0237
0238     set_data(gpio, 1);
0239     set_clock(gpio, 1);
0240     intel_i2c_quirk_set(dev_priv, false);
0241
0242     return ret;
0243 }
0244
0245 static int
0246 gmbus_xfer(struct i2c_adapter *adapter,
0247        struct i2c_msg *msgs,
0248        int num)
0249 {
0250     struct intel_gmbus *bus = container_of(adapter,
0251                            struct intel_gmbus,
0252                            adapter);
0253     struct drm_psb_private *dev_priv = adapter->algo_data;
0254     int i, reg_offset;
0255
0256     if (bus->force_bit)
0257         return intel_i2c_quirk_xfer(dev_priv,
0258                         bus->force_bit, msgs, num);
0259
0260     reg_offset = 0;
0261
0262     GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
0263
0264     for (i = 0; i < num; i++) {
0265         u16 len = msgs[i].len;
0266         u8 *buf = msgs[i].buf;
0267
0268         if (msgs[i].flags & I2C_M_RD) {
0269             GMBUS_REG_WRITE(GMBUS1 + reg_offset,
0270                     GMBUS_CYCLE_WAIT |
0271                     (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
0272                     (len << GMBUS_BYTE_COUNT_SHIFT) |
0273                     (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
0274                     GMBUS_SLAVE_READ | GMBUS_SW_RDY);
0275             GMBUS_REG_READ(GMBUS2+reg_offset);
0276             do {
0277                 u32 val, loop = 0;
0278
0279                 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
0280                          (GMBUS_SATOER | GMBUS_HW_RDY), 50))
0281                     goto timeout;
0282                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
0283                     goto clear_err;
0284
0285                 val = GMBUS_REG_READ(GMBUS3 + reg_offset);
0286                 do {
0287                     *buf++ = val & 0xff;
0288                     val >>= 8;
0289                 } while (--len && ++loop < 4);
0290             } while (len);
0291         } else {
0292             u32 val, loop;
0293
0294             val = loop = 0;
0295             do {
0296                 val |= *buf++ << (8 * loop);
0297             } while (--len && ++loop < 4);
0298
0299             GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
0300             GMBUS_REG_WRITE(GMBUS1 + reg_offset,
0301                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
0302                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
0303                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
0304                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
0305             GMBUS_REG_READ(GMBUS2+reg_offset);
0306
0307             while (len) {
0308                 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
0309                          (GMBUS_SATOER | GMBUS_HW_RDY), 50))
0310                     goto timeout;
0311                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
0312                     GMBUS_SATOER)
0313                     goto clear_err;
0314
0315                 val = loop = 0;
0316                 do {
0317                     val |= *buf++ << (8 * loop);
0318                 } while (--len && ++loop < 4);
0319
0320                 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
0321                 GMBUS_REG_READ(GMBUS2+reg_offset);
0322             }
0323         }
0324
0325         if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
0326             goto timeout;
0327         if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
0328             goto clear_err;
0329     }
0330
0331     goto done;
0332
0333 clear_err:
0334     /* Toggle the Software Clear Interrupt bit. This has the effect
0335      * of resetting the GMBUS controller and so clearing the
0336      * BUS_ERROR raised by the slave's NAK.
0337      */
0338     GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
0339     GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
0340
0341 done:
0342     /* Mark the GMBUS interface as disabled. We will re-enable it at the
0343      * start of the next xfer, till then let it sleep.
0344      */
0345     GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
0346     return i;
0347
0348 timeout:
0349     DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
0350          bus->reg0 & 0xff, bus->adapter.name);
0351     GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
0352
0353     /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
0354     bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
0355     if (!bus->force_bit)
0356         return -ENOMEM;
0357
0358     return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
0359 }
0360
0361 static u32 gmbus_func(struct i2c_adapter *adapter)
0362 {
0363     struct intel_gmbus *bus = container_of(adapter,
0364                            struct intel_gmbus,
0365                            adapter);
0366
0367     if (bus->force_bit)
0368         bus->force_bit->algo->functionality(bus->force_bit);
0369
0370     return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
0371         /* I2C_FUNC_10BIT_ADDR | */
0372         I2C_FUNC_SMBUS_READ_BLOCK_DATA |
0373         I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
0374 }
0375
0376 static const struct i2c_algorithm gmbus_algorithm = {
0377     .master_xfer    = gmbus_xfer,
0378     .functionality  = gmbus_func
0379 };
0380
0381 /**
0382  * gma_intel_setup_gmbus() - instantiate all Intel i2c GMBuses
0383  * @dev: DRM device
0384  */
0385 int gma_intel_setup_gmbus(struct drm_device *dev)
0386 {
0387     static const char *names[GMBUS_NUM_PORTS] = {
0388         "disabled",
0389         "ssc",
0390         "vga",
0391         "panel",
0392         "dpc",
0393         "dpb",
0394         "reserved",
0395         "dpd",
0396     };
0397     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0398     int ret, i;
0399
0400     dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
0401                   GFP_KERNEL);
0402     if (dev_priv->gmbus == NULL)
0403         return -ENOMEM;
0404
0405     if (IS_MRST(dev))
0406         dev_priv->gmbus_reg = dev_priv->aux_reg;
0407     else
0408         dev_priv->gmbus_reg = dev_priv->vdc_reg;
0409
0410     for (i = 0; i < GMBUS_NUM_PORTS; i++) {
0411         struct intel_gmbus *bus = &dev_priv->gmbus[i];
0412
0413         bus->adapter.owner = THIS_MODULE;
0414         bus->adapter.class = I2C_CLASS_DDC;
0415         snprintf(bus->adapter.name,
0416              sizeof(bus->adapter.name),
0417              "gma500 gmbus %s",
0418              names[i]);
0419
0420         bus->adapter.dev.parent = dev->dev;
0421         bus->adapter.algo_data  = dev_priv;
0422
0423         bus->adapter.algo = &gmbus_algorithm;
0424         ret = i2c_add_adapter(&bus->adapter);
0425         if (ret)
0426             goto err;
0427
0428         /* By default use a conservative clock rate */
0429         bus->reg0 = i | GMBUS_RATE_100KHZ;
0430
0431         /* XXX force bit banging until GMBUS is fully debugged */
0432         bus->force_bit = intel_gpio_create(dev_priv, i);
0433     }
0434
0435     gma_intel_i2c_reset(&dev_priv->dev);
0436
0437     return 0;
0438
0439 err:
0440     while (i--) {
0441         struct intel_gmbus *bus = &dev_priv->gmbus[i];
0442         i2c_del_adapter(&bus->adapter);
0443     }
0444     kfree(dev_priv->gmbus);
0445     dev_priv->gmbus = NULL;
0446     return ret;
0447 }
0448
0449 void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
0450 {
0451     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0452
0453     /* speed:
0454      * 0x0 = 100 KHz
0455      * 0x1 = 50 KHz
0456      * 0x2 = 400 KHz
0457      * 0x3 = 1000 Khz
0458      */
0459     bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
0460 }
0461
0462 void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
0463 {
0464     struct intel_gmbus *bus = to_intel_gmbus(adapter);
0465
0466     if (force_bit) {
0467         if (bus->force_bit == NULL) {
0468             struct drm_psb_private *dev_priv = adapter->algo_data;
0469             bus->force_bit = intel_gpio_create(dev_priv,
0470                                bus->reg0 & 0xff);
0471         }
0472     } else {
0473         if (bus->force_bit) {
0474             i2c_del_adapter(bus->force_bit);
0475             kfree(bus->force_bit);
0476             bus->force_bit = NULL;
0477         }
0478     }
0479 }
0480
0481 void gma_intel_teardown_gmbus(struct drm_device *dev)
0482 {
0483     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0484     int i;
0485
0486     if (dev_priv->gmbus == NULL)
0487         return;
0488
0489     for (i = 0; i < GMBUS_NUM_PORTS; i++) {
0490         struct intel_gmbus *bus = &dev_priv->gmbus[i];
0491         if (bus->force_bit) {
0492             i2c_del_adapter(bus->force_bit);
0493             kfree(bus->force_bit);
0494         }
0495         i2c_del_adapter(&bus->adapter);
0496     }
0497
0498     dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
0499     kfree(dev_priv->gmbus);
0500     dev_priv->gmbus = NULL;
0501 }