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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2006 Intel Corporation
0004  *
0005  * Authors:
0006  *    Eric Anholt <eric@anholt.net>
0007  */
0008 
0009 #ifndef _INTEL_BIOS_H_
0010 #define _INTEL_BIOS_H_
0011 
0012 struct drm_device;
0013 
0014 struct vbt_header {
0015     u8 signature[20];       /**< Always starts with 'VBT$' */
0016     u16 version;            /**< decimal */
0017     u16 header_size;        /**< in bytes */
0018     u16 vbt_size;           /**< in bytes */
0019     u8 vbt_checksum;
0020     u8 reserved0;
0021     u32 bdb_offset;         /**< from beginning of VBT */
0022     u32 aim_offset[4];      /**< from beginning of VBT */
0023 } __packed;
0024 
0025 
0026 struct bdb_header {
0027     u8 signature[16];       /**< Always 'BIOS_DATA_BLOCK' */
0028     u16 version;            /**< decimal */
0029     u16 header_size;        /**< in bytes */
0030     u16 bdb_size;           /**< in bytes */
0031 };
0032 
0033 /* strictly speaking, this is a "skip" block, but it has interesting info */
0034 struct vbios_data {
0035     u8 type; /* 0 == desktop, 1 == mobile */
0036     u8 relstage;
0037     u8 chipset;
0038     u8 lvds_present:1;
0039     u8 tv_present:1;
0040     u8 rsvd2:6; /* finish byte */
0041     u8 rsvd3[4];
0042     u8 signon[155];
0043     u8 copyright[61];
0044     u16 code_segment;
0045     u8 dos_boot_mode;
0046     u8 bandwidth_percent;
0047     u8 rsvd4; /* popup memory size */
0048     u8 resize_pci_bios;
0049     u8 rsvd5; /* is crt already on ddc2 */
0050 } __packed;
0051 
0052 /*
0053  * There are several types of BIOS data blocks (BDBs), each block has
0054  * an ID and size in the first 3 bytes (ID in first, size in next 2).
0055  * Known types are listed below.
0056  */
0057 #define BDB_GENERAL_FEATURES      1
0058 #define BDB_GENERAL_DEFINITIONS   2
0059 #define BDB_OLD_TOGGLE_LIST   3
0060 #define BDB_MODE_SUPPORT_LIST     4
0061 #define BDB_GENERIC_MODE_TABLE    5
0062 #define BDB_EXT_MMIO_REGS     6
0063 #define BDB_SWF_IO        7
0064 #define BDB_SWF_MMIO          8
0065 #define BDB_DOT_CLOCK_TABLE   9
0066 #define BDB_MODE_REMOVAL_TABLE   10
0067 #define BDB_CHILD_DEVICE_TABLE   11
0068 #define BDB_DRIVER_FEATURES  12
0069 #define BDB_DRIVER_PERSISTENCE   13
0070 #define BDB_EXT_TABLE_PTRS   14
0071 #define BDB_DOT_CLOCK_OVERRIDE   15
0072 #define BDB_DISPLAY_SELECT   16
0073 /* 17 rsvd */
0074 #define BDB_DRIVER_ROTATION  18
0075 #define BDB_DISPLAY_REMOVE   19
0076 #define BDB_OEM_CUSTOM       20
0077 #define BDB_EFP_LIST         21 /* workarounds for VGA hsync/vsync */
0078 #define BDB_SDVO_LVDS_OPTIONS    22
0079 #define BDB_SDVO_PANEL_DTDS  23
0080 #define BDB_SDVO_LVDS_PNP_IDS    24
0081 #define BDB_SDVO_LVDS_POWER_SEQ  25
0082 #define BDB_TV_OPTIONS       26
0083 #define BDB_EDP          27
0084 #define BDB_LVDS_OPTIONS     40
0085 #define BDB_LVDS_LFP_DATA_PTRS   41
0086 #define BDB_LVDS_LFP_DATA    42
0087 #define BDB_LVDS_BACKLIGHT   43
0088 #define BDB_LVDS_POWER       44
0089 #define BDB_SKIP        254 /* VBIOS private block, ignore */
0090 
0091 struct bdb_general_features {
0092     /* bits 1 */
0093     u8 panel_fitting:2;
0094     u8 flexaim:1;
0095     u8 msg_enable:1;
0096     u8 clear_screen:3;
0097     u8 color_flip:1;
0098 
0099     /* bits 2 */
0100     u8 download_ext_vbt:1;
0101     u8 enable_ssc:1;
0102     u8 ssc_freq:1;
0103     u8 enable_lfp_on_override:1;
0104     u8 disable_ssc_ddt:1;
0105     u8 rsvd8:3; /* finish byte */
0106 
0107     /* bits 3 */
0108     u8 disable_smooth_vision:1;
0109     u8 single_dvi:1;
0110     u8 rsvd9:6; /* finish byte */
0111 
0112     /* bits 4 */
0113     u8 legacy_monitor_detect;
0114 
0115     /* bits 5 */
0116     u8 int_crt_support:1;
0117     u8 int_tv_support:1;
0118     u8 int_efp_support:1;
0119     u8 dp_ssc_enb:1;    /* PCH attached eDP supports SSC */
0120     u8 dp_ssc_freq:1;   /* SSC freq for PCH attached eDP */
0121     u8 rsvd11:3; /* finish byte */
0122 } __packed;
0123 
0124 /* pre-915 */
0125 #define GPIO_PIN_DVI_LVDS   0x03 /* "DVI/LVDS DDC GPIO pins" */
0126 #define GPIO_PIN_ADD_I2C    0x05 /* "ADDCARD I2C GPIO pins" */
0127 #define GPIO_PIN_ADD_DDC    0x04 /* "ADDCARD DDC GPIO pins" */
0128 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
0129 
0130 /* Pre 915 */
0131 #define DEVICE_TYPE_NONE    0x00
0132 #define DEVICE_TYPE_CRT     0x01
0133 #define DEVICE_TYPE_TV      0x09
0134 #define DEVICE_TYPE_EFP     0x12
0135 #define DEVICE_TYPE_LFP     0x22
0136 /* On 915+ */
0137 #define DEVICE_TYPE_CRT_DPMS        0x6001
0138 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
0139 #define DEVICE_TYPE_TV_COMPOSITE    0x0209
0140 #define DEVICE_TYPE_TV_MACROVISION  0x0289
0141 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
0142 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
0143 #define DEVICE_TYPE_TV_SCART        0x0209
0144 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
0145 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
0146 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
0147 #define DEVICE_TYPE_EFP_DVI_I       0x6053
0148 #define DEVICE_TYPE_EFP_DVI_D_DUAL  0x6152
0149 #define DEVICE_TYPE_EFP_DVI_D_HDCP  0x60d2
0150 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
0151 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
0152 #define DEVICE_TYPE_LFP_PANELLINK   0x5012
0153 #define DEVICE_TYPE_LFP_CMOS_PWR    0x5042
0154 #define DEVICE_TYPE_LFP_LVDS_PWR    0x5062
0155 #define DEVICE_TYPE_LFP_LVDS_DUAL   0x5162
0156 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
0157 
0158 #define DEVICE_CFG_NONE     0x00
0159 #define DEVICE_CFG_12BIT_DVOB   0x01
0160 #define DEVICE_CFG_12BIT_DVOC   0x02
0161 #define DEVICE_CFG_24BIT_DVOBC  0x09
0162 #define DEVICE_CFG_24BIT_DVOCB  0x0a
0163 #define DEVICE_CFG_DUAL_DVOB    0x11
0164 #define DEVICE_CFG_DUAL_DVOC    0x12
0165 #define DEVICE_CFG_DUAL_DVOBC   0x13
0166 #define DEVICE_CFG_DUAL_LINK_DVOBC  0x19
0167 #define DEVICE_CFG_DUAL_LINK_DVOCB  0x1a
0168 
0169 #define DEVICE_WIRE_NONE    0x00
0170 #define DEVICE_WIRE_DVOB    0x01
0171 #define DEVICE_WIRE_DVOC    0x02
0172 #define DEVICE_WIRE_DVOBC   0x03
0173 #define DEVICE_WIRE_DVOBB   0x05
0174 #define DEVICE_WIRE_DVOCC   0x06
0175 #define DEVICE_WIRE_DVOB_MASTER 0x0d
0176 #define DEVICE_WIRE_DVOC_MASTER 0x0e
0177 
0178 #define DEVICE_PORT_DVOA    0x00 /* none on 845+ */
0179 #define DEVICE_PORT_DVOB    0x01
0180 #define DEVICE_PORT_DVOC    0x02
0181 
0182 struct child_device_config {
0183     u16 handle;
0184     u16 device_type;
0185     u8  device_id[10]; /* ascii string */
0186     u16 addin_offset;
0187     u8  dvo_port; /* See Device_PORT_* above */
0188     u8  i2c_pin;
0189     u8  slave_addr;
0190     u8  ddc_pin;
0191     u16 edid_ptr;
0192     u8  dvo_cfg; /* See DEVICE_CFG_* above */
0193     u8  dvo2_port;
0194     u8  i2c2_pin;
0195     u8  slave2_addr;
0196     u8  ddc2_pin;
0197     u8  capabilities;
0198     u8  dvo_wiring;/* See DEVICE_WIRE_* above */
0199     u8  dvo2_wiring;
0200     u16 extended_type;
0201     u8  dvo_function;
0202 } __packed;
0203 
0204 
0205 struct bdb_general_definitions {
0206     /* DDC GPIO */
0207     u8 crt_ddc_gmbus_pin;
0208 
0209     /* DPMS bits */
0210     u8 dpms_acpi:1;
0211     u8 skip_boot_crt_detect:1;
0212     u8 dpms_aim:1;
0213     u8 rsvd1:5; /* finish byte */
0214 
0215     /* boot device bits */
0216     u8 boot_display[2];
0217     u8 child_dev_size;
0218 
0219     /*
0220      * Device info:
0221      * If TV is present, it'll be at devices[0].
0222      * LVDS will be next, either devices[0] or [1], if present.
0223      * On some platforms the number of device is 6. But could be as few as
0224      * 4 if both TV and LVDS are missing.
0225      * And the device num is related with the size of general definition
0226      * block. It is obtained by using the following formula:
0227      * number = (block_size - sizeof(bdb_general_definitions))/
0228      *       sizeof(child_device_config);
0229      */
0230     struct child_device_config devices[];
0231 };
0232 
0233 struct bdb_lvds_options {
0234     u8 panel_type;
0235     u8 rsvd1;
0236     /* LVDS capabilities, stored in a dword */
0237     u8 pfit_mode:2;
0238     u8 pfit_text_mode_enhanced:1;
0239     u8 pfit_gfx_mode_enhanced:1;
0240     u8 pfit_ratio_auto:1;
0241     u8 pixel_dither:1;
0242     u8 lvds_edid:1;
0243     u8 rsvd2:1;
0244     u8 rsvd4;
0245 } __packed;
0246 
0247 struct bdb_lvds_backlight {
0248     u8 type:2;
0249     u8 pol:1;
0250     u8 gpio:3;
0251     u8 gmbus:2;
0252     u16 freq;
0253     u8 minbrightness;
0254     u8 i2caddr;
0255     u8 brightnesscmd;
0256     /*FIXME: more...*/
0257 } __packed;
0258 
0259 /* LFP pointer table contains entries to the struct below */
0260 struct bdb_lvds_lfp_data_ptr {
0261     u16 fp_timing_offset; /* offsets are from start of bdb */
0262     u8 fp_table_size;
0263     u16 dvo_timing_offset;
0264     u8 dvo_table_size;
0265     u16 panel_pnp_id_offset;
0266     u8 pnp_table_size;
0267 } __packed;
0268 
0269 struct bdb_lvds_lfp_data_ptrs {
0270     u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
0271     struct bdb_lvds_lfp_data_ptr ptr[16];
0272 } __packed;
0273 
0274 /* LFP data has 3 blocks per entry */
0275 struct lvds_fp_timing {
0276     u16 x_res;
0277     u16 y_res;
0278     u32 lvds_reg;
0279     u32 lvds_reg_val;
0280     u32 pp_on_reg;
0281     u32 pp_on_reg_val;
0282     u32 pp_off_reg;
0283     u32 pp_off_reg_val;
0284     u32 pp_cycle_reg;
0285     u32 pp_cycle_reg_val;
0286     u32 pfit_reg;
0287     u32 pfit_reg_val;
0288     u16 terminator;
0289 } __packed;
0290 
0291 struct lvds_dvo_timing {
0292     u16 clock;      /**< In 10khz */
0293     u8 hactive_lo;
0294     u8 hblank_lo;
0295     u8 hblank_hi:4;
0296     u8 hactive_hi:4;
0297     u8 vactive_lo;
0298     u8 vblank_lo;
0299     u8 vblank_hi:4;
0300     u8 vactive_hi:4;
0301     u8 hsync_off_lo;
0302     u8 hsync_pulse_width;
0303     u8 vsync_pulse_width:4;
0304     u8 vsync_off:4;
0305     u8 rsvd0:6;
0306     u8 hsync_off_hi:2;
0307     u8 h_image;
0308     u8 v_image;
0309     u8 max_hv;
0310     u8 h_border;
0311     u8 v_border;
0312     u8 rsvd1:3;
0313     u8 digital:2;
0314     u8 vsync_positive:1;
0315     u8 hsync_positive:1;
0316     u8 rsvd2:1;
0317 } __packed;
0318 
0319 struct lvds_pnp_id {
0320     u16 mfg_name;
0321     u16 product_code;
0322     u32 serial;
0323     u8 mfg_week;
0324     u8 mfg_year;
0325 } __packed;
0326 
0327 struct bdb_lvds_lfp_data_entry {
0328     struct lvds_fp_timing fp_timing;
0329     struct lvds_dvo_timing dvo_timing;
0330     struct lvds_pnp_id pnp_id;
0331 } __packed;
0332 
0333 struct bdb_lvds_lfp_data {
0334     struct bdb_lvds_lfp_data_entry data[16];
0335 } __packed;
0336 
0337 struct aimdb_header {
0338     char signature[16];
0339     char oem_device[20];
0340     u16 aimdb_version;
0341     u16 aimdb_header_size;
0342     u16 aimdb_size;
0343 } __packed;
0344 
0345 struct aimdb_block {
0346     u8 aimdb_id;
0347     u16 aimdb_size;
0348 } __packed;
0349 
0350 struct vch_panel_data {
0351     u16 fp_timing_offset;
0352     u8 fp_timing_size;
0353     u16 dvo_timing_offset;
0354     u8 dvo_timing_size;
0355     u16 text_fitting_offset;
0356     u8 text_fitting_size;
0357     u16 graphics_fitting_offset;
0358     u8 graphics_fitting_size;
0359 } __packed;
0360 
0361 struct vch_bdb_22 {
0362     struct aimdb_block aimdb_block;
0363     struct vch_panel_data panels[16];
0364 } __packed;
0365 
0366 struct bdb_sdvo_lvds_options {
0367     u8 panel_backlight;
0368     u8 h40_set_panel_type;
0369     u8 panel_type;
0370     u8 ssc_clk_freq;
0371     u16 als_low_trip;
0372     u16 als_high_trip;
0373     u8 sclalarcoeff_tab_row_num;
0374     u8 sclalarcoeff_tab_row_size;
0375     u8 coefficient[8];
0376     u8 panel_misc_bits_1;
0377     u8 panel_misc_bits_2;
0378     u8 panel_misc_bits_3;
0379     u8 panel_misc_bits_4;
0380 } __packed;
0381 
0382 #define BDB_DRIVER_FEATURE_NO_LVDS      0
0383 #define BDB_DRIVER_FEATURE_INT_LVDS     1
0384 #define BDB_DRIVER_FEATURE_SDVO_LVDS        2
0385 #define BDB_DRIVER_FEATURE_EDP          3
0386 
0387 struct bdb_driver_features {
0388     u8 boot_dev_algorithm:1;
0389     u8 block_display_switch:1;
0390     u8 allow_display_switch:1;
0391     u8 hotplug_dvo:1;
0392     u8 dual_view_zoom:1;
0393     u8 int15h_hook:1;
0394     u8 sprite_in_clone:1;
0395     u8 primary_lfp_id:1;
0396 
0397     u16 boot_mode_x;
0398     u16 boot_mode_y;
0399     u8 boot_mode_bpp;
0400     u8 boot_mode_refresh;
0401 
0402     u16 enable_lfp_primary:1;
0403     u16 selective_mode_pruning:1;
0404     u16 dual_frequency:1;
0405     u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
0406     u16 nt_clone_support:1;
0407     u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
0408     u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
0409     u16 cui_aspect_scaling:1;
0410     u16 preserve_aspect_ratio:1;
0411     u16 sdvo_device_power_down:1;
0412     u16 crt_hotplug:1;
0413     u16 lvds_config:2;
0414     u16 tv_hotplug:1;
0415     u16 hdmi_config:2;
0416 
0417     u8 static_display:1;
0418     u8 reserved2:7;
0419     u16 legacy_crt_max_x;
0420     u16 legacy_crt_max_y;
0421     u8 legacy_crt_max_refresh;
0422 
0423     u8 hdmi_termination;
0424     u8 custom_vbt_version;
0425 } __packed;
0426 
0427 #define EDP_18BPP   0
0428 #define EDP_24BPP   1
0429 #define EDP_30BPP   2
0430 #define EDP_RATE_1_62   0
0431 #define EDP_RATE_2_7    1
0432 #define EDP_LANE_1  0
0433 #define EDP_LANE_2  1
0434 #define EDP_LANE_4  3
0435 #define EDP_PREEMPHASIS_NONE    0
0436 #define EDP_PREEMPHASIS_3_5dB   1
0437 #define EDP_PREEMPHASIS_6dB 2
0438 #define EDP_PREEMPHASIS_9_5dB   3
0439 #define EDP_VSWING_0_4V     0
0440 #define EDP_VSWING_0_6V     1
0441 #define EDP_VSWING_0_8V     2
0442 #define EDP_VSWING_1_2V     3
0443 
0444 struct edp_power_seq {
0445     u16 t1_t3;
0446     u16 t8;
0447     u16 t9;
0448     u16 t10;
0449     u16 t11_t12;
0450 } __attribute__ ((packed));
0451 
0452 struct edp_link_params {
0453     u8 rate:4;
0454     u8 lanes:4;
0455     u8 preemphasis:4;
0456     u8 vswing:4;
0457 } __attribute__ ((packed));
0458 
0459 struct bdb_edp {
0460     struct edp_power_seq power_seqs[16];
0461     u32 color_depth;
0462     u32 sdrrs_msa_timing_delay;
0463     struct edp_link_params link_params[16];
0464 } __attribute__ ((packed));
0465 
0466 extern int psb_intel_init_bios(struct drm_device *dev);
0467 extern void psb_intel_destroy_bios(struct drm_device *dev);
0468 
0469 /*
0470  * Driver<->VBIOS interaction occurs through scratch bits in
0471  * GR18 & SWF*.
0472  */
0473 
0474 /* GR18 bits are set on display switch and hotkey events */
0475 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
0476 #define GR18_HOTKEY_MASK    0x78 /* See also SWF4 15:0 */
0477 #define   GR18_HK_NONE      (0x0<<3)
0478 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
0479 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
0480 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
0481 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
0482 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
0483 #define   GR18_HK_PFIT      (0x8<<3)
0484 #define   GR18_HK_APM_CHANGE    (0xa<<3)
0485 #define   GR18_HK_MULTIPLE  (0xc<<3)
0486 #define GR18_USER_INT_EN    (1<<2)
0487 #define GR18_A0000_FLUSH_EN (1<<1)
0488 #define GR18_SMM_EN     (1<<0)
0489 
0490 /* Set by driver, cleared by VBIOS */
0491 #define SWF00_YRES_SHIFT    16
0492 #define SWF00_XRES_SHIFT    0
0493 #define SWF00_RES_MASK      0xffff
0494 
0495 /* Set by VBIOS at boot time and driver at runtime */
0496 #define SWF01_TV2_FORMAT_SHIFT  8
0497 #define SWF01_TV1_FORMAT_SHIFT  0
0498 #define SWF01_TV_FORMAT_MASK    0xffff
0499 
0500 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
0501 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
0502 #define SWF10_LFP_DPMS_OVR  (1<<27) /* override DPMS on display switch */
0503 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
0504 #define   SWF10_OLD_TOGGLE  0x0
0505 #define   SWF10_TOGGLE_LIST_1   0x1
0506 #define   SWF10_TOGGLE_LIST_2   0x2
0507 #define   SWF10_TOGGLE_LIST_3   0x3
0508 #define   SWF10_TOGGLE_LIST_4   0x4
0509 #define SWF10_PANNING_EN    (1<<23)
0510 #define SWF10_DRIVER_LOADED (1<<22)
0511 #define SWF10_EXTENDED_DESKTOP  (1<<21)
0512 #define SWF10_EXCLUSIVE_MODE    (1<<20)
0513 #define SWF10_OVERLAY_EN    (1<<19)
0514 #define SWF10_PLANEB_HOLDOFF    (1<<18)
0515 #define SWF10_PLANEA_HOLDOFF    (1<<17)
0516 #define SWF10_VGA_HOLDOFF   (1<<16)
0517 #define SWF10_ACTIVE_DISP_MASK  0xffff
0518 #define   SWF10_PIPEB_LFP2  (1<<15)
0519 #define   SWF10_PIPEB_EFP2  (1<<14)
0520 #define   SWF10_PIPEB_TV2   (1<<13)
0521 #define   SWF10_PIPEB_CRT2  (1<<12)
0522 #define   SWF10_PIPEB_LFP   (1<<11)
0523 #define   SWF10_PIPEB_EFP   (1<<10)
0524 #define   SWF10_PIPEB_TV    (1<<9)
0525 #define   SWF10_PIPEB_CRT   (1<<8)
0526 #define   SWF10_PIPEA_LFP2  (1<<7)
0527 #define   SWF10_PIPEA_EFP2  (1<<6)
0528 #define   SWF10_PIPEA_TV2   (1<<5)
0529 #define   SWF10_PIPEA_CRT2  (1<<4)
0530 #define   SWF10_PIPEA_LFP   (1<<3)
0531 #define   SWF10_PIPEA_EFP   (1<<2)
0532 #define   SWF10_PIPEA_TV    (1<<1)
0533 #define   SWF10_PIPEA_CRT   (1<<0)
0534 
0535 #define SWF11_MEMORY_SIZE_SHIFT 16
0536 #define SWF11_SV_TEST_EN    (1<<15)
0537 #define SWF11_IS_AGP        (1<<14)
0538 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
0539 #define SWF11_DPMS_REDUCED  (1<<12)
0540 #define SWF11_IS_VBE_MODE   (1<<11)
0541 #define SWF11_PIPEB_ACCESS  (1<<10) /* 0 here means pipe a */
0542 #define SWF11_DPMS_MASK     0x07
0543 #define   SWF11_DPMS_OFF    (1<<2)
0544 #define   SWF11_DPMS_SUSPEND    (1<<1)
0545 #define   SWF11_DPMS_STANDBY    (1<<0)
0546 #define   SWF11_DPMS_ON     0
0547 
0548 #define SWF14_GFX_PFIT_EN   (1<<31)
0549 #define SWF14_TEXT_PFIT_EN  (1<<30)
0550 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
0551 #define SWF14_POPUP_EN      (1<<28)
0552 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
0553 #define SWF14_DISP_DETECT_EN    (1<<26)
0554 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
0555 #define SWF14_DRIVER_STATUS (1<<24)
0556 #define SWF14_OS_TYPE_WIN9X (1<<23)
0557 #define SWF14_OS_TYPE_WINNT (1<<22)
0558 /* 21:19 rsvd */
0559 #define SWF14_PM_TYPE_MASK  0x00070000
0560 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
0561 #define   SWF14_PM_ACPI     (0x3 << 16)
0562 #define   SWF14_PM_APM_12   (0x2 << 16)
0563 #define   SWF14_PM_APM_11   (0x1 << 16)
0564 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
0565       /* if GR18 indicates a display switch */
0566 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
0567 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
0568 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
0569 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
0570 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
0571 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
0572 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
0573 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
0574 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
0575 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
0576 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
0577 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
0578 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
0579 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
0580 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
0581 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
0582       /* if GR18 indicates a panel fitting request */
0583 #define   SWF14_PFIT_EN     (1<<0) /* 0 means disable */
0584       /* if GR18 indicates an APM change request */
0585 #define   SWF14_APM_HIBERNATE   0x4
0586 #define   SWF14_APM_SUSPEND 0x3
0587 #define   SWF14_APM_STANDBY 0x1
0588 #define   SWF14_APM_RESTORE 0x0
0589 
0590 /* Add the device class for LFP, TV, HDMI */
0591 #define  DEVICE_TYPE_INT_LFP    0x1022
0592 #define  DEVICE_TYPE_INT_TV 0x1009
0593 #define  DEVICE_TYPE_HDMI   0x60D2
0594 #define  DEVICE_TYPE_DP     0x68C6
0595 #define  DEVICE_TYPE_eDP    0x78C6
0596 
0597 /* define the DVO port for HDMI output type */
0598 #define     DVO_B       1
0599 #define     DVO_C       2
0600 #define     DVO_D       3
0601 
0602 /* define the PORT for DP output type */
0603 #define     PORT_IDPB   7
0604 #define     PORT_IDPC   8
0605 #define     PORT_IDPD   9
0606 
0607 #endif /* _INTEL_BIOS_H_ */
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