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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright © 2006-2011 Intel Corporation
0004  *
0005  * Authors:
0006  *  Eric Anholt <eric@anholt.net>
0007  */
0008 
0009 #include <linux/delay.h>
0010 #include <linux/i2c.h>
0011 
0012 #include <drm/drm_crtc.h>
0013 
0014 #include "cdv_device.h"
0015 #include "framebuffer.h"
0016 #include "gma_display.h"
0017 #include "power.h"
0018 #include "psb_drv.h"
0019 #include "psb_intel_drv.h"
0020 #include "psb_intel_reg.h"
0021 
0022 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
0023                   struct drm_crtc *crtc, int target,
0024                   int refclk, struct gma_clock_t *best_clock);
0025 
0026 
0027 #define CDV_LIMIT_SINGLE_LVDS_96    0
0028 #define CDV_LIMIT_SINGLE_LVDS_100   1
0029 #define CDV_LIMIT_DAC_HDMI_27       2
0030 #define CDV_LIMIT_DAC_HDMI_96       3
0031 #define CDV_LIMIT_DP_27         4
0032 #define CDV_LIMIT_DP_100        5
0033 
0034 static const struct gma_limit_t cdv_intel_limits[] = {
0035     {           /* CDV_SINGLE_LVDS_96MHz */
0036      .dot = {.min = 20000, .max = 115500},
0037      .vco = {.min = 1800000, .max = 3600000},
0038      .n = {.min = 2, .max = 6},
0039      .m = {.min = 60, .max = 160},
0040      .m1 = {.min = 0, .max = 0},
0041      .m2 = {.min = 58, .max = 158},
0042      .p = {.min = 28, .max = 140},
0043      .p1 = {.min = 2, .max = 10},
0044      .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
0045      .find_pll = gma_find_best_pll,
0046      },
0047     {           /* CDV_SINGLE_LVDS_100MHz */
0048      .dot = {.min = 20000, .max = 115500},
0049      .vco = {.min = 1800000, .max = 3600000},
0050      .n = {.min = 2, .max = 6},
0051      .m = {.min = 60, .max = 160},
0052      .m1 = {.min = 0, .max = 0},
0053      .m2 = {.min = 58, .max = 158},
0054      .p = {.min = 28, .max = 140},
0055      .p1 = {.min = 2, .max = 10},
0056      /* The single-channel range is 25-112Mhz, and dual-channel
0057       * is 80-224Mhz.  Prefer single channel as much as possible.
0058       */
0059      .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
0060      .find_pll = gma_find_best_pll,
0061      },
0062     {           /* CDV_DAC_HDMI_27MHz */
0063      .dot = {.min = 20000, .max = 400000},
0064      .vco = {.min = 1809000, .max = 3564000},
0065      .n = {.min = 1, .max = 1},
0066      .m = {.min = 67, .max = 132},
0067      .m1 = {.min = 0, .max = 0},
0068      .m2 = {.min = 65, .max = 130},
0069      .p = {.min = 5, .max = 90},
0070      .p1 = {.min = 1, .max = 9},
0071      .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
0072      .find_pll = gma_find_best_pll,
0073      },
0074     {           /* CDV_DAC_HDMI_96MHz */
0075      .dot = {.min = 20000, .max = 400000},
0076      .vco = {.min = 1800000, .max = 3600000},
0077      .n = {.min = 2, .max = 6},
0078      .m = {.min = 60, .max = 160},
0079      .m1 = {.min = 0, .max = 0},
0080      .m2 = {.min = 58, .max = 158},
0081      .p = {.min = 5, .max = 100},
0082      .p1 = {.min = 1, .max = 10},
0083      .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
0084      .find_pll = gma_find_best_pll,
0085      },
0086     {           /* CDV_DP_27MHz */
0087      .dot = {.min = 160000, .max = 272000},
0088      .vco = {.min = 1809000, .max = 3564000},
0089      .n = {.min = 1, .max = 1},
0090      .m = {.min = 67, .max = 132},
0091      .m1 = {.min = 0, .max = 0},
0092      .m2 = {.min = 65, .max = 130},
0093      .p = {.min = 5, .max = 90},
0094      .p1 = {.min = 1, .max = 9},
0095      .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
0096      .find_pll = cdv_intel_find_dp_pll,
0097      },
0098     {           /* CDV_DP_100MHz */
0099      .dot = {.min = 160000, .max = 272000},
0100      .vco = {.min = 1800000, .max = 3600000},
0101      .n = {.min = 2, .max = 6},
0102      .m = {.min = 60, .max = 164},
0103      .m1 = {.min = 0, .max = 0},
0104      .m2 = {.min = 58, .max = 162},
0105      .p = {.min = 5, .max = 100},
0106      .p1 = {.min = 1, .max = 10},
0107      .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
0108      .find_pll = cdv_intel_find_dp_pll,
0109     }
0110 };
0111 
0112 #define _wait_for(COND, MS, W) ({ \
0113     unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);   \
0114     int ret__ = 0;                          \
0115     while (!(COND)) {                       \
0116         if (time_after(jiffies, timeout__)) {           \
0117             ret__ = -ETIMEDOUT;             \
0118             break;                      \
0119         }                           \
0120         if (W && !in_dbg_master())              \
0121             msleep(W);                  \
0122     }                               \
0123     ret__;                              \
0124 })
0125 
0126 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
0127 
0128 
0129 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
0130 {
0131     int ret;
0132 
0133     ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
0134     if (ret) {
0135         DRM_ERROR("timeout waiting for SB to idle before read\n");
0136         return ret;
0137     }
0138 
0139     REG_WRITE(SB_ADDR, reg);
0140     REG_WRITE(SB_PCKT,
0141            SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
0142            SET_FIELD(SB_DEST_DPLL, SB_DEST) |
0143            SET_FIELD(0xf, SB_BYTE_ENABLE));
0144 
0145     ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
0146     if (ret) {
0147         DRM_ERROR("timeout waiting for SB to idle after read\n");
0148         return ret;
0149     }
0150 
0151     *val = REG_READ(SB_DATA);
0152 
0153     return 0;
0154 }
0155 
0156 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
0157 {
0158     int ret;
0159     static bool dpio_debug = true;
0160     u32 temp;
0161 
0162     if (dpio_debug) {
0163         if (cdv_sb_read(dev, reg, &temp) == 0)
0164             DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
0165         DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
0166     }
0167 
0168     ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
0169     if (ret) {
0170         DRM_ERROR("timeout waiting for SB to idle before write\n");
0171         return ret;
0172     }
0173 
0174     REG_WRITE(SB_ADDR, reg);
0175     REG_WRITE(SB_DATA, val);
0176     REG_WRITE(SB_PCKT,
0177            SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
0178            SET_FIELD(SB_DEST_DPLL, SB_DEST) |
0179            SET_FIELD(0xf, SB_BYTE_ENABLE));
0180 
0181     ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
0182     if (ret) {
0183         DRM_ERROR("timeout waiting for SB to idle after write\n");
0184         return ret;
0185     }
0186 
0187     if (dpio_debug) {
0188         if (cdv_sb_read(dev, reg, &temp) == 0)
0189             DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
0190     }
0191 
0192     return 0;
0193 }
0194 
0195 /* Reset the DPIO configuration register.  The BIOS does this at every
0196  * mode set.
0197  */
0198 void cdv_sb_reset(struct drm_device *dev)
0199 {
0200 
0201     REG_WRITE(DPIO_CFG, 0);
0202     REG_READ(DPIO_CFG);
0203     REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
0204 }
0205 
0206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
0207  * are behind this sideband bus.  They must be programmed while the
0208  * DPLL reference clock is on in the DPLL control register, but before
0209  * the DPLL is enabled in the DPLL control register.
0210  */
0211 static int
0212 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
0213                struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
0214 {
0215     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0216     int pipe = gma_crtc->pipe;
0217     u32 m, n_vco, p;
0218     int ret = 0;
0219     int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
0220     int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
0221     u32 ref_value;
0222     u32 lane_reg, lane_value;
0223 
0224     cdv_sb_reset(dev);
0225 
0226     REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
0227 
0228     udelay(100);
0229 
0230     /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
0231     ref_value = 0x68A701;
0232 
0233     cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
0234 
0235     /* We don't know what the other fields of these regs are, so
0236      * leave them in place.
0237      */
0238     /*
0239      * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
0240      * for the pipe A/B. Display spec 1.06 has wrong definition.
0241      * Correct definition is like below:
0242      *
0243      * refclka mean use clock from same PLL
0244      *
0245      * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
0246      *
0247      * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
0248      *
0249      */
0250     ret = cdv_sb_read(dev, ref_sfr, &ref_value);
0251     if (ret)
0252         return ret;
0253     ref_value &= ~(REF_CLK_MASK);
0254 
0255     /* use DPLL_A for pipeB on CRT/HDMI */
0256     if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
0257         DRM_DEBUG_KMS("use DPLLA for pipe B\n");
0258         ref_value |= REF_CLK_DPLLA;
0259     } else {
0260         DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
0261         ref_value |= REF_CLK_DPLL;
0262     }
0263     ret = cdv_sb_write(dev, ref_sfr, ref_value);
0264     if (ret)
0265         return ret;
0266 
0267     ret = cdv_sb_read(dev, SB_M(pipe), &m);
0268     if (ret)
0269         return ret;
0270     m &= ~SB_M_DIVIDER_MASK;
0271     m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
0272     ret = cdv_sb_write(dev, SB_M(pipe), m);
0273     if (ret)
0274         return ret;
0275 
0276     ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
0277     if (ret)
0278         return ret;
0279 
0280     /* Follow the BIOS to program the N_DIVIDER REG */
0281     n_vco &= 0xFFFF;
0282     n_vco |= 0x107;
0283     n_vco &= ~(SB_N_VCO_SEL_MASK |
0284            SB_N_DIVIDER_MASK |
0285            SB_N_CB_TUNE_MASK);
0286 
0287     n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
0288 
0289     if (clock->vco < 2250000) {
0290         n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
0291         n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
0292     } else if (clock->vco < 2750000) {
0293         n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
0294         n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
0295     } else if (clock->vco < 3300000) {
0296         n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
0297         n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
0298     } else {
0299         n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
0300         n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
0301     }
0302 
0303     ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
0304     if (ret)
0305         return ret;
0306 
0307     ret = cdv_sb_read(dev, SB_P(pipe), &p);
0308     if (ret)
0309         return ret;
0310     p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
0311     p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
0312     switch (clock->p2) {
0313     case 5:
0314         p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
0315         break;
0316     case 10:
0317         p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
0318         break;
0319     case 14:
0320         p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
0321         break;
0322     case 7:
0323         p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
0324         break;
0325     default:
0326         DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
0327         return -EINVAL;
0328     }
0329     ret = cdv_sb_write(dev, SB_P(pipe), p);
0330     if (ret)
0331         return ret;
0332 
0333     if (ddi_select) {
0334         if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
0335             lane_reg = PSB_LANE0;
0336             cdv_sb_read(dev, lane_reg, &lane_value);
0337             lane_value &= ~(LANE_PLL_MASK);
0338             lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
0339             cdv_sb_write(dev, lane_reg, lane_value);
0340 
0341             lane_reg = PSB_LANE1;
0342             cdv_sb_read(dev, lane_reg, &lane_value);
0343             lane_value &= ~(LANE_PLL_MASK);
0344             lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
0345             cdv_sb_write(dev, lane_reg, lane_value);
0346         } else {
0347             lane_reg = PSB_LANE2;
0348             cdv_sb_read(dev, lane_reg, &lane_value);
0349             lane_value &= ~(LANE_PLL_MASK);
0350             lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
0351             cdv_sb_write(dev, lane_reg, lane_value);
0352 
0353             lane_reg = PSB_LANE3;
0354             cdv_sb_read(dev, lane_reg, &lane_value);
0355             lane_value &= ~(LANE_PLL_MASK);
0356             lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
0357             cdv_sb_write(dev, lane_reg, lane_value);
0358         }
0359     }
0360     return 0;
0361 }
0362 
0363 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
0364                          int refclk)
0365 {
0366     const struct gma_limit_t *limit;
0367     if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
0368         /*
0369          * Now only single-channel LVDS is supported on CDV. If it is
0370          * incorrect, please add the dual-channel LVDS.
0371          */
0372         if (refclk == 96000)
0373             limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
0374         else
0375             limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
0376     } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
0377             gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
0378         if (refclk == 27000)
0379             limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
0380         else
0381             limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
0382     } else {
0383         if (refclk == 27000)
0384             limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
0385         else
0386             limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
0387     }
0388     return limit;
0389 }
0390 
0391 /* m1 is reserved as 0 in CDV, n is a ring counter */
0392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
0393 {
0394     clock->m = clock->m2 + 2;
0395     clock->p = clock->p1 * clock->p2;
0396     clock->vco = (refclk * clock->m) / clock->n;
0397     clock->dot = clock->vco / clock->p;
0398 }
0399 
0400 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
0401                   struct drm_crtc *crtc, int target,
0402                   int refclk,
0403                   struct gma_clock_t *best_clock)
0404 {
0405     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0406     struct gma_clock_t clock;
0407 
0408     memset(&clock, 0, sizeof(clock));
0409 
0410     switch (refclk) {
0411     case 27000:
0412         if (target < 200000) {
0413             clock.p1 = 2;
0414             clock.p2 = 10;
0415             clock.n = 1;
0416             clock.m1 = 0;
0417             clock.m2 = 118;
0418         } else {
0419             clock.p1 = 1;
0420             clock.p2 = 10;
0421             clock.n = 1;
0422             clock.m1 = 0;
0423             clock.m2 = 98;
0424         }
0425         break;
0426 
0427     case 100000:
0428         if (target < 200000) {
0429             clock.p1 = 2;
0430             clock.p2 = 10;
0431             clock.n = 5;
0432             clock.m1 = 0;
0433             clock.m2 = 160;
0434         } else {
0435             clock.p1 = 1;
0436             clock.p2 = 10;
0437             clock.n = 5;
0438             clock.m1 = 0;
0439             clock.m2 = 133;
0440         }
0441         break;
0442 
0443     default:
0444         return false;
0445     }
0446 
0447     gma_crtc->clock_funcs->clock(refclk, &clock);
0448     memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
0449     return true;
0450 }
0451 
0452 #define     FIFO_PIPEA      (1 << 0)
0453 #define     FIFO_PIPEB      (1 << 1)
0454 
0455 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
0456 {
0457     struct drm_crtc *crtc;
0458     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0459     struct gma_crtc *gma_crtc = NULL;
0460 
0461     crtc = dev_priv->pipe_to_crtc_mapping[pipe];
0462     gma_crtc = to_gma_crtc(crtc);
0463 
0464     if (crtc->primary->fb == NULL || !gma_crtc->active)
0465         return false;
0466     return true;
0467 }
0468 
0469 void cdv_disable_sr(struct drm_device *dev)
0470 {
0471     if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
0472 
0473         /* Disable self-refresh before adjust WM */
0474         REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
0475         REG_READ(FW_BLC_SELF);
0476 
0477         gma_wait_for_vblank(dev);
0478 
0479         /* Cedarview workaround to write ovelay plane, which force to leave
0480          * MAX_FIFO state.
0481          */
0482         REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
0483         REG_READ(OV_OVADD);
0484 
0485         gma_wait_for_vblank(dev);
0486     }
0487 
0488 }
0489 
0490 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
0491 {
0492     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0493     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0494 
0495     /* Is only one pipe enabled? */
0496     if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
0497         u32 fw;
0498 
0499         fw = REG_READ(DSPFW1);
0500         fw &= ~DSP_FIFO_SR_WM_MASK;
0501         fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
0502         fw &= ~CURSOR_B_FIFO_WM_MASK;
0503         fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
0504         REG_WRITE(DSPFW1, fw);
0505 
0506         fw = REG_READ(DSPFW2);
0507         fw &= ~CURSOR_A_FIFO_WM_MASK;
0508         fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
0509         fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
0510         fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
0511         REG_WRITE(DSPFW2, fw);
0512 
0513         REG_WRITE(DSPFW3, 0x36000000);
0514 
0515         /* ignore FW4 */
0516 
0517         /* Is pipe b lvds ? */
0518         if (gma_crtc->pipe == 1 &&
0519             gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
0520             REG_WRITE(DSPFW5, 0x00040330);
0521         } else {
0522             fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
0523                  (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
0524                  (3 << CURSOR_B_FIFO_WM1_SHIFT) |
0525                  (4 << CURSOR_FIFO_SR_WM1_SHIFT);
0526             REG_WRITE(DSPFW5, fw);
0527         }
0528 
0529         REG_WRITE(DSPFW6, 0x10);
0530 
0531         gma_wait_for_vblank(dev);
0532 
0533         /* enable self-refresh for single pipe active */
0534         REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
0535         REG_READ(FW_BLC_SELF);
0536         gma_wait_for_vblank(dev);
0537 
0538     } else {
0539 
0540         /* HW team suggested values... */
0541         REG_WRITE(DSPFW1, 0x3f880808);
0542         REG_WRITE(DSPFW2, 0x0b020202);
0543         REG_WRITE(DSPFW3, 0x24000000);
0544         REG_WRITE(DSPFW4, 0x08030202);
0545         REG_WRITE(DSPFW5, 0x01010101);
0546         REG_WRITE(DSPFW6, 0x1d0);
0547 
0548         gma_wait_for_vblank(dev);
0549 
0550         dev_priv->ops->disable_sr(dev);
0551     }
0552 }
0553 
0554 /*
0555  * Return the pipe currently connected to the panel fitter,
0556  * or -1 if the panel fitter is not present or not in use
0557  */
0558 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
0559 {
0560     u32 pfit_control;
0561 
0562     pfit_control = REG_READ(PFIT_CONTROL);
0563 
0564     /* See if the panel fitter is in use */
0565     if ((pfit_control & PFIT_ENABLE) == 0)
0566         return -1;
0567     return (pfit_control >> 29) & 0x3;
0568 }
0569 
0570 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
0571                    struct drm_display_mode *mode,
0572                    struct drm_display_mode *adjusted_mode,
0573                    int x, int y,
0574                    struct drm_framebuffer *old_fb)
0575 {
0576     struct drm_device *dev = crtc->dev;
0577     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0578     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0579     int pipe = gma_crtc->pipe;
0580     const struct psb_offset *map = &dev_priv->regmap[pipe];
0581     int refclk;
0582     struct gma_clock_t clock;
0583     u32 dpll = 0, dspcntr, pipeconf;
0584     bool ok;
0585     bool is_lvds = false;
0586     bool is_dp = false;
0587     struct drm_connector_list_iter conn_iter;
0588     struct drm_connector *connector;
0589     const struct gma_limit_t *limit;
0590     u32 ddi_select = 0;
0591     bool is_edp = false;
0592 
0593     drm_connector_list_iter_begin(dev, &conn_iter);
0594     drm_for_each_connector_iter(connector, &conn_iter) {
0595         struct gma_encoder *gma_encoder =
0596                     gma_attached_encoder(connector);
0597 
0598         if (!connector->encoder
0599             || connector->encoder->crtc != crtc)
0600             continue;
0601 
0602         ddi_select = gma_encoder->ddi_select;
0603         switch (gma_encoder->type) {
0604         case INTEL_OUTPUT_LVDS:
0605             is_lvds = true;
0606             break;
0607         case INTEL_OUTPUT_ANALOG:
0608         case INTEL_OUTPUT_HDMI:
0609             break;
0610         case INTEL_OUTPUT_DISPLAYPORT:
0611             is_dp = true;
0612             break;
0613         case INTEL_OUTPUT_EDP:
0614             is_edp = true;
0615             break;
0616         default:
0617             drm_connector_list_iter_end(&conn_iter);
0618             DRM_ERROR("invalid output type.\n");
0619             return 0;
0620         }
0621 
0622         break;
0623     }
0624     drm_connector_list_iter_end(&conn_iter);
0625 
0626     if (dev_priv->dplla_96mhz)
0627         /* low-end sku, 96/100 mhz */
0628         refclk = 96000;
0629     else
0630         /* high-end sku, 27/100 mhz */
0631         refclk = 27000;
0632     if (is_dp || is_edp) {
0633         /*
0634          * Based on the spec the low-end SKU has only CRT/LVDS. So it is
0635          * unnecessary to consider it for DP/eDP.
0636          * On the high-end SKU, it will use the 27/100M reference clk
0637          * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
0638          * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
0639          * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
0640          */
0641         if (pipe == 0)
0642             refclk = 27000;
0643         else
0644             refclk = 100000;
0645     }
0646 
0647     if (is_lvds && dev_priv->lvds_use_ssc) {
0648         refclk = dev_priv->lvds_ssc_freq * 1000;
0649         DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
0650     }
0651 
0652     drm_mode_debug_printmodeline(adjusted_mode);
0653 
0654     limit = gma_crtc->clock_funcs->limit(crtc, refclk);
0655 
0656     ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
0657                  &clock);
0658     if (!ok) {
0659         DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
0660               adjusted_mode->clock, clock.dot);
0661         return 0;
0662     }
0663 
0664     dpll = DPLL_VGA_MODE_DIS;
0665 
0666     if (is_dp || is_edp) {
0667         cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
0668     } else {
0669         REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
0670         REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
0671         REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
0672         REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
0673     }
0674 
0675     dpll |= DPLL_SYNCLOCK_ENABLE;
0676 /*  if (is_lvds)
0677         dpll |= DPLLB_MODE_LVDS;
0678     else
0679         dpll |= DPLLB_MODE_DAC_SERIAL; */
0680     /* dpll |= (2 << 11); */
0681 
0682     /* setup pipeconf */
0683     pipeconf = REG_READ(map->conf);
0684 
0685     pipeconf &= ~(PIPE_BPC_MASK);
0686     if (is_edp) {
0687         switch (dev_priv->edp.bpp) {
0688         case 24:
0689             pipeconf |= PIPE_8BPC;
0690             break;
0691         case 18:
0692             pipeconf |= PIPE_6BPC;
0693             break;
0694         case 30:
0695             pipeconf |= PIPE_10BPC;
0696             break;
0697         default:
0698             pipeconf |= PIPE_8BPC;
0699             break;
0700         }
0701     } else if (is_lvds) {
0702         /* the BPC will be 6 if it is 18-bit LVDS panel */
0703         if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
0704             pipeconf |= PIPE_8BPC;
0705         else
0706             pipeconf |= PIPE_6BPC;
0707     } else
0708         pipeconf |= PIPE_8BPC;
0709 
0710     /* Set up the display plane register */
0711     dspcntr = DISPPLANE_GAMMA_ENABLE;
0712 
0713     if (pipe == 0)
0714         dspcntr |= DISPPLANE_SEL_PIPE_A;
0715     else
0716         dspcntr |= DISPPLANE_SEL_PIPE_B;
0717 
0718     dspcntr |= DISPLAY_PLANE_ENABLE;
0719     pipeconf |= PIPEACONF_ENABLE;
0720 
0721     REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
0722     REG_READ(map->dpll);
0723 
0724     cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
0725 
0726     udelay(150);
0727 
0728 
0729     /* The LVDS pin pair needs to be on before the DPLLs are enabled.
0730      * This is an exception to the general rule that mode_set doesn't turn
0731      * things on.
0732      */
0733     if (is_lvds) {
0734         u32 lvds = REG_READ(LVDS);
0735 
0736         lvds |=
0737             LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
0738             LVDS_PIPEB_SELECT;
0739         /* Set the B0-B3 data pairs corresponding to
0740          * whether we're going to
0741          * set the DPLLs for dual-channel mode or not.
0742          */
0743         if (clock.p2 == 7)
0744             lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
0745         else
0746             lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
0747 
0748         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
0749          * appropriately here, but we need to look more
0750          * thoroughly into how panels behave in the two modes.
0751          */
0752 
0753         REG_WRITE(LVDS, lvds);
0754         REG_READ(LVDS);
0755     }
0756 
0757     dpll |= DPLL_VCO_ENABLE;
0758 
0759     /* Disable the panel fitter if it was on our pipe */
0760     if (cdv_intel_panel_fitter_pipe(dev) == pipe)
0761         REG_WRITE(PFIT_CONTROL, 0);
0762 
0763     DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
0764     drm_mode_debug_printmodeline(mode);
0765 
0766     REG_WRITE(map->dpll,
0767         (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
0768     REG_READ(map->dpll);
0769     /* Wait for the clocks to stabilize. */
0770     udelay(150); /* 42 usec w/o calibration, 110 with.  rounded up. */
0771 
0772     if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
0773         dev_err(dev->dev, "Failed to get DPLL lock\n");
0774         return -EBUSY;
0775     }
0776 
0777     {
0778         int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
0779         REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
0780     }
0781 
0782     REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
0783           ((adjusted_mode->crtc_htotal - 1) << 16));
0784     REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
0785           ((adjusted_mode->crtc_hblank_end - 1) << 16));
0786     REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
0787           ((adjusted_mode->crtc_hsync_end - 1) << 16));
0788     REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
0789           ((adjusted_mode->crtc_vtotal - 1) << 16));
0790     REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
0791           ((adjusted_mode->crtc_vblank_end - 1) << 16));
0792     REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
0793           ((adjusted_mode->crtc_vsync_end - 1) << 16));
0794     /* pipesrc and dspsize control the size that is scaled from,
0795      * which should always be the user's requested size.
0796      */
0797     REG_WRITE(map->size,
0798           ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
0799     REG_WRITE(map->pos, 0);
0800     REG_WRITE(map->src,
0801           ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
0802     REG_WRITE(map->conf, pipeconf);
0803     REG_READ(map->conf);
0804 
0805     gma_wait_for_vblank(dev);
0806 
0807     REG_WRITE(map->cntr, dspcntr);
0808 
0809     /* Flush the plane changes */
0810     {
0811         const struct drm_crtc_helper_funcs *crtc_funcs =
0812             crtc->helper_private;
0813         crtc_funcs->mode_set_base(crtc, x, y, old_fb);
0814     }
0815 
0816     gma_wait_for_vblank(dev);
0817 
0818     return 0;
0819 }
0820 
0821 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
0822 
0823 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
0824 
0825 static void i8xx_clock(int refclk, struct gma_clock_t *clock)
0826 {
0827     clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
0828     clock->p = clock->p1 * clock->p2;
0829     clock->vco = refclk * clock->m / (clock->n + 2);
0830     clock->dot = clock->vco / clock->p;
0831 }
0832 
0833 /* Returns the clock of the currently programmed mode of the given pipe. */
0834 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
0835                 struct drm_crtc *crtc)
0836 {
0837     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0838     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0839     int pipe = gma_crtc->pipe;
0840     const struct psb_offset *map = &dev_priv->regmap[pipe];
0841     u32 dpll;
0842     u32 fp;
0843     struct gma_clock_t clock;
0844     bool is_lvds;
0845     struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
0846 
0847     if (gma_power_begin(dev, false)) {
0848         dpll = REG_READ(map->dpll);
0849         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
0850             fp = REG_READ(map->fp0);
0851         else
0852             fp = REG_READ(map->fp1);
0853         is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
0854         gma_power_end(dev);
0855     } else {
0856         dpll = p->dpll;
0857         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
0858             fp = p->fp0;
0859         else
0860             fp = p->fp1;
0861 
0862         is_lvds = (pipe == 1) &&
0863                 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
0864     }
0865 
0866     clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
0867     clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
0868     clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
0869 
0870     if (is_lvds) {
0871         clock.p1 =
0872             ffs((dpll &
0873              DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
0874             DPLL_FPA01_P1_POST_DIV_SHIFT);
0875         if (clock.p1 == 0) {
0876             clock.p1 = 4;
0877             dev_err(dev->dev, "PLL %d\n", dpll);
0878         }
0879         clock.p2 = 14;
0880 
0881         if ((dpll & PLL_REF_INPUT_MASK) ==
0882             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
0883             /* XXX: might not be 66MHz */
0884             i8xx_clock(66000, &clock);
0885         } else
0886             i8xx_clock(48000, &clock);
0887     } else {
0888         if (dpll & PLL_P1_DIVIDE_BY_TWO)
0889             clock.p1 = 2;
0890         else {
0891             clock.p1 =
0892                 ((dpll &
0893                   DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
0894                  DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
0895         }
0896         if (dpll & PLL_P2_DIVIDE_BY_4)
0897             clock.p2 = 4;
0898         else
0899             clock.p2 = 2;
0900 
0901         i8xx_clock(48000, &clock);
0902     }
0903 
0904     /* XXX: It would be nice to validate the clocks, but we can't reuse
0905      * i830PllIsValid() because it relies on the xf86_config connector
0906      * configuration being accurate, which it isn't necessarily.
0907      */
0908 
0909     return clock.dot;
0910 }
0911 
0912 /** Returns the currently programmed mode of the given pipe. */
0913 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
0914                          struct drm_crtc *crtc)
0915 {
0916     struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
0917     int pipe = gma_crtc->pipe;
0918     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0919     struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
0920     const struct psb_offset *map = &dev_priv->regmap[pipe];
0921     struct drm_display_mode *mode;
0922     int htot;
0923     int hsync;
0924     int vtot;
0925     int vsync;
0926 
0927     if (gma_power_begin(dev, false)) {
0928         htot = REG_READ(map->htotal);
0929         hsync = REG_READ(map->hsync);
0930         vtot = REG_READ(map->vtotal);
0931         vsync = REG_READ(map->vsync);
0932         gma_power_end(dev);
0933     } else {
0934         htot = p->htotal;
0935         hsync = p->hsync;
0936         vtot = p->vtotal;
0937         vsync = p->vsync;
0938     }
0939 
0940     mode = kzalloc(sizeof(*mode), GFP_KERNEL);
0941     if (!mode)
0942         return NULL;
0943 
0944     mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
0945     mode->hdisplay = (htot & 0xffff) + 1;
0946     mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
0947     mode->hsync_start = (hsync & 0xffff) + 1;
0948     mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
0949     mode->vdisplay = (vtot & 0xffff) + 1;
0950     mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
0951     mode->vsync_start = (vsync & 0xffff) + 1;
0952     mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
0953 
0954     drm_mode_set_name(mode);
0955     drm_mode_set_crtcinfo(mode, 0);
0956 
0957     return mode;
0958 }
0959 
0960 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
0961     .dpms = gma_crtc_dpms,
0962     .mode_set = cdv_intel_crtc_mode_set,
0963     .mode_set_base = gma_pipe_set_base,
0964     .prepare = gma_crtc_prepare,
0965     .commit = gma_crtc_commit,
0966     .disable = gma_crtc_disable,
0967 };
0968 
0969 const struct gma_clock_funcs cdv_clock_funcs = {
0970     .clock = cdv_intel_clock,
0971     .limit = cdv_intel_limit,
0972     .pll_is_valid = gma_pll_is_valid,
0973 };
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