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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**************************************************************************
0003  * Copyright (c) 2011, Intel Corporation.
0004  * All Rights Reserved.
0005  *
0006  **************************************************************************/
0007 
0008 #include <linux/backlight.h>
0009 #include <linux/delay.h>
0010 
0011 #include <drm/drm.h>
0012 
0013 #include "cdv_device.h"
0014 #include "gma_device.h"
0015 #include "intel_bios.h"
0016 #include "psb_drv.h"
0017 #include "psb_intel_reg.h"
0018 #include "psb_reg.h"
0019 
0020 #define VGA_SR_INDEX        0x3c4
0021 #define VGA_SR_DATA     0x3c5
0022 
0023 static void cdv_disable_vga(struct drm_device *dev)
0024 {
0025     u8 sr1;
0026     u32 vga_reg;
0027 
0028     vga_reg = VGACNTRL;
0029 
0030     outb(1, VGA_SR_INDEX);
0031     sr1 = inb(VGA_SR_DATA);
0032     outb(sr1 | 1<<5, VGA_SR_DATA);
0033     udelay(300);
0034 
0035     REG_WRITE(vga_reg, VGA_DISP_DISABLE);
0036     REG_READ(vga_reg);
0037 }
0038 
0039 static int cdv_output_init(struct drm_device *dev)
0040 {
0041     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0042 
0043     drm_mode_create_scaling_mode_property(dev);
0044 
0045     cdv_disable_vga(dev);
0046 
0047     cdv_intel_crt_init(dev, &dev_priv->mode_dev);
0048     cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
0049 
0050     /* These bits indicate HDMI not SDVO on CDV */
0051     if (REG_READ(SDVOB) & SDVO_DETECTED) {
0052         cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
0053         if (REG_READ(DP_B) & DP_DETECTED)
0054             cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);
0055     }
0056 
0057     if (REG_READ(SDVOC) & SDVO_DETECTED) {
0058         cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
0059         if (REG_READ(DP_C) & DP_DETECTED)
0060             cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);
0061     }
0062     return 0;
0063 }
0064 
0065 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
0066 
0067 /*
0068  *  Cedartrail Backlght Interfaces
0069  */
0070 
0071 static struct backlight_device *cdv_backlight_device;
0072 
0073 static int cdv_backlight_combination_mode(struct drm_device *dev)
0074 {
0075     return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
0076 }
0077 
0078 static u32 cdv_get_max_backlight(struct drm_device *dev)
0079 {
0080     u32 max = REG_READ(BLC_PWM_CTL);
0081 
0082     if (max == 0) {
0083         DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
0084         /* i915 does this, I believe which means that we should not
0085          * smash PWM control as firmware will take control of it. */
0086         return 1;
0087     }
0088 
0089     max >>= 16;
0090     if (cdv_backlight_combination_mode(dev))
0091         max *= 0xff;
0092     return max;
0093 }
0094 
0095 static int cdv_get_brightness(struct backlight_device *bd)
0096 {
0097     struct drm_device *dev = bl_get_data(bd);
0098     struct pci_dev *pdev = to_pci_dev(dev->dev);
0099     u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
0100 
0101     if (cdv_backlight_combination_mode(dev)) {
0102         u8 lbpc;
0103 
0104         val &= ~1;
0105         pci_read_config_byte(pdev, 0xF4, &lbpc);
0106         val *= lbpc;
0107     }
0108     return (val * 100)/cdv_get_max_backlight(dev);
0109 
0110 }
0111 
0112 static int cdv_set_brightness(struct backlight_device *bd)
0113 {
0114     struct drm_device *dev = bl_get_data(bd);
0115     struct pci_dev *pdev = to_pci_dev(dev->dev);
0116     int level = bd->props.brightness;
0117     u32 blc_pwm_ctl;
0118 
0119     /* Percentage 1-100% being valid */
0120     if (level < 1)
0121         level = 1;
0122 
0123     level *= cdv_get_max_backlight(dev);
0124     level /= 100;
0125 
0126     if (cdv_backlight_combination_mode(dev)) {
0127         u32 max = cdv_get_max_backlight(dev);
0128         u8 lbpc;
0129 
0130         lbpc = level * 0xfe / max + 1;
0131         level /= lbpc;
0132 
0133         pci_write_config_byte(pdev, 0xF4, lbpc);
0134     }
0135 
0136     blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
0137     REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
0138                 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
0139     return 0;
0140 }
0141 
0142 static const struct backlight_ops cdv_ops = {
0143     .get_brightness = cdv_get_brightness,
0144     .update_status  = cdv_set_brightness,
0145 };
0146 
0147 static int cdv_backlight_init(struct drm_device *dev)
0148 {
0149     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0150     struct backlight_properties props;
0151 
0152     memset(&props, 0, sizeof(struct backlight_properties));
0153     props.max_brightness = 100;
0154     props.type = BACKLIGHT_PLATFORM;
0155 
0156     cdv_backlight_device = backlight_device_register("psb-bl",
0157                     NULL, (void *)dev, &cdv_ops, &props);
0158     if (IS_ERR(cdv_backlight_device))
0159         return PTR_ERR(cdv_backlight_device);
0160 
0161     cdv_backlight_device->props.brightness =
0162             cdv_get_brightness(cdv_backlight_device);
0163     backlight_update_status(cdv_backlight_device);
0164     dev_priv->backlight_device = cdv_backlight_device;
0165     dev_priv->backlight_enabled = true;
0166     return 0;
0167 }
0168 
0169 #endif
0170 
0171 /*
0172  *  Provide the Cedarview specific chip logic and low level methods
0173  *  for power management
0174  *
0175  *  FIXME: we need to implement the apm/ospm base management bits
0176  *  for this and the MID devices.
0177  */
0178 
0179 static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset)
0180 {
0181     int mcr = (0x10<<24) | (port << 16) | (offset << 8);
0182     uint32_t ret_val = 0;
0183     struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
0184     pci_write_config_dword(pci_root, 0xD0, mcr);
0185     pci_read_config_dword(pci_root, 0xD4, &ret_val);
0186     pci_dev_put(pci_root);
0187     return ret_val;
0188 }
0189 
0190 static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset,
0191                    u32 value)
0192 {
0193     int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
0194     struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
0195     pci_write_config_dword(pci_root, 0xD4, value);
0196     pci_write_config_dword(pci_root, 0xD0, mcr);
0197     pci_dev_put(pci_root);
0198 }
0199 
0200 #define PSB_PM_SSC          0x20
0201 #define PSB_PM_SSS          0x30
0202 #define PSB_PWRGT_GFX_ON        0x02
0203 #define PSB_PWRGT_GFX_OFF       0x01
0204 #define PSB_PWRGT_GFX_D0        0x00
0205 #define PSB_PWRGT_GFX_D3        0x03
0206 
0207 static void cdv_init_pm(struct drm_device *dev)
0208 {
0209     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0210     struct pci_dev *pdev = to_pci_dev(dev->dev);
0211     u32 pwr_cnt;
0212     int domain = pci_domain_nr(pdev->bus);
0213     int i;
0214 
0215     dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
0216                             PSB_APMBA) & 0xFFFF;
0217     dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
0218                             PSB_OSPMBA) & 0xFFFF;
0219 
0220     /* Power status */
0221     pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
0222 
0223     /* Enable the GPU */
0224     pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
0225     pwr_cnt |= PSB_PWRGT_GFX_ON;
0226     outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
0227 
0228     /* Wait for the GPU power */
0229     for (i = 0; i < 5; i++) {
0230         u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
0231         if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
0232             return;
0233         udelay(10);
0234     }
0235     dev_err(dev->dev, "GPU: power management timed out.\n");
0236 }
0237 
0238 static void cdv_errata(struct drm_device *dev)
0239 {
0240     struct pci_dev *pdev = to_pci_dev(dev->dev);
0241 
0242     /* Disable bonus launch.
0243      *  CPU and GPU competes for memory and display misses updates and
0244      *  flickers. Worst with dual core, dual displays.
0245      *
0246      *  Fixes were done to Win 7 gfx driver to disable a feature called
0247      *  Bonus Launch to work around the issue, by degrading
0248      *  performance.
0249      */
0250      CDV_MSG_WRITE32(pci_domain_nr(pdev->bus), 3, 0x30, 0x08027108);
0251 }
0252 
0253 /**
0254  *  cdv_save_display_registers  -   save registers lost on suspend
0255  *  @dev: our DRM device
0256  *
0257  *  Save the state we need in order to be able to restore the interface
0258  *  upon resume from suspend
0259  */
0260 static int cdv_save_display_registers(struct drm_device *dev)
0261 {
0262     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0263     struct pci_dev *pdev = to_pci_dev(dev->dev);
0264     struct psb_save_area *regs = &dev_priv->regs;
0265     struct drm_connector_list_iter conn_iter;
0266     struct drm_connector *connector;
0267 
0268     dev_dbg(dev->dev, "Saving GPU registers.\n");
0269 
0270     pci_read_config_byte(pdev, 0xF4, &regs->cdv.saveLBB);
0271 
0272     regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
0273     regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
0274 
0275     regs->cdv.saveDSPARB = REG_READ(DSPARB);
0276     regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
0277     regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
0278     regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
0279     regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
0280     regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
0281     regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
0282 
0283     regs->cdv.saveADPA = REG_READ(ADPA);
0284 
0285     regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
0286     regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
0287     regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
0288     regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
0289     regs->cdv.saveLVDS = REG_READ(LVDS);
0290 
0291     regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
0292 
0293     regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
0294     regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
0295     regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
0296 
0297     regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
0298 
0299     regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
0300     regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
0301 
0302     drm_connector_list_iter_begin(dev, &conn_iter);
0303     drm_for_each_connector_iter(connector, &conn_iter)
0304         connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
0305     drm_connector_list_iter_end(&conn_iter);
0306 
0307     return 0;
0308 }
0309 
0310 /**
0311  *  cdv_restore_display_registers   -   restore lost register state
0312  *  @dev: our DRM device
0313  *
0314  *  Restore register state that was lost during suspend and resume.
0315  *
0316  *  FIXME: review
0317  */
0318 static int cdv_restore_display_registers(struct drm_device *dev)
0319 {
0320     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0321     struct pci_dev *pdev = to_pci_dev(dev->dev);
0322     struct psb_save_area *regs = &dev_priv->regs;
0323     struct drm_connector_list_iter conn_iter;
0324     struct drm_connector *connector;
0325     u32 temp;
0326 
0327     pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB);
0328 
0329     REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
0330     REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
0331 
0332     /* BIOS does below anyway */
0333     REG_WRITE(DPIO_CFG, 0);
0334     REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
0335 
0336     temp = REG_READ(DPLL_A);
0337     if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
0338         REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
0339         REG_READ(DPLL_A);
0340     }
0341 
0342     temp = REG_READ(DPLL_B);
0343     if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
0344         REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
0345         REG_READ(DPLL_B);
0346     }
0347 
0348     udelay(500);
0349 
0350     REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
0351     REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
0352     REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
0353     REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
0354     REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
0355     REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
0356 
0357     REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
0358     REG_WRITE(ADPA, regs->cdv.saveADPA);
0359 
0360     REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
0361     REG_WRITE(LVDS, regs->cdv.saveLVDS);
0362     REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
0363     REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
0364     REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
0365     REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
0366     REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
0367     REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
0368     REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
0369 
0370     REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
0371 
0372     REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
0373     REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
0374 
0375     /* Fix arbitration bug */
0376     cdv_errata(dev);
0377 
0378     drm_mode_config_reset(dev);
0379 
0380     drm_connector_list_iter_begin(dev, &conn_iter);
0381     drm_for_each_connector_iter(connector, &conn_iter)
0382         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
0383     drm_connector_list_iter_end(&conn_iter);
0384 
0385     /* Resume the modeset for every activated CRTC */
0386     drm_helper_resume_force_mode(dev);
0387     return 0;
0388 }
0389 
0390 static int cdv_power_down(struct drm_device *dev)
0391 {
0392     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0393     u32 pwr_cnt, pwr_mask, pwr_sts;
0394     int tries = 5;
0395 
0396     pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
0397     pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
0398     pwr_cnt |= PSB_PWRGT_GFX_OFF;
0399     pwr_mask = PSB_PWRGT_GFX_MASK;
0400 
0401     outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
0402 
0403     while (tries--) {
0404         pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
0405         if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
0406             return 0;
0407         udelay(10);
0408     }
0409     return 0;
0410 }
0411 
0412 static int cdv_power_up(struct drm_device *dev)
0413 {
0414     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0415     u32 pwr_cnt, pwr_mask, pwr_sts;
0416     int tries = 5;
0417 
0418     pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
0419     pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
0420     pwr_cnt |= PSB_PWRGT_GFX_ON;
0421     pwr_mask = PSB_PWRGT_GFX_MASK;
0422 
0423     outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
0424 
0425     while (tries--) {
0426         pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
0427         if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
0428             return 0;
0429         udelay(10);
0430     }
0431     return 0;
0432 }
0433 
0434 static void cdv_hotplug_work_func(struct work_struct *work)
0435 {
0436         struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
0437                             hotplug_work);
0438     struct drm_device *dev = &dev_priv->dev;
0439 
0440         /* Just fire off a uevent and let userspace tell us what to do */
0441         drm_helper_hpd_irq_event(dev);
0442 }
0443 
0444 /* The core driver has received a hotplug IRQ. We are in IRQ context
0445    so extract the needed information and kick off queued processing */
0446 
0447 static int cdv_hotplug_event(struct drm_device *dev)
0448 {
0449     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0450     schedule_work(&dev_priv->hotplug_work);
0451     REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
0452     return 1;
0453 }
0454 
0455 static void cdv_hotplug_enable(struct drm_device *dev, bool on)
0456 {
0457     if (on) {
0458         u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
0459         hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
0460                HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
0461         REG_WRITE(PORT_HOTPLUG_EN, hotplug);
0462     }  else {
0463         REG_WRITE(PORT_HOTPLUG_EN, 0);
0464         REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
0465     }
0466 }
0467 
0468 static const char *force_audio_names[] = {
0469     "off",
0470     "auto",
0471     "on",
0472 };
0473 
0474 void cdv_intel_attach_force_audio_property(struct drm_connector *connector)
0475 {
0476     struct drm_device *dev = connector->dev;
0477     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0478     struct drm_property *prop;
0479     int i;
0480 
0481     prop = dev_priv->force_audio_property;
0482     if (prop == NULL) {
0483         prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
0484                        "audio",
0485                        ARRAY_SIZE(force_audio_names));
0486         if (prop == NULL)
0487             return;
0488 
0489         for (i = 0; i < ARRAY_SIZE(force_audio_names); i++)
0490             drm_property_add_enum(prop, i-1, force_audio_names[i]);
0491 
0492         dev_priv->force_audio_property = prop;
0493     }
0494     drm_object_attach_property(&connector->base, prop, 0);
0495 }
0496 
0497 
0498 static const char *broadcast_rgb_names[] = {
0499     "Full",
0500     "Limited 16:235",
0501 };
0502 
0503 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector)
0504 {
0505     struct drm_device *dev = connector->dev;
0506     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0507     struct drm_property *prop;
0508     int i;
0509 
0510     prop = dev_priv->broadcast_rgb_property;
0511     if (prop == NULL) {
0512         prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
0513                        "Broadcast RGB",
0514                        ARRAY_SIZE(broadcast_rgb_names));
0515         if (prop == NULL)
0516             return;
0517 
0518         for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++)
0519             drm_property_add_enum(prop, i, broadcast_rgb_names[i]);
0520 
0521         dev_priv->broadcast_rgb_property = prop;
0522     }
0523 
0524     drm_object_attach_property(&connector->base, prop, 0);
0525 }
0526 
0527 /* Cedarview */
0528 static const struct psb_offset cdv_regmap[2] = {
0529     {
0530         .fp0 = FPA0,
0531         .fp1 = FPA1,
0532         .cntr = DSPACNTR,
0533         .conf = PIPEACONF,
0534         .src = PIPEASRC,
0535         .dpll = DPLL_A,
0536         .dpll_md = DPLL_A_MD,
0537         .htotal = HTOTAL_A,
0538         .hblank = HBLANK_A,
0539         .hsync = HSYNC_A,
0540         .vtotal = VTOTAL_A,
0541         .vblank = VBLANK_A,
0542         .vsync = VSYNC_A,
0543         .stride = DSPASTRIDE,
0544         .size = DSPASIZE,
0545         .pos = DSPAPOS,
0546         .base = DSPABASE,
0547         .surf = DSPASURF,
0548         .addr = DSPABASE,
0549         .status = PIPEASTAT,
0550         .linoff = DSPALINOFF,
0551         .tileoff = DSPATILEOFF,
0552         .palette = PALETTE_A,
0553     },
0554     {
0555         .fp0 = FPB0,
0556         .fp1 = FPB1,
0557         .cntr = DSPBCNTR,
0558         .conf = PIPEBCONF,
0559         .src = PIPEBSRC,
0560         .dpll = DPLL_B,
0561         .dpll_md = DPLL_B_MD,
0562         .htotal = HTOTAL_B,
0563         .hblank = HBLANK_B,
0564         .hsync = HSYNC_B,
0565         .vtotal = VTOTAL_B,
0566         .vblank = VBLANK_B,
0567         .vsync = VSYNC_B,
0568         .stride = DSPBSTRIDE,
0569         .size = DSPBSIZE,
0570         .pos = DSPBPOS,
0571         .base = DSPBBASE,
0572         .surf = DSPBSURF,
0573         .addr = DSPBBASE,
0574         .status = PIPEBSTAT,
0575         .linoff = DSPBLINOFF,
0576         .tileoff = DSPBTILEOFF,
0577         .palette = PALETTE_B,
0578     }
0579 };
0580 
0581 static int cdv_chip_setup(struct drm_device *dev)
0582 {
0583     struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
0584     INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
0585 
0586     dev_priv->use_msi = true;
0587     dev_priv->regmap = cdv_regmap;
0588     gma_get_core_freq(dev);
0589     psb_intel_opregion_init(dev);
0590     psb_intel_init_bios(dev);
0591     cdv_hotplug_enable(dev, false);
0592     return 0;
0593 }
0594 
0595 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
0596 
0597 const struct psb_ops cdv_chip_ops = {
0598     .name = "GMA3600/3650",
0599     .pipes = 2,
0600     .crtcs = 2,
0601     .hdmi_mask = (1 << 0) | (1 << 1),
0602     .lvds_mask = (1 << 1),
0603     .sdvo_mask = (1 << 0),
0604     .cursor_needs_phys = 0,
0605     .sgx_offset = MRST_SGX_OFFSET,
0606     .chip_setup = cdv_chip_setup,
0607     .errata = cdv_errata,
0608 
0609     .crtc_helper = &cdv_intel_helper_funcs,
0610     .clock_funcs = &cdv_clock_funcs,
0611 
0612     .output_init = cdv_output_init,
0613     .hotplug = cdv_hotplug_event,
0614     .hotplug_enable = cdv_hotplug_enable,
0615 
0616 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
0617     .backlight_init = cdv_backlight_init,
0618 #endif
0619 
0620     .init_pm = cdv_init_pm,
0621     .save_regs = cdv_save_display_registers,
0622     .restore_regs = cdv_restore_display_registers,
0623     .save_crtc = gma_crtc_save,
0624     .restore_crtc = gma_crtc_restore,
0625     .power_down = cdv_power_down,
0626     .power_up = cdv_power_up,
0627     .update_wm = cdv_update_wm,
0628     .disable_sr = cdv_disable_sr,
0629 };
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