drm/fsl-dcu/fsl_dcu_drm_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2015 Freescale Semiconductor, Inc.
0004  *
0005  * Freescale DCU drm device driver
0006  */
0007
0008 #ifndef __FSL_DCU_DRM_DRV_H__
0009 #define __FSL_DCU_DRM_DRV_H__
0010
0011 #include <drm/drm_encoder.h>
0012
0013 #include "fsl_dcu_drm_crtc.h"
0014 #include "fsl_dcu_drm_output.h"
0015 #include "fsl_dcu_drm_plane.h"
0016
0017 #define DCU_DCU_MODE            0x0010
0018 #define DCU_MODE_BLEND_ITER(x)      ((x) << 20)
0019 #define DCU_MODE_RASTER_EN      BIT(14)
0020 #define DCU_MODE_DCU_MODE(x)        (x)
0021 #define DCU_MODE_DCU_MODE_MASK      0x03
0022 #define DCU_MODE_OFF            0
0023 #define DCU_MODE_NORMAL         1
0024 #define DCU_MODE_TEST           2
0025 #define DCU_MODE_COLORBAR       3
0026
0027 #define DCU_BGND            0x0014
0028 #define DCU_BGND_R(x)           ((x) << 16)
0029 #define DCU_BGND_G(x)           ((x) << 8)
0030 #define DCU_BGND_B(x)           (x)
0031
0032 #define DCU_DISP_SIZE           0x0018
0033 #define DCU_DISP_SIZE_DELTA_Y(x)    ((x) << 16)
0034 /*Regisiter value 1/16 of horizontal resolution*/
0035 #define DCU_DISP_SIZE_DELTA_X(x)    ((x) >> 4)
0036
0037 #define DCU_HSYN_PARA           0x001c
0038 #define DCU_HSYN_PARA_BP(x)     ((x) << 22)
0039 #define DCU_HSYN_PARA_PW(x)     ((x) << 11)
0040 #define DCU_HSYN_PARA_FP(x)     (x)
0041
0042 #define DCU_VSYN_PARA           0x0020
0043 #define DCU_VSYN_PARA_BP(x)     ((x) << 22)
0044 #define DCU_VSYN_PARA_PW(x)     ((x) << 11)
0045 #define DCU_VSYN_PARA_FP(x)     (x)
0046
0047 #define DCU_SYN_POL         0x0024
0048 #define DCU_SYN_POL_INV_PXCK        BIT(6)
0049 #define DCU_SYN_POL_NEG         BIT(5)
0050 #define DCU_SYN_POL_INV_VS_LOW      BIT(1)
0051 #define DCU_SYN_POL_INV_HS_LOW      BIT(0)
0052
0053 #define DCU_THRESHOLD           0x0028
0054 #define DCU_THRESHOLD_LS_BF_VS(x)   ((x) << 16)
0055 #define DCU_THRESHOLD_OUT_BUF_HIGH(x)   ((x) << 8)
0056 #define DCU_THRESHOLD_OUT_BUF_LOW(x)    (x)
0057 #define BF_VS_VAL           0x03
0058 #define BUF_MAX_VAL         0x78
0059 #define BUF_MIN_VAL         0x0a
0060
0061 #define DCU_INT_STATUS          0x002C
0062 #define DCU_INT_STATUS_VSYNC        BIT(0)
0063 #define DCU_INT_STATUS_UNDRUN       BIT(1)
0064 #define DCU_INT_STATUS_LSBFVS       BIT(2)
0065 #define DCU_INT_STATUS_VBLANK       BIT(3)
0066 #define DCU_INT_STATUS_CRCREADY     BIT(4)
0067 #define DCU_INT_STATUS_CRCOVERFLOW  BIT(5)
0068 #define DCU_INT_STATUS_P1FIFOLO     BIT(6)
0069 #define DCU_INT_STATUS_P1FIFOHI     BIT(7)
0070 #define DCU_INT_STATUS_P2FIFOLO     BIT(8)
0071 #define DCU_INT_STATUS_P2FIFOHI     BIT(9)
0072 #define DCU_INT_STATUS_PROGEND      BIT(10)
0073 #define DCU_INT_STATUS_IPMERROR     BIT(11)
0074 #define DCU_INT_STATUS_LYRTRANS     BIT(12)
0075 #define DCU_INT_STATUS_DMATRANS     BIT(14)
0076 #define DCU_INT_STATUS_P3FIFOLO     BIT(16)
0077 #define DCU_INT_STATUS_P3FIFOHI     BIT(17)
0078 #define DCU_INT_STATUS_P4FIFOLO     BIT(18)
0079 #define DCU_INT_STATUS_P4FIFOHI     BIT(19)
0080 #define DCU_INT_STATUS_P1EMPTY      BIT(26)
0081 #define DCU_INT_STATUS_P2EMPTY      BIT(27)
0082 #define DCU_INT_STATUS_P3EMPTY      BIT(28)
0083 #define DCU_INT_STATUS_P4EMPTY      BIT(29)
0084
0085 #define DCU_INT_MASK            0x0030
0086 #define DCU_INT_MASK_VSYNC      BIT(0)
0087 #define DCU_INT_MASK_UNDRUN     BIT(1)
0088 #define DCU_INT_MASK_LSBFVS     BIT(2)
0089 #define DCU_INT_MASK_VBLANK     BIT(3)
0090 #define DCU_INT_MASK_CRCREADY       BIT(4)
0091 #define DCU_INT_MASK_CRCOVERFLOW    BIT(5)
0092 #define DCU_INT_MASK_P1FIFOLO       BIT(6)
0093 #define DCU_INT_MASK_P1FIFOHI       BIT(7)
0094 #define DCU_INT_MASK_P2FIFOLO       BIT(8)
0095 #define DCU_INT_MASK_P2FIFOHI       BIT(9)
0096 #define DCU_INT_MASK_PROGEND        BIT(10)
0097 #define DCU_INT_MASK_IPMERROR       BIT(11)
0098 #define DCU_INT_MASK_LYRTRANS       BIT(12)
0099 #define DCU_INT_MASK_DMATRANS       BIT(14)
0100 #define DCU_INT_MASK_P3FIFOLO       BIT(16)
0101 #define DCU_INT_MASK_P3FIFOHI       BIT(17)
0102 #define DCU_INT_MASK_P4FIFOLO       BIT(18)
0103 #define DCU_INT_MASK_P4FIFOHI       BIT(19)
0104 #define DCU_INT_MASK_P1EMPTY        BIT(26)
0105 #define DCU_INT_MASK_P2EMPTY        BIT(27)
0106 #define DCU_INT_MASK_P3EMPTY        BIT(28)
0107 #define DCU_INT_MASK_P4EMPTY        BIT(29)
0108
0109 #define DCU_DIV_RATIO           0x0054
0110
0111 #define DCU_UPDATE_MODE         0x00cc
0112 #define DCU_UPDATE_MODE_MODE        BIT(31)
0113 #define DCU_UPDATE_MODE_READREG     BIT(30)
0114
0115 #define DCU_DCFB_MAX            0x300
0116
0117 #define DCU_CTRLDESCLN(layer, reg)  (0x200 + (reg - 1) * 4 + (layer) * 0x40)
0118
0119 #define DCU_LAYER_HEIGHT(x)     ((x) << 16)
0120 #define DCU_LAYER_WIDTH(x)      (x)
0121
0122 #define DCU_LAYER_POSY(x)       ((x) << 16)
0123 #define DCU_LAYER_POSX(x)       (x)
0124
0125 #define DCU_LAYER_EN            BIT(31)
0126 #define DCU_LAYER_TILE_EN       BIT(30)
0127 #define DCU_LAYER_DATA_SEL_CLUT     BIT(29)
0128 #define DCU_LAYER_SAFETY_EN     BIT(28)
0129 #define DCU_LAYER_TRANS(x)      ((x) << 20)
0130 #define DCU_LAYER_BPP(x)        ((x) << 16)
0131 #define DCU_LAYER_RLE_EN        BIT(15)
0132 #define DCU_LAYER_LUOFFS(x)     ((x) << 4)
0133 #define DCU_LAYER_BB_ON         BIT(2)
0134 #define DCU_LAYER_AB_NONE       0
0135 #define DCU_LAYER_AB_CHROMA_KEYING  1
0136 #define DCU_LAYER_AB_WHOLE_FRAME    2
0137
0138 #define DCU_LAYER_CKMAX_R(x)        ((x) << 16)
0139 #define DCU_LAYER_CKMAX_G(x)        ((x) << 8)
0140 #define DCU_LAYER_CKMAX_B(x)        (x)
0141
0142 #define DCU_LAYER_CKMIN_R(x)        ((x) << 16)
0143 #define DCU_LAYER_CKMIN_G(x)        ((x) << 8)
0144 #define DCU_LAYER_CKMIN_B(x)        (x)
0145
0146 #define DCU_LAYER_TILE_VER(x)       ((x) << 16)
0147 #define DCU_LAYER_TILE_HOR(x)       (x)
0148
0149 #define DCU_LAYER_FG_FCOLOR(x)      (x)
0150
0151 #define DCU_LAYER_BG_BCOLOR(x)      (x)
0152
0153 #define DCU_LAYER_POST_SKIP(x)      ((x) << 16)
0154 #define DCU_LAYER_PRE_SKIP(x)       (x)
0155
0156 #define FSL_DCU_RGB565          4
0157 #define FSL_DCU_RGB888          5
0158 #define FSL_DCU_ARGB8888        6
0159 #define FSL_DCU_ARGB1555        11
0160 #define FSL_DCU_ARGB4444        12
0161 #define FSL_DCU_YUV422          14
0162
0163 #define VF610_LAYER_REG_NUM     9
0164 #define LS1021A_LAYER_REG_NUM       10
0165
0166 struct clk;
0167 struct device;
0168 struct drm_device;
0169
0170 struct fsl_dcu_soc_data {
0171     const char *name;
0172     /*total layer number*/
0173     unsigned int total_layer;
0174     /*max layer number DCU supported*/
0175     unsigned int max_layer;
0176     unsigned int layer_regs;
0177 };
0178
0179 struct fsl_dcu_drm_device {
0180     struct device *dev;
0181     struct device_node *np;
0182     struct regmap *regmap;
0183     int irq;
0184     struct clk *clk;
0185     struct clk *pix_clk;
0186     struct fsl_tcon *tcon;
0187     /*protects hardware register*/
0188     spinlock_t irq_lock;
0189     struct drm_device *drm;
0190     struct drm_crtc crtc;
0191     struct drm_encoder encoder;
0192     struct fsl_dcu_drm_connector connector;
0193     const struct fsl_dcu_soc_data *soc;
0194 };
0195
0196 int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev);
0197
0198 #endif /* __FSL_DCU_DRM_DRV_H__ */