drm/fsl-dcu/fsl_dcu_drm_crtc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2015 Freescale Semiconductor, Inc.
0004  *
0005  * Freescale DCU drm device driver
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/regmap.h>
0010
0011 #include <video/videomode.h>
0012
0013 #include <drm/drm_atomic.h>
0014 #include <drm/drm_atomic_helper.h>
0015 #include <drm/drm_crtc.h>
0016 #include <drm/drm_probe_helper.h>
0017 #include <drm/drm_vblank.h>
0018
0019 #include "fsl_dcu_drm_crtc.h"
0020 #include "fsl_dcu_drm_drv.h"
0021 #include "fsl_dcu_drm_plane.h"
0022
0023 static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
0024                       struct drm_atomic_state *state)
0025 {
0026     struct drm_device *dev = crtc->dev;
0027     struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
0028     struct drm_pending_vblank_event *event = crtc->state->event;
0029
0030     regmap_write(fsl_dev->regmap,
0031              DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
0032
0033     if (event) {
0034         crtc->state->event = NULL;
0035
0036         spin_lock_irq(&crtc->dev->event_lock);
0037         if (drm_crtc_vblank_get(crtc) == 0)
0038             drm_crtc_arm_vblank_event(crtc, event);
0039         else
0040             drm_crtc_send_vblank_event(crtc, event);
0041         spin_unlock_irq(&crtc->dev->event_lock);
0042     }
0043 }
0044
0045 static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc,
0046                     struct drm_atomic_state *state)
0047 {
0048     struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
0049                                           crtc);
0050     struct drm_device *dev = crtc->dev;
0051     struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
0052
0053     /* always disable planes on the CRTC */
0054     drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true);
0055
0056     drm_crtc_vblank_off(crtc);
0057
0058     regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
0059                DCU_MODE_DCU_MODE_MASK,
0060                DCU_MODE_DCU_MODE(DCU_MODE_OFF));
0061     regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
0062              DCU_UPDATE_MODE_READREG);
0063     clk_disable_unprepare(fsl_dev->pix_clk);
0064 }
0065
0066 static void fsl_dcu_drm_crtc_atomic_enable(struct drm_crtc *crtc,
0067                        struct drm_atomic_state *state)
0068 {
0069     struct drm_device *dev = crtc->dev;
0070     struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
0071
0072     clk_prepare_enable(fsl_dev->pix_clk);
0073     regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
0074                DCU_MODE_DCU_MODE_MASK,
0075                DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
0076     regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
0077              DCU_UPDATE_MODE_READREG);
0078
0079     drm_crtc_vblank_on(crtc);
0080 }
0081
0082 static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
0083 {
0084     struct drm_device *dev = crtc->dev;
0085     struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
0086     struct drm_connector *con = &fsl_dev->connector.base;
0087     struct drm_display_mode *mode = &crtc->state->mode;
0088     unsigned int pol = 0;
0089     struct videomode vm;
0090
0091     clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
0092
0093     drm_display_mode_to_videomode(mode, &vm);
0094
0095     /* INV_PXCK as default (most display sample data on rising edge) */
0096     if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE))
0097         pol |= DCU_SYN_POL_INV_PXCK;
0098
0099     if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
0100         pol |= DCU_SYN_POL_INV_HS_LOW;
0101
0102     if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
0103         pol |= DCU_SYN_POL_INV_VS_LOW;
0104
0105     regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
0106              DCU_HSYN_PARA_BP(vm.hback_porch) |
0107              DCU_HSYN_PARA_PW(vm.hsync_len) |
0108              DCU_HSYN_PARA_FP(vm.hfront_porch));
0109     regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
0110              DCU_VSYN_PARA_BP(vm.vback_porch) |
0111              DCU_VSYN_PARA_PW(vm.vsync_len) |
0112              DCU_VSYN_PARA_FP(vm.vfront_porch));
0113     regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
0114              DCU_DISP_SIZE_DELTA_Y(vm.vactive) |
0115              DCU_DISP_SIZE_DELTA_X(vm.hactive));
0116     regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
0117     regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
0118              DCU_BGND_G(0) | DCU_BGND_B(0));
0119     regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
0120              DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
0121     regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
0122              DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
0123              DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
0124              DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
0125     return;
0126 }
0127
0128 static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
0129     .atomic_disable = fsl_dcu_drm_crtc_atomic_disable,
0130     .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
0131     .atomic_enable = fsl_dcu_drm_crtc_atomic_enable,
0132     .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
0133 };
0134
0135 static int fsl_dcu_drm_crtc_enable_vblank(struct drm_crtc *crtc)
0136 {
0137     struct drm_device *dev = crtc->dev;
0138     struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
0139     unsigned int value;
0140
0141     regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
0142     value &= ~DCU_INT_MASK_VBLANK;
0143     regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
0144
0145     return 0;
0146 }
0147
0148 static void fsl_dcu_drm_crtc_disable_vblank(struct drm_crtc *crtc)
0149 {
0150     struct drm_device *dev = crtc->dev;
0151     struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
0152     unsigned int value;
0153
0154     regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
0155     value |= DCU_INT_MASK_VBLANK;
0156     regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
0157 }
0158
0159 static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
0160     .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
0161     .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
0162     .destroy = drm_crtc_cleanup,
0163     .page_flip = drm_atomic_helper_page_flip,
0164     .reset = drm_atomic_helper_crtc_reset,
0165     .set_config = drm_atomic_helper_set_config,
0166     .enable_vblank = fsl_dcu_drm_crtc_enable_vblank,
0167     .disable_vblank = fsl_dcu_drm_crtc_disable_vblank,
0168 };
0169
0170 int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
0171 {
0172     struct drm_plane *primary;
0173     struct drm_crtc *crtc = &fsl_dev->crtc;
0174     int ret;
0175
0176     fsl_dcu_drm_init_planes(fsl_dev->drm);
0177
0178     primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
0179     if (!primary)
0180         return -ENOMEM;
0181
0182     ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
0183                     &fsl_dcu_drm_crtc_funcs, NULL);
0184     if (ret) {
0185         primary->funcs->destroy(primary);
0186         return ret;
0187     }
0188
0189     drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
0190
0191     return 0;
0192 }