drm/exynos/regs-mixer.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  *  Cloned from drivers/media/video/s5p-tv/regs-mixer.h
0005  *
0006  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
0007  * http://www.samsung.com/
0008  *
0009  * Mixer register header file for Samsung Mixer driver
0010 */
0011 #ifndef SAMSUNG_REGS_MIXER_H
0012 #define SAMSUNG_REGS_MIXER_H
0013
0014 /*
0015  * Register part
0016  */
0017 #define MXR_STATUS          0x0000
0018 #define MXR_CFG             0x0004
0019 #define MXR_INT_EN          0x0008
0020 #define MXR_INT_STATUS          0x000C
0021 #define MXR_LAYER_CFG           0x0010
0022 #define MXR_VIDEO_CFG           0x0014
0023 #define MXR_GRAPHIC0_CFG        0x0020
0024 #define MXR_GRAPHIC0_BASE       0x0024
0025 #define MXR_GRAPHIC0_SPAN       0x0028
0026 #define MXR_GRAPHIC0_SXY        0x002C
0027 #define MXR_GRAPHIC0_WH         0x0030
0028 #define MXR_GRAPHIC0_DXY        0x0034
0029 #define MXR_GRAPHIC0_BLANK      0x0038
0030 #define MXR_GRAPHIC1_CFG        0x0040
0031 #define MXR_GRAPHIC1_BASE       0x0044
0032 #define MXR_GRAPHIC1_SPAN       0x0048
0033 #define MXR_GRAPHIC1_SXY        0x004C
0034 #define MXR_GRAPHIC1_WH         0x0050
0035 #define MXR_GRAPHIC1_DXY        0x0054
0036 #define MXR_GRAPHIC1_BLANK      0x0058
0037 #define MXR_BG_CFG          0x0060
0038 #define MXR_BG_COLOR0           0x0064
0039 #define MXR_BG_COLOR1           0x0068
0040 #define MXR_BG_COLOR2           0x006C
0041 #define MXR_CM_COEFF_Y          0x0080
0042 #define MXR_CM_COEFF_CB         0x0084
0043 #define MXR_CM_COEFF_CR         0x0088
0044 #define MXR_MO              0x0304
0045 #define MXR_RESOLUTION          0x0310
0046
0047 #define MXR_CFG_S           0x2004
0048 #define MXR_GRAPHIC0_BASE_S     0x2024
0049 #define MXR_GRAPHIC1_BASE_S     0x2044
0050
0051 /* for parametrized access to layer registers */
0052 #define MXR_GRAPHIC_CFG(i)      (0x0020 + (i) * 0x20)
0053 #define MXR_GRAPHIC_BASE(i)     (0x0024 + (i) * 0x20)
0054 #define MXR_GRAPHIC_SPAN(i)     (0x0028 + (i) * 0x20)
0055 #define MXR_GRAPHIC_SXY(i)      (0x002C + (i) * 0x20)
0056 #define MXR_GRAPHIC_WH(i)       (0x0030 + (i) * 0x20)
0057 #define MXR_GRAPHIC_DXY(i)      (0x0034 + (i) * 0x20)
0058 #define MXR_GRAPHIC_BLANK(i)        (0x0038 + (i) * 0x20)
0059 #define MXR_GRAPHIC_BASE_S(i)       (0x2024 + (i) * 0x20)
0060
0061 /*
0062  * Bit definition part
0063  */
0064
0065 /* generates mask for range of bits */
0066 #define MXR_MASK(high_bit, low_bit) \
0067     (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
0068
0069 #define MXR_MASK_VAL(val, high_bit, low_bit) \
0070     (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
0071
0072 /* bits for MXR_STATUS */
0073 #define MXR_STATUS_SOFT_RESET       (1 << 8)
0074 #define MXR_STATUS_16_BURST     (1 << 7)
0075 #define MXR_STATUS_BURST_MASK       (1 << 7)
0076 #define MXR_STATUS_BIG_ENDIAN       (1 << 3)
0077 #define MXR_STATUS_ENDIAN_MASK      (1 << 3)
0078 #define MXR_STATUS_SYNC_ENABLE      (1 << 2)
0079 #define MXR_STATUS_REG_IDLE     (1 << 1)
0080 #define MXR_STATUS_REG_RUN      (1 << 0)
0081
0082 /* bits for MXR_CFG */
0083 #define MXR_CFG_LAYER_UPDATE        (1 << 31)
0084 #define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29)
0085 #define MXR_CFG_QUANT_RANGE_FULL    (0 << 9)
0086 #define MXR_CFG_QUANT_RANGE_LIMITED (1 << 9)
0087 #define MXR_CFG_RGB601          (0 << 10)
0088 #define MXR_CFG_RGB709          (1 << 10)
0089
0090 #define MXR_CFG_RGB_FMT_MASK        0x600
0091 #define MXR_CFG_OUT_YUV444      (0 << 8)
0092 #define MXR_CFG_OUT_RGB888      (1 << 8)
0093 #define MXR_CFG_OUT_MASK        (1 << 8)
0094 #define MXR_CFG_DST_SDO         (0 << 7)
0095 #define MXR_CFG_DST_HDMI        (1 << 7)
0096 #define MXR_CFG_DST_MASK        (1 << 7)
0097 #define MXR_CFG_SCAN_HD_720     (0 << 6)
0098 #define MXR_CFG_SCAN_HD_1080        (1 << 6)
0099 #define MXR_CFG_GRP1_ENABLE     (1 << 5)
0100 #define MXR_CFG_GRP0_ENABLE     (1 << 4)
0101 #define MXR_CFG_VP_ENABLE       (1 << 3)
0102 #define MXR_CFG_SCAN_INTERLACE      (0 << 2)
0103 #define MXR_CFG_SCAN_PROGRESSIVE    (1 << 2)
0104 #define MXR_CFG_SCAN_NTSC       (0 << 1)
0105 #define MXR_CFG_SCAN_PAL        (1 << 1)
0106 #define MXR_CFG_SCAN_SD         (0 << 0)
0107 #define MXR_CFG_SCAN_HD         (1 << 0)
0108 #define MXR_CFG_SCAN_MASK       0x47
0109
0110 /* bits for MXR_VIDEO_CFG */
0111 #define MXR_VID_CFG_BLEND_EN        (1 << 16)
0112
0113 /* bits for MXR_GRAPHICn_CFG */
0114 #define MXR_GRP_CFG_COLOR_KEY_DISABLE   (1 << 21)
0115 #define MXR_GRP_CFG_BLEND_PRE_MUL   (1 << 20)
0116 #define MXR_GRP_CFG_WIN_BLEND_EN    (1 << 17)
0117 #define MXR_GRP_CFG_PIXEL_BLEND_EN  (1 << 16)
0118 #define MXR_GRP_CFG_MISC_MASK       ((3 << 16) | (3 << 20) | 0xff)
0119 #define MXR_GRP_CFG_FORMAT_VAL(x)   MXR_MASK_VAL(x, 11, 8)
0120 #define MXR_GRP_CFG_FORMAT_MASK     MXR_GRP_CFG_FORMAT_VAL(~0)
0121 #define MXR_GRP_CFG_ALPHA_VAL(x)    MXR_MASK_VAL(x, 7, 0)
0122
0123 /* bits for MXR_GRAPHICn_WH */
0124 #define MXR_GRP_WH_H_SCALE(x)       MXR_MASK_VAL(x, 28, 28)
0125 #define MXR_GRP_WH_V_SCALE(x)       MXR_MASK_VAL(x, 12, 12)
0126 #define MXR_GRP_WH_WIDTH(x)     MXR_MASK_VAL(x, 26, 16)
0127 #define MXR_GRP_WH_HEIGHT(x)        MXR_MASK_VAL(x, 10, 0)
0128
0129 /* bits for MXR_RESOLUTION */
0130 #define MXR_MXR_RES_HEIGHT(x)       MXR_MASK_VAL(x, 26, 16)
0131 #define MXR_MXR_RES_WIDTH(x)        MXR_MASK_VAL(x, 10, 0)
0132
0133 /* bits for MXR_GRAPHICn_SXY */
0134 #define MXR_GRP_SXY_SX(x)       MXR_MASK_VAL(x, 26, 16)
0135 #define MXR_GRP_SXY_SY(x)       MXR_MASK_VAL(x, 10, 0)
0136
0137 /* bits for MXR_GRAPHICn_DXY */
0138 #define MXR_GRP_DXY_DX(x)       MXR_MASK_VAL(x, 26, 16)
0139 #define MXR_GRP_DXY_DY(x)       MXR_MASK_VAL(x, 10, 0)
0140
0141 /* bits for MXR_INT_EN */
0142 #define MXR_INT_EN_VSYNC        (1 << 11)
0143 #define MXR_INT_EN_ALL          (0x0f << 8)
0144
0145 /* bits for MXR_INT_STATUS */
0146 #define MXR_INT_CLEAR_VSYNC     (1 << 11)
0147 #define MXR_INT_STATUS_VSYNC        (1 << 0)
0148
0149 /* bits for MXR_LAYER_CFG */
0150 #define MXR_LAYER_CFG_GRP1_VAL(x)   MXR_MASK_VAL(x, 11, 8)
0151 #define MXR_LAYER_CFG_GRP1_MASK     MXR_LAYER_CFG_GRP1_VAL(~0)
0152 #define MXR_LAYER_CFG_GRP0_VAL(x)   MXR_MASK_VAL(x, 7, 4)
0153 #define MXR_LAYER_CFG_GRP0_MASK     MXR_LAYER_CFG_GRP0_VAL(~0)
0154 #define MXR_LAYER_CFG_VP_VAL(x)     MXR_MASK_VAL(x, 3, 0)
0155 #define MXR_LAYER_CFG_VP_MASK       MXR_LAYER_CFG_VP_VAL(~0)
0156
0157 /* bits for MXR_CM_COEFF_Y */
0158 #define MXR_CM_COEFF_RGB_FULL       (1 << 30)
0159
0160 #endif /* SAMSUNG_REGS_MIXER_H */
0161