drm/exynos/regs-fimc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* drivers/gpu/drm/exynos/regs-fimc.h
0003  *
0004  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
0005  *      http://www.samsung.com/
0006  *
0007  * Register definition file for Samsung Camera Interface (FIMC) driver
0008 */
0009
0010 #ifndef EXYNOS_REGS_FIMC_H
0011 #define EXYNOS_REGS_FIMC_H
0012
0013 /*
0014  * Register part
0015 */
0016 /* Input source format */
0017 #define EXYNOS_CISRCFMT     (0x00)
0018 /* Window offset */
0019 #define EXYNOS_CIWDOFST     (0x04)
0020 /* Global control */
0021 #define EXYNOS_CIGCTRL      (0x08)
0022 /* Window offset 2 */
0023 #define EXYNOS_CIWDOFST2    (0x14)
0024 /* Y 1st frame start address for output DMA */
0025 #define EXYNOS_CIOYSA1      (0x18)
0026 /* Y 2nd frame start address for output DMA */
0027 #define EXYNOS_CIOYSA2      (0x1c)
0028 /* Y 3rd frame start address for output DMA */
0029 #define EXYNOS_CIOYSA3      (0x20)
0030 /* Y 4th frame start address for output DMA */
0031 #define EXYNOS_CIOYSA4      (0x24)
0032 /* Cb 1st frame start address for output DMA */
0033 #define EXYNOS_CIOCBSA1     (0x28)
0034 /* Cb 2nd frame start address for output DMA */
0035 #define EXYNOS_CIOCBSA2     (0x2c)
0036 /* Cb 3rd frame start address for output DMA */
0037 #define EXYNOS_CIOCBSA3     (0x30)
0038 /* Cb 4th frame start address for output DMA */
0039 #define EXYNOS_CIOCBSA4     (0x34)
0040 /* Cr 1st frame start address for output DMA */
0041 #define EXYNOS_CIOCRSA1     (0x38)
0042 /* Cr 2nd frame start address for output DMA */
0043 #define EXYNOS_CIOCRSA2     (0x3c)
0044 /* Cr 3rd frame start address for output DMA */
0045 #define EXYNOS_CIOCRSA3     (0x40)
0046 /* Cr 4th frame start address for output DMA */
0047 #define EXYNOS_CIOCRSA4     (0x44)
0048 /* Target image format */
0049 #define EXYNOS_CITRGFMT     (0x48)
0050 /* Output DMA control */
0051 #define EXYNOS_CIOCTRL      (0x4c)
0052 /* Pre-scaler control 1 */
0053 #define EXYNOS_CISCPRERATIO (0x50)
0054 /* Pre-scaler control 2 */
0055 #define EXYNOS_CISCPREDST       (0x54)
0056 /* Main scaler control */
0057 #define EXYNOS_CISCCTRL     (0x58)
0058 /* Target area */
0059 #define EXYNOS_CITAREA      (0x5c)
0060 /* Status */
0061 #define EXYNOS_CISTATUS     (0x64)
0062 /* Status2 */
0063 #define EXYNOS_CISTATUS2        (0x68)
0064 /* Image capture enable command */
0065 #define EXYNOS_CIIMGCPT     (0xc0)
0066 /* Capture sequence */
0067 #define EXYNOS_CICPTSEQ     (0xc4)
0068 /* Image effects */
0069 #define EXYNOS_CIIMGEFF     (0xd0)
0070 /* Y frame start address for input DMA */
0071 #define EXYNOS_CIIYSA0      (0xd4)
0072 /* Cb frame start address for input DMA */
0073 #define EXYNOS_CIICBSA0     (0xd8)
0074 /* Cr frame start address for input DMA */
0075 #define EXYNOS_CIICRSA0     (0xdc)
0076 /* Input DMA Y Line Skip */
0077 #define EXYNOS_CIILINESKIP_Y    (0xec)
0078 /* Input DMA Cb Line Skip */
0079 #define EXYNOS_CIILINESKIP_CB   (0xf0)
0080 /* Input DMA Cr Line Skip */
0081 #define EXYNOS_CIILINESKIP_CR   (0xf4)
0082 /* Real input DMA image size */
0083 #define EXYNOS_CIREAL_ISIZE (0xf8)
0084 /* Input DMA control */
0085 #define EXYNOS_MSCTRL       (0xfc)
0086 /* Y frame start address for input DMA */
0087 #define EXYNOS_CIIYSA1      (0x144)
0088 /* Cb frame start address for input DMA */
0089 #define EXYNOS_CIICBSA1     (0x148)
0090 /* Cr frame start address for input DMA */
0091 #define EXYNOS_CIICRSA1     (0x14c)
0092 /* Output DMA Y offset */
0093 #define EXYNOS_CIOYOFF      (0x168)
0094 /* Output DMA CB offset */
0095 #define EXYNOS_CIOCBOFF     (0x16c)
0096 /* Output DMA CR offset */
0097 #define EXYNOS_CIOCROFF     (0x170)
0098 /* Input DMA Y offset */
0099 #define EXYNOS_CIIYOFF      (0x174)
0100 /* Input DMA CB offset */
0101 #define EXYNOS_CIICBOFF     (0x178)
0102 /* Input DMA CR offset */
0103 #define EXYNOS_CIICROFF     (0x17c)
0104 /* Input DMA original image size */
0105 #define EXYNOS_ORGISIZE     (0x180)
0106 /* Output DMA original image size */
0107 #define EXYNOS_ORGOSIZE     (0x184)
0108 /* Real output DMA image size */
0109 #define EXYNOS_CIEXTEN      (0x188)
0110 /* DMA parameter */
0111 #define EXYNOS_CIDMAPARAM       (0x18c)
0112 /* MIPI CSI image format */
0113 #define EXYNOS_CSIIMGFMT        (0x194)
0114 /* FIMC Clock Source Select */
0115 #define EXYNOS_MISC_FIMC        (0x198)
0116
0117 /* Add for FIMC v5.1 */
0118 /* Output Frame Buffer Sequence */
0119 #define EXYNOS_CIFCNTSEQ        (0x1fc)
0120 /* Y 5th frame start address for output DMA */
0121 #define EXYNOS_CIOYSA5      (0x200)
0122 /* Y 6th frame start address for output DMA */
0123 #define EXYNOS_CIOYSA6      (0x204)
0124 /* Y 7th frame start address for output DMA */
0125 #define EXYNOS_CIOYSA7      (0x208)
0126 /* Y 8th frame start address for output DMA */
0127 #define EXYNOS_CIOYSA8      (0x20c)
0128 /* Y 9th frame start address for output DMA */
0129 #define EXYNOS_CIOYSA9      (0x210)
0130 /* Y 10th frame start address for output DMA */
0131 #define EXYNOS_CIOYSA10     (0x214)
0132 /* Y 11th frame start address for output DMA */
0133 #define EXYNOS_CIOYSA11     (0x218)
0134 /* Y 12th frame start address for output DMA */
0135 #define EXYNOS_CIOYSA12     (0x21c)
0136 /* Y 13th frame start address for output DMA */
0137 #define EXYNOS_CIOYSA13     (0x220)
0138 /* Y 14th frame start address for output DMA */
0139 #define EXYNOS_CIOYSA14     (0x224)
0140 /* Y 15th frame start address for output DMA */
0141 #define EXYNOS_CIOYSA15     (0x228)
0142 /* Y 16th frame start address for output DMA */
0143 #define EXYNOS_CIOYSA16     (0x22c)
0144 /* Y 17th frame start address for output DMA */
0145 #define EXYNOS_CIOYSA17     (0x230)
0146 /* Y 18th frame start address for output DMA */
0147 #define EXYNOS_CIOYSA18     (0x234)
0148 /* Y 19th frame start address for output DMA */
0149 #define EXYNOS_CIOYSA19     (0x238)
0150 /* Y 20th frame start address for output DMA */
0151 #define EXYNOS_CIOYSA20     (0x23c)
0152 /* Y 21th frame start address for output DMA */
0153 #define EXYNOS_CIOYSA21     (0x240)
0154 /* Y 22th frame start address for output DMA */
0155 #define EXYNOS_CIOYSA22     (0x244)
0156 /* Y 23th frame start address for output DMA */
0157 #define EXYNOS_CIOYSA23     (0x248)
0158 /* Y 24th frame start address for output DMA */
0159 #define EXYNOS_CIOYSA24     (0x24c)
0160 /* Y 25th frame start address for output DMA */
0161 #define EXYNOS_CIOYSA25     (0x250)
0162 /* Y 26th frame start address for output DMA */
0163 #define EXYNOS_CIOYSA26     (0x254)
0164 /* Y 27th frame start address for output DMA */
0165 #define EXYNOS_CIOYSA27     (0x258)
0166 /* Y 28th frame start address for output DMA */
0167 #define EXYNOS_CIOYSA28     (0x25c)
0168 /* Y 29th frame start address for output DMA */
0169 #define EXYNOS_CIOYSA29     (0x260)
0170 /* Y 30th frame start address for output DMA */
0171 #define EXYNOS_CIOYSA30     (0x264)
0172 /* Y 31th frame start address for output DMA */
0173 #define EXYNOS_CIOYSA31     (0x268)
0174 /* Y 32th frame start address for output DMA */
0175 #define EXYNOS_CIOYSA32     (0x26c)
0176
0177 /* CB 5th frame start address for output DMA */
0178 #define EXYNOS_CIOCBSA5     (0x270)
0179 /* CB 6th frame start address for output DMA */
0180 #define EXYNOS_CIOCBSA6     (0x274)
0181 /* CB 7th frame start address for output DMA */
0182 #define EXYNOS_CIOCBSA7     (0x278)
0183 /* CB 8th frame start address for output DMA */
0184 #define EXYNOS_CIOCBSA8     (0x27c)
0185 /* CB 9th frame start address for output DMA */
0186 #define EXYNOS_CIOCBSA9     (0x280)
0187 /* CB 10th frame start address for output DMA */
0188 #define EXYNOS_CIOCBSA10        (0x284)
0189 /* CB 11th frame start address for output DMA */
0190 #define EXYNOS_CIOCBSA11        (0x288)
0191 /* CB 12th frame start address for output DMA */
0192 #define EXYNOS_CIOCBSA12        (0x28c)
0193 /* CB 13th frame start address for output DMA */
0194 #define EXYNOS_CIOCBSA13        (0x290)
0195 /* CB 14th frame start address for output DMA */
0196 #define EXYNOS_CIOCBSA14        (0x294)
0197 /* CB 15th frame start address for output DMA */
0198 #define EXYNOS_CIOCBSA15        (0x298)
0199 /* CB 16th frame start address for output DMA */
0200 #define EXYNOS_CIOCBSA16        (0x29c)
0201 /* CB 17th frame start address for output DMA */
0202 #define EXYNOS_CIOCBSA17        (0x2a0)
0203 /* CB 18th frame start address for output DMA */
0204 #define EXYNOS_CIOCBSA18        (0x2a4)
0205 /* CB 19th frame start address for output DMA */
0206 #define EXYNOS_CIOCBSA19        (0x2a8)
0207 /* CB 20th frame start address for output DMA */
0208 #define EXYNOS_CIOCBSA20        (0x2ac)
0209 /* CB 21th frame start address for output DMA */
0210 #define EXYNOS_CIOCBSA21        (0x2b0)
0211 /* CB 22th frame start address for output DMA */
0212 #define EXYNOS_CIOCBSA22        (0x2b4)
0213 /* CB 23th frame start address for output DMA */
0214 #define EXYNOS_CIOCBSA23        (0x2b8)
0215 /* CB 24th frame start address for output DMA */
0216 #define EXYNOS_CIOCBSA24        (0x2bc)
0217 /* CB 25th frame start address for output DMA */
0218 #define EXYNOS_CIOCBSA25        (0x2c0)
0219 /* CB 26th frame start address for output DMA */
0220 #define EXYNOS_CIOCBSA26        (0x2c4)
0221 /* CB 27th frame start address for output DMA */
0222 #define EXYNOS_CIOCBSA27        (0x2c8)
0223 /* CB 28th frame start address for output DMA */
0224 #define EXYNOS_CIOCBSA28        (0x2cc)
0225 /* CB 29th frame start address for output DMA */
0226 #define EXYNOS_CIOCBSA29        (0x2d0)
0227 /* CB 30th frame start address for output DMA */
0228 #define EXYNOS_CIOCBSA30        (0x2d4)
0229 /* CB 31th frame start address for output DMA */
0230 #define EXYNOS_CIOCBSA31        (0x2d8)
0231 /* CB 32th frame start address for output DMA */
0232 #define EXYNOS_CIOCBSA32        (0x2dc)
0233
0234 /* CR 5th frame start address for output DMA */
0235 #define EXYNOS_CIOCRSA5     (0x2e0)
0236 /* CR 6th frame start address for output DMA */
0237 #define EXYNOS_CIOCRSA6     (0x2e4)
0238 /* CR 7th frame start address for output DMA */
0239 #define EXYNOS_CIOCRSA7     (0x2e8)
0240 /* CR 8th frame start address for output DMA */
0241 #define EXYNOS_CIOCRSA8     (0x2ec)
0242 /* CR 9th frame start address for output DMA */
0243 #define EXYNOS_CIOCRSA9     (0x2f0)
0244 /* CR 10th frame start address for output DMA */
0245 #define EXYNOS_CIOCRSA10        (0x2f4)
0246 /* CR 11th frame start address for output DMA */
0247 #define EXYNOS_CIOCRSA11        (0x2f8)
0248 /* CR 12th frame start address for output DMA */
0249 #define EXYNOS_CIOCRSA12        (0x2fc)
0250 /* CR 13th frame start address for output DMA */
0251 #define EXYNOS_CIOCRSA13        (0x300)
0252 /* CR 14th frame start address for output DMA */
0253 #define EXYNOS_CIOCRSA14        (0x304)
0254 /* CR 15th frame start address for output DMA */
0255 #define EXYNOS_CIOCRSA15        (0x308)
0256 /* CR 16th frame start address for output DMA */
0257 #define EXYNOS_CIOCRSA16        (0x30c)
0258 /* CR 17th frame start address for output DMA */
0259 #define EXYNOS_CIOCRSA17        (0x310)
0260 /* CR 18th frame start address for output DMA */
0261 #define EXYNOS_CIOCRSA18        (0x314)
0262 /* CR 19th frame start address for output DMA */
0263 #define EXYNOS_CIOCRSA19        (0x318)
0264 /* CR 20th frame start address for output DMA */
0265 #define EXYNOS_CIOCRSA20        (0x31c)
0266 /* CR 21th frame start address for output DMA */
0267 #define EXYNOS_CIOCRSA21        (0x320)
0268 /* CR 22th frame start address for output DMA */
0269 #define EXYNOS_CIOCRSA22        (0x324)
0270 /* CR 23th frame start address for output DMA */
0271 #define EXYNOS_CIOCRSA23        (0x328)
0272 /* CR 24th frame start address for output DMA */
0273 #define EXYNOS_CIOCRSA24        (0x32c)
0274 /* CR 25th frame start address for output DMA */
0275 #define EXYNOS_CIOCRSA25        (0x330)
0276 /* CR 26th frame start address for output DMA */
0277 #define EXYNOS_CIOCRSA26        (0x334)
0278 /* CR 27th frame start address for output DMA */
0279 #define EXYNOS_CIOCRSA27        (0x338)
0280 /* CR 28th frame start address for output DMA */
0281 #define EXYNOS_CIOCRSA28        (0x33c)
0282 /* CR 29th frame start address for output DMA */
0283 #define EXYNOS_CIOCRSA29        (0x340)
0284 /* CR 30th frame start address for output DMA */
0285 #define EXYNOS_CIOCRSA30        (0x344)
0286 /* CR 31th frame start address for output DMA */
0287 #define EXYNOS_CIOCRSA31        (0x348)
0288 /* CR 32th frame start address for output DMA */
0289 #define EXYNOS_CIOCRSA32        (0x34c)
0290
0291 /*
0292  * Macro part
0293 */
0294 /* frame start address 1 ~ 4, 5 ~ 32 */
0295 /* Number of Default PingPong Memory */
0296 #define DEF_PP      4
0297 #define EXYNOS_CIOYSA(__x)      \
0298     (((__x) < DEF_PP) ? \
0299      (EXYNOS_CIOYSA1  + (__x) * 4) : \
0300     (EXYNOS_CIOYSA5  + ((__x) - DEF_PP) * 4))
0301 #define EXYNOS_CIOCBSA(__x) \
0302     (((__x) < DEF_PP) ? \
0303      (EXYNOS_CIOCBSA1 + (__x) * 4) : \
0304     (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4))
0305 #define EXYNOS_CIOCRSA(__x) \
0306     (((__x) < DEF_PP) ? \
0307      (EXYNOS_CIOCRSA1 + (__x) * 4) : \
0308     (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4))
0309 /* Number of Default PingPong Memory */
0310 #define DEF_IPP     1
0311 #define EXYNOS_CIIYSA(__x)      \
0312     (((__x) < DEF_IPP) ?    \
0313      (EXYNOS_CIIYSA0) : (EXYNOS_CIIYSA1))
0314 #define EXYNOS_CIICBSA(__x) \
0315     (((__x) < DEF_IPP) ?    \
0316      (EXYNOS_CIICBSA0) : (EXYNOS_CIICBSA1))
0317 #define EXYNOS_CIICRSA(__x) \
0318     (((__x) < DEF_IPP) ?    \
0319      (EXYNOS_CIICRSA0) : (EXYNOS_CIICRSA1))
0320
0321 #define EXYNOS_CISRCFMT_SOURCEHSIZE(x)      ((x) << 16)
0322 #define EXYNOS_CISRCFMT_SOURCEVSIZE(x)      ((x) << 0)
0323
0324 #define EXYNOS_CIWDOFST_WINHOROFST(x)       ((x) << 16)
0325 #define EXYNOS_CIWDOFST_WINVEROFST(x)       ((x) << 0)
0326
0327 #define EXYNOS_CIWDOFST2_WINHOROFST2(x)     ((x) << 16)
0328 #define EXYNOS_CIWDOFST2_WINVEROFST2(x)     ((x) << 0)
0329
0330 #define EXYNOS_CITRGFMT_TARGETHSIZE(x)      (((x) & 0x1fff) << 16)
0331 #define EXYNOS_CITRGFMT_TARGETVSIZE(x)      (((x) & 0x1fff) << 0)
0332
0333 #define EXYNOS_CISCPRERATIO_SHFACTOR(x)     ((x) << 28)
0334 #define EXYNOS_CISCPRERATIO_PREHORRATIO(x)      ((x) << 16)
0335 #define EXYNOS_CISCPRERATIO_PREVERRATIO(x)      ((x) << 0)
0336
0337 #define EXYNOS_CISCPREDST_PREDSTWIDTH(x)        ((x) << 16)
0338 #define EXYNOS_CISCPREDST_PREDSTHEIGHT(x)       ((x) << 0)
0339
0340 #define EXYNOS_CISCCTRL_MAINHORRATIO(x)     ((x) << 16)
0341 #define EXYNOS_CISCCTRL_MAINVERRATIO(x)     ((x) << 0)
0342
0343 #define EXYNOS_CITAREA_TARGET_AREA(x)       ((x) << 0)
0344
0345 #define EXYNOS_CISTATUS_GET_FRAME_COUNT(x)      (((x) >> 26) & 0x3)
0346 #define EXYNOS_CISTATUS_GET_FRAME_END(x)        (((x) >> 17) & 0x1)
0347 #define EXYNOS_CISTATUS_GET_LAST_CAPTURE_END(x) (((x) >> 16) & 0x1)
0348 #define EXYNOS_CISTATUS_GET_LCD_STATUS(x)       (((x) >> 9) & 0x1)
0349 #define EXYNOS_CISTATUS_GET_ENVID_STATUS(x) (((x) >> 8) & 0x1)
0350
0351 #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(x)   (((x) >> 7) & 0x3f)
0352 #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(x)  ((x) & 0x3f)
0353
0354 #define EXYNOS_CIIMGEFF_FIN(x)          ((x & 0x7) << 26)
0355 #define EXYNOS_CIIMGEFF_PAT_CB(x)           ((x) << 13)
0356 #define EXYNOS_CIIMGEFF_PAT_CR(x)           ((x) << 0)
0357
0358 #define EXYNOS_CIILINESKIP(x)           (((x) & 0xf) << 24)
0359
0360 #define EXYNOS_CIREAL_ISIZE_HEIGHT(x)       ((x) << 16)
0361 #define EXYNOS_CIREAL_ISIZE_WIDTH(x)        ((x) << 0)
0362
0363 #define EXYNOS_MSCTRL_SUCCESSIVE_COUNT(x)       ((x) << 24)
0364 #define EXYNOS_MSCTRL_GET_INDMA_STATUS(x)       ((x) & 0x1)
0365
0366 #define EXYNOS_CIOYOFF_VERTICAL(x)          ((x) << 16)
0367 #define EXYNOS_CIOYOFF_HORIZONTAL(x)        ((x) << 0)
0368
0369 #define EXYNOS_CIOCBOFF_VERTICAL(x)     ((x) << 16)
0370 #define EXYNOS_CIOCBOFF_HORIZONTAL(x)       ((x) << 0)
0371
0372 #define EXYNOS_CIOCROFF_VERTICAL(x)     ((x) << 16)
0373 #define EXYNOS_CIOCROFF_HORIZONTAL(x)       ((x) << 0)
0374
0375 #define EXYNOS_CIIYOFF_VERTICAL(x)          ((x) << 16)
0376 #define EXYNOS_CIIYOFF_HORIZONTAL(x)        ((x) << 0)
0377
0378 #define EXYNOS_CIICBOFF_VERTICAL(x)     ((x) << 16)
0379 #define EXYNOS_CIICBOFF_HORIZONTAL(x)       ((x) << 0)
0380
0381 #define EXYNOS_CIICROFF_VERTICAL(x)     ((x) << 16)
0382 #define EXYNOS_CIICROFF_HORIZONTAL(x)       ((x) << 0)
0383
0384 #define EXYNOS_ORGISIZE_VERTICAL(x)     ((x) << 16)
0385 #define EXYNOS_ORGISIZE_HORIZONTAL(x)       ((x) << 0)
0386
0387 #define EXYNOS_ORGOSIZE_VERTICAL(x)     ((x) << 16)
0388 #define EXYNOS_ORGOSIZE_HORIZONTAL(x)       ((x) << 0)
0389
0390 #define EXYNOS_CIEXTEN_TARGETH_EXT(x)       ((((x) & 0x2000) >> 13) << 26)
0391 #define EXYNOS_CIEXTEN_TARGETV_EXT(x)       ((((x) & 0x2000) >> 13) << 24)
0392 #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT(x)      (((x) & 0x3F) << 10)
0393 #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT(x)      ((x) & 0x3F)
0394
0395 /*
0396  * Bit definition part
0397 */
0398 /* Source format register */
0399 #define EXYNOS_CISRCFMT_ITU601_8BIT     (1 << 31)
0400 #define EXYNOS_CISRCFMT_ITU656_8BIT     (0 << 31)
0401 #define EXYNOS_CISRCFMT_ITU601_16BIT        (1 << 29)
0402 #define EXYNOS_CISRCFMT_ORDER422_YCBYCR     (0 << 14)
0403 #define EXYNOS_CISRCFMT_ORDER422_YCRYCB     (1 << 14)
0404 #define EXYNOS_CISRCFMT_ORDER422_CBYCRY     (2 << 14)
0405 #define EXYNOS_CISRCFMT_ORDER422_CRYCBY     (3 << 14)
0406 /* ITU601 16bit only */
0407 #define EXYNOS_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14)
0408 /* ITU601 16bit only */
0409 #define EXYNOS_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14)
0410
0411 /* Window offset register */
0412 #define EXYNOS_CIWDOFST_WINOFSEN            (1 << 31)
0413 #define EXYNOS_CIWDOFST_CLROVFIY            (1 << 30)
0414 #define EXYNOS_CIWDOFST_CLROVRLB            (1 << 29)
0415 #define EXYNOS_CIWDOFST_WINHOROFST_MASK     (0x7ff << 16)
0416 #define EXYNOS_CIWDOFST_CLROVFICB           (1 << 15)
0417 #define EXYNOS_CIWDOFST_CLROVFICR           (1 << 14)
0418 #define EXYNOS_CIWDOFST_WINVEROFST_MASK     (0xfff << 0)
0419
0420 /* Global control register */
0421 #define EXYNOS_CIGCTRL_SWRST            (1 << 31)
0422 #define EXYNOS_CIGCTRL_CAMRST_A         (1 << 30)
0423 #define EXYNOS_CIGCTRL_SELCAM_ITU_B     (0 << 29)
0424 #define EXYNOS_CIGCTRL_SELCAM_ITU_A     (1 << 29)
0425 #define EXYNOS_CIGCTRL_SELCAM_ITU_MASK      (1 << 29)
0426 #define EXYNOS_CIGCTRL_TESTPATTERN_NORMAL       (0 << 27)
0427 #define EXYNOS_CIGCTRL_TESTPATTERN_COLOR_BAR    (1 << 27)
0428 #define EXYNOS_CIGCTRL_TESTPATTERN_HOR_INC      (2 << 27)
0429 #define EXYNOS_CIGCTRL_TESTPATTERN_VER_INC      (3 << 27)
0430 #define EXYNOS_CIGCTRL_TESTPATTERN_MASK     (3 << 27)
0431 #define EXYNOS_CIGCTRL_TESTPATTERN_SHIFT        (27)
0432 #define EXYNOS_CIGCTRL_INVPOLPCLK           (1 << 26)
0433 #define EXYNOS_CIGCTRL_INVPOLVSYNC          (1 << 25)
0434 #define EXYNOS_CIGCTRL_INVPOLHREF           (1 << 24)
0435 #define EXYNOS_CIGCTRL_IRQ_OVFEN            (1 << 22)
0436 #define EXYNOS_CIGCTRL_HREF_MASK            (1 << 21)
0437 #define EXYNOS_CIGCTRL_IRQ_EDGE         (0 << 20)
0438 #define EXYNOS_CIGCTRL_IRQ_LEVEL            (1 << 20)
0439 #define EXYNOS_CIGCTRL_IRQ_CLR          (1 << 19)
0440 #define EXYNOS_CIGCTRL_IRQ_END_DISABLE      (1 << 18)
0441 #define EXYNOS_CIGCTRL_IRQ_DISABLE          (0 << 16)
0442 #define EXYNOS_CIGCTRL_IRQ_ENABLE           (1 << 16)
0443 #define EXYNOS_CIGCTRL_SHADOW_DISABLE       (1 << 12)
0444 #define EXYNOS_CIGCTRL_CAM_JPEG         (1 << 8)
0445 #define EXYNOS_CIGCTRL_SELCAM_MIPI_B        (0 << 7)
0446 #define EXYNOS_CIGCTRL_SELCAM_MIPI_A        (1 << 7)
0447 #define EXYNOS_CIGCTRL_SELCAM_MIPI_MASK     (1 << 7)
0448 #define EXYNOS_CIGCTRL_SELWB_CAMIF_CAMERA   (0 << 6)
0449 #define EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK    (1 << 6)
0450 #define EXYNOS_CIGCTRL_SELWRITEBACK_MASK        (1 << 10)
0451 #define EXYNOS_CIGCTRL_SELWRITEBACK_A       (1 << 10)
0452 #define EXYNOS_CIGCTRL_SELWRITEBACK_B       (0 << 10)
0453 #define EXYNOS_CIGCTRL_SELWB_CAMIF_MASK     (1 << 6)
0454 #define EXYNOS_CIGCTRL_CSC_ITU601           (0 << 5)
0455 #define EXYNOS_CIGCTRL_CSC_ITU709           (1 << 5)
0456 #define EXYNOS_CIGCTRL_CSC_MASK         (1 << 5)
0457 #define EXYNOS_CIGCTRL_INVPOLHSYNC          (1 << 4)
0458 #define EXYNOS_CIGCTRL_SELCAM_FIMC_ITU      (0 << 3)
0459 #define EXYNOS_CIGCTRL_SELCAM_FIMC_MIPI     (1 << 3)
0460 #define EXYNOS_CIGCTRL_SELCAM_FIMC_MASK     (1 << 3)
0461 #define EXYNOS_CIGCTRL_PROGRESSIVE          (0 << 0)
0462 #define EXYNOS_CIGCTRL_INTERLACE            (1 << 0)
0463
0464 /* Window offset2 register */
0465 #define EXYNOS_CIWDOFST_WINHOROFST2_MASK        (0xfff << 16)
0466 #define EXYNOS_CIWDOFST_WINVEROFST2_MASK        (0xfff << 16)
0467
0468 /* Target format register */
0469 #define EXYNOS_CITRGFMT_INROT90_CLOCKWISE       (1 << 31)
0470 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420      (0 << 29)
0471 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422      (1 << 29)
0472 #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE   (2 << 29)
0473 #define EXYNOS_CITRGFMT_OUTFORMAT_RGB       (3 << 29)
0474 #define EXYNOS_CITRGFMT_OUTFORMAT_MASK      (3 << 29)
0475 #define EXYNOS_CITRGFMT_FLIP_SHIFT          (14)
0476 #define EXYNOS_CITRGFMT_FLIP_NORMAL     (0 << 14)
0477 #define EXYNOS_CITRGFMT_FLIP_X_MIRROR       (1 << 14)
0478 #define EXYNOS_CITRGFMT_FLIP_Y_MIRROR       (2 << 14)
0479 #define EXYNOS_CITRGFMT_FLIP_180            (3 << 14)
0480 #define EXYNOS_CITRGFMT_FLIP_MASK           (3 << 14)
0481 #define EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE      (1 << 13)
0482 #define EXYNOS_CITRGFMT_TARGETV_MASK        (0x1fff << 0)
0483 #define EXYNOS_CITRGFMT_TARGETH_MASK        (0x1fff << 16)
0484
0485 /* Output DMA control register */
0486 #define EXYNOS_CIOCTRL_WEAVE_OUT            (1 << 31)
0487 #define EXYNOS_CIOCTRL_WEAVE_MASK           (1 << 31)
0488 #define EXYNOS_CIOCTRL_LASTENDEN            (1 << 30)
0489 #define EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR     (0 << 24)
0490 #define EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB     (1 << 24)
0491 #define EXYNOS_CIOCTRL_ORDER2P_MSB_CRCB     (2 << 24)
0492 #define EXYNOS_CIOCTRL_ORDER2P_MSB_CBCR     (3 << 24)
0493 #define EXYNOS_CIOCTRL_ORDER2P_SHIFT        (24)
0494 #define EXYNOS_CIOCTRL_ORDER2P_MASK     (3 << 24)
0495 #define EXYNOS_CIOCTRL_YCBCR_3PLANE     (0 << 3)
0496 #define EXYNOS_CIOCTRL_YCBCR_2PLANE     (1 << 3)
0497 #define EXYNOS_CIOCTRL_YCBCR_PLANE_MASK     (1 << 3)
0498 #define EXYNOS_CIOCTRL_LASTIRQ_ENABLE       (1 << 2)
0499 #define EXYNOS_CIOCTRL_ALPHA_OUT            (0xff << 4)
0500 #define EXYNOS_CIOCTRL_ORDER422_YCBYCR      (0 << 0)
0501 #define EXYNOS_CIOCTRL_ORDER422_YCRYCB      (1 << 0)
0502 #define EXYNOS_CIOCTRL_ORDER422_CBYCRY      (2 << 0)
0503 #define EXYNOS_CIOCTRL_ORDER422_CRYCBY      (3 << 0)
0504 #define EXYNOS_CIOCTRL_ORDER422_MASK        (3 << 0)
0505
0506 /* Main scaler control register */
0507 #define EXYNOS_CISCCTRL_SCALERBYPASS        (1 << 31)
0508 #define EXYNOS_CISCCTRL_SCALEUP_H           (1 << 30)
0509 #define EXYNOS_CISCCTRL_SCALEUP_V           (1 << 29)
0510 #define EXYNOS_CISCCTRL_CSCR2Y_NARROW       (0 << 28)
0511 #define EXYNOS_CISCCTRL_CSCR2Y_WIDE     (1 << 28)
0512 #define EXYNOS_CISCCTRL_CSCY2R_NARROW       (0 << 27)
0513 #define EXYNOS_CISCCTRL_CSCY2R_WIDE     (1 << 27)
0514 #define EXYNOS_CISCCTRL_LCDPATHEN_FIFO      (1 << 26)
0515 #define EXYNOS_CISCCTRL_PROGRESSIVE     (0 << 25)
0516 #define EXYNOS_CISCCTRL_INTERLACE           (1 << 25)
0517 #define EXYNOS_CISCCTRL_SCAN_MASK           (1 << 25)
0518 #define EXYNOS_CISCCTRL_SCALERSTART     (1 << 15)
0519 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB565        (0 << 13)
0520 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB666        (1 << 13)
0521 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB888        (2 << 13)
0522 #define EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK      (3 << 13)
0523 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565       (0 << 11)
0524 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB666       (1 << 11)
0525 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888       (2 << 11)
0526 #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK (3 << 11)
0527 #define EXYNOS_CISCCTRL_EXTRGB_NORMAL       (0 << 10)
0528 #define EXYNOS_CISCCTRL_EXTRGB_EXTENSION        (1 << 10)
0529 #define EXYNOS_CISCCTRL_ONE2ONE         (1 << 9)
0530 #define EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK       (0x1ff << 0)
0531 #define EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK       (0x1ff << 16)
0532
0533 /* Status register */
0534 #define EXYNOS_CISTATUS_OVFIY           (1 << 31)
0535 #define EXYNOS_CISTATUS_OVFICB          (1 << 30)
0536 #define EXYNOS_CISTATUS_OVFICR          (1 << 29)
0537 #define EXYNOS_CISTATUS_VSYNC           (1 << 28)
0538 #define EXYNOS_CISTATUS_SCALERSTART     (1 << 26)
0539 #define EXYNOS_CISTATUS_WINOFSTEN           (1 << 25)
0540 #define EXYNOS_CISTATUS_IMGCPTEN            (1 << 22)
0541 #define EXYNOS_CISTATUS_IMGCPTENSC          (1 << 21)
0542 #define EXYNOS_CISTATUS_VSYNC_A         (1 << 20)
0543 #define EXYNOS_CISTATUS_VSYNC_B         (1 << 19)
0544 #define EXYNOS_CISTATUS_OVRLB           (1 << 18)
0545 #define EXYNOS_CISTATUS_FRAMEEND            (1 << 17)
0546 #define EXYNOS_CISTATUS_LASTCAPTUREEND      (1 << 16)
0547 #define EXYNOS_CISTATUS_VVALID_A            (1 << 15)
0548 #define EXYNOS_CISTATUS_VVALID_B            (1 << 14)
0549
0550 /* Image capture enable register */
0551 #define EXYNOS_CIIMGCPT_IMGCPTEN            (1 << 31)
0552 #define EXYNOS_CIIMGCPT_IMGCPTEN_SC     (1 << 30)
0553 #define EXYNOS_CIIMGCPT_CPT_FREN_ENABLE     (1 << 25)
0554 #define EXYNOS_CIIMGCPT_CPT_FRMOD_EN        (0 << 18)
0555 #define EXYNOS_CIIMGCPT_CPT_FRMOD_CNT       (1 << 18)
0556
0557 /* Image effects register */
0558 #define EXYNOS_CIIMGEFF_IE_DISABLE          (0 << 30)
0559 #define EXYNOS_CIIMGEFF_IE_ENABLE           (1 << 30)
0560 #define EXYNOS_CIIMGEFF_IE_SC_BEFORE        (0 << 29)
0561 #define EXYNOS_CIIMGEFF_IE_SC_AFTER     (1 << 29)
0562 #define EXYNOS_CIIMGEFF_FIN_BYPASS          (0 << 26)
0563 #define EXYNOS_CIIMGEFF_FIN_ARBITRARY       (1 << 26)
0564 #define EXYNOS_CIIMGEFF_FIN_NEGATIVE        (2 << 26)
0565 #define EXYNOS_CIIMGEFF_FIN_ARTFREEZE       (3 << 26)
0566 #define EXYNOS_CIIMGEFF_FIN_EMBOSSING       (4 << 26)
0567 #define EXYNOS_CIIMGEFF_FIN_SILHOUETTE      (5 << 26)
0568 #define EXYNOS_CIIMGEFF_FIN_MASK            (7 << 26)
0569 #define EXYNOS_CIIMGEFF_PAT_CBCR_MASK       ((0xff << 13) | (0xff << 0))
0570
0571 /* Real input DMA size register */
0572 #define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31)
0573 #define EXYNOS_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30)
0574 #define EXYNOS_CIREAL_ISIZE_HEIGHT_MASK     (0x3FFF << 16)
0575 #define EXYNOS_CIREAL_ISIZE_WIDTH_MASK      (0x3FFF << 0)
0576
0577 /* Input DMA control register */
0578 #define EXYNOS_MSCTRL_FIELD_MASK            (1 << 31)
0579 #define EXYNOS_MSCTRL_FIELD_WEAVE           (1 << 31)
0580 #define EXYNOS_MSCTRL_FIELD_NORMAL          (0 << 31)
0581 #define EXYNOS_MSCTRL_BURST_CNT         (24)
0582 #define EXYNOS_MSCTRL_BURST_CNT_MASK        (0xf << 24)
0583 #define EXYNOS_MSCTRL_ORDER2P_LSB_CBCR      (0 << 16)
0584 #define EXYNOS_MSCTRL_ORDER2P_LSB_CRCB      (1 << 16)
0585 #define EXYNOS_MSCTRL_ORDER2P_MSB_CRCB      (2 << 16)
0586 #define EXYNOS_MSCTRL_ORDER2P_MSB_CBCR      (3 << 16)
0587 #define EXYNOS_MSCTRL_ORDER2P_SHIFT     (16)
0588 #define EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK        (0x3 << 16)
0589 #define EXYNOS_MSCTRL_C_INT_IN_3PLANE       (0 << 15)
0590 #define EXYNOS_MSCTRL_C_INT_IN_2PLANE       (1 << 15)
0591 #define EXYNOS_MSCTRL_FLIP_SHIFT            (13)
0592 #define EXYNOS_MSCTRL_FLIP_NORMAL           (0 << 13)
0593 #define EXYNOS_MSCTRL_FLIP_X_MIRROR     (1 << 13)
0594 #define EXYNOS_MSCTRL_FLIP_Y_MIRROR     (2 << 13)
0595 #define EXYNOS_MSCTRL_FLIP_180          (3 << 13)
0596 #define EXYNOS_MSCTRL_FLIP_MASK         (3 << 13)
0597 #define EXYNOS_MSCTRL_ORDER422_CRYCBY       (0 << 4)
0598 #define EXYNOS_MSCTRL_ORDER422_YCRYCB       (1 << 4)
0599 #define EXYNOS_MSCTRL_ORDER422_CBYCRY       (2 << 4)
0600 #define EXYNOS_MSCTRL_ORDER422_YCBYCR       (3 << 4)
0601 #define EXYNOS_MSCTRL_INPUT_EXTCAM          (0 << 3)
0602 #define EXYNOS_MSCTRL_INPUT_MEMORY          (1 << 3)
0603 #define EXYNOS_MSCTRL_INPUT_MASK            (1 << 3)
0604 #define EXYNOS_MSCTRL_INFORMAT_YCBCR420     (0 << 1)
0605 #define EXYNOS_MSCTRL_INFORMAT_YCBCR422     (1 << 1)
0606 #define EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE  (2 << 1)
0607 #define EXYNOS_MSCTRL_INFORMAT_RGB          (3 << 1)
0608 #define EXYNOS_MSCTRL_ENVID         (1 << 0)
0609
0610 /* DMA parameter register */
0611 #define EXYNOS_CIDMAPARAM_R_MODE_LINEAR     (0 << 29)
0612 #define EXYNOS_CIDMAPARAM_R_MODE_CONFTILE       (1 << 29)
0613 #define EXYNOS_CIDMAPARAM_R_MODE_16X16      (2 << 29)
0614 #define EXYNOS_CIDMAPARAM_R_MODE_64X32      (3 << 29)
0615 #define EXYNOS_CIDMAPARAM_R_MODE_MASK       (3 << 29)
0616 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_64       (0 << 24)
0617 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_128      (1 << 24)
0618 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_256      (2 << 24)
0619 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_512      (3 << 24)
0620 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24)
0621 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24)
0622 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24)
0623 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_1        (0 << 20)
0624 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_2        (1 << 20)
0625 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_4        (2 << 20)
0626 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_8        (3 << 20)
0627 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_16       (4 << 20)
0628 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_32       (5 << 20)
0629 #define EXYNOS_CIDMAPARAM_W_MODE_LINEAR     (0 << 13)
0630 #define EXYNOS_CIDMAPARAM_W_MODE_CONFTILE       (1 << 13)
0631 #define EXYNOS_CIDMAPARAM_W_MODE_16X16      (2 << 13)
0632 #define EXYNOS_CIDMAPARAM_W_MODE_64X32      (3 << 13)
0633 #define EXYNOS_CIDMAPARAM_W_MODE_MASK       (3 << 13)
0634 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_64       (0 << 8)
0635 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_128      (1 << 8)
0636 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_256      (2 << 8)
0637 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_512      (3 << 8)
0638 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8)
0639 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8)
0640 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8)
0641 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_1        (0 << 4)
0642 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_2        (1 << 4)
0643 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_4        (2 << 4)
0644 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_8        (3 << 4)
0645 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_16       (4 << 4)
0646 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_32       (5 << 4)
0647
0648 /* Gathering Extension register */
0649 #define EXYNOS_CIEXTEN_TARGETH_EXT_MASK     (1 << 26)
0650 #define EXYNOS_CIEXTEN_TARGETV_EXT_MASK     (1 << 24)
0651 #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK    (0x3F << 10)
0652 #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK    (0x3F)
0653 #define EXYNOS_CIEXTEN_YUV444_OUT           (1 << 22)
0654
0655 /* FIMC Clock Source Select register */
0656 #define EXYNOS_CLKSRC_HCLK              (0 << 1)
0657 #define EXYNOS_CLKSRC_HCLK_MASK         (1 << 1)
0658 #define EXYNOS_CLKSRC_SCLK              (1 << 1)
0659
0660 /* SYSREG for FIMC writeback */
0661 #define SYSREG_CAMERA_BLK           (0x0218)
0662 #define SYSREG_FIMD0WB_DEST_MASK        (0x3 << 23)
0663 #define SYSREG_FIMD0WB_DEST_SHIFT       23
0664
0665 #endif /* EXYNOS_REGS_FIMC_H */