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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0004  * Author: Ajay Kumar <ajaykumar.rs@samsung.com>
0005  */
0006 
0007 #ifndef EXYNOS_REGS_DECON7_H
0008 #define EXYNOS_REGS_DECON7_H
0009 
0010 /* VIDCON0 */
0011 #define VIDCON0                 0x00
0012 
0013 #define VIDCON0_SWRESET             (1 << 28)
0014 #define VIDCON0_DECON_STOP_STATUS       (1 << 2)
0015 #define VIDCON0_ENVID               (1 << 1)
0016 #define VIDCON0_ENVID_F             (1 << 0)
0017 
0018 /* VIDOUTCON0 */
0019 #define VIDOUTCON0              0x4
0020 
0021 #define VIDOUTCON0_DUAL_MASK            (0x3 << 24)
0022 #define VIDOUTCON0_DUAL_ON          (0x3 << 24)
0023 #define VIDOUTCON0_DISP_IF_1_ON         (0x2 << 24)
0024 #define VIDOUTCON0_DISP_IF_0_ON         (0x1 << 24)
0025 #define VIDOUTCON0_DUAL_OFF         (0x0 << 24)
0026 #define VIDOUTCON0_IF_SHIFT         23
0027 #define VIDOUTCON0_IF_MASK          (0x1 << 23)
0028 #define VIDOUTCON0_RGBIF            (0x0 << 23)
0029 #define VIDOUTCON0_I80IF            (0x1 << 23)
0030 
0031 /* VIDCON3 */
0032 #define VIDCON3                 0x8
0033 
0034 /* VIDCON4 */
0035 #define VIDCON4                 0xC
0036 #define VIDCON4_FIFOCNT_START_EN        (1 << 0)
0037 
0038 /* VCLKCON0 */
0039 #define VCLKCON0                0x10
0040 #define VCLKCON0_CLKVALUP           (1 << 8)
0041 #define VCLKCON0_VCLKFREE           (1 << 0)
0042 
0043 /* VCLKCON */
0044 #define VCLKCON1                0x14
0045 #define VCLKCON1_CLKVAL_NUM_VCLK(val)       (((val) & 0xff) << 0)
0046 #define VCLKCON2                0x18
0047 
0048 /* SHADOWCON */
0049 #define SHADOWCON               0x30
0050 
0051 #define SHADOWCON_WINx_PROTECT(_win)        (1 << (10 + (_win)))
0052 
0053 /* WINCONx */
0054 #define WINCON(_win)                (0x50 + ((_win) * 4))
0055 
0056 #define WINCONx_BUFSTATUS           (0x3 << 30)
0057 #define WINCONx_BUFSEL_MASK         (0x3 << 28)
0058 #define WINCONx_BUFSEL_SHIFT            28
0059 #define WINCONx_TRIPLE_BUF_MODE         (0x1 << 18)
0060 #define WINCONx_DOUBLE_BUF_MODE         (0x0 << 18)
0061 #define WINCONx_BURSTLEN_16WORD         (0x0 << 11)
0062 #define WINCONx_BURSTLEN_8WORD          (0x1 << 11)
0063 #define WINCONx_BURSTLEN_MASK           (0x1 << 11)
0064 #define WINCONx_BURSTLEN_SHIFT          11
0065 #define WINCONx_BLD_PLANE           (0 << 8)
0066 #define WINCONx_BLD_PIX             (1 << 8)
0067 #define WINCONx_ALPHA_MUL           (1 << 7)
0068 
0069 #define WINCONx_BPPMODE_MASK            (0xf << 2)
0070 #define WINCONx_BPPMODE_SHIFT           2
0071 #define WINCONx_BPPMODE_16BPP_565       (0x8 << 2)
0072 #define WINCONx_BPPMODE_24BPP_BGRx      (0x7 << 2)
0073 #define WINCONx_BPPMODE_24BPP_RGBx      (0x6 << 2)
0074 #define WINCONx_BPPMODE_24BPP_xBGR      (0x5 << 2)
0075 #define WINCONx_BPPMODE_24BPP_xRGB      (0x4 << 2)
0076 #define WINCONx_BPPMODE_32BPP_BGRA      (0x3 << 2)
0077 #define WINCONx_BPPMODE_32BPP_RGBA      (0x2 << 2)
0078 #define WINCONx_BPPMODE_32BPP_ABGR      (0x1 << 2)
0079 #define WINCONx_BPPMODE_32BPP_ARGB      (0x0 << 2)
0080 #define WINCONx_ALPHA_SEL           (1 << 1)
0081 #define WINCONx_ENWIN               (1 << 0)
0082 
0083 #define WINCON1_ALPHA_MUL_F         (1 << 7)
0084 #define WINCON2_ALPHA_MUL_F         (1 << 7)
0085 #define WINCON3_ALPHA_MUL_F         (1 << 7)
0086 #define WINCON4_ALPHA_MUL_F         (1 << 7)
0087 
0088 /*  VIDOSDxH: The height for the OSD image(READ ONLY)*/
0089 #define VIDOSD_H(_x)                (0x80 + ((_x) * 4))
0090 
0091 /* Frame buffer start addresses: VIDWxxADD0n */
0092 #define VIDW_BUF_START(_win)            (0x80 + ((_win) * 0x10))
0093 #define VIDW_BUF_START1(_win)           (0x84 + ((_win) * 0x10))
0094 #define VIDW_BUF_START2(_win)           (0x88 + ((_win) * 0x10))
0095 
0096 #define VIDW_WHOLE_X(_win)          (0x0130 + ((_win) * 8))
0097 #define VIDW_WHOLE_Y(_win)          (0x0134 + ((_win) * 8))
0098 #define VIDW_OFFSET_X(_win)         (0x0170 + ((_win) * 8))
0099 #define VIDW_OFFSET_Y(_win)         (0x0174 + ((_win) * 8))
0100 #define VIDW_BLKOFFSET(_win)            (0x01B0 + ((_win) * 4))
0101 #define VIDW_BLKSIZE(win)           (0x0200 + ((_win) * 4))
0102 
0103 /* Interrupt controls register */
0104 #define VIDINTCON2              0x228
0105 
0106 #define VIDINTCON1_INTEXTRA1_EN         (1 << 1)
0107 #define VIDINTCON1_INTEXTRA0_EN         (1 << 0)
0108 
0109 /* Interrupt controls and status register */
0110 #define VIDINTCON3              0x22C
0111 
0112 #define VIDINTCON1_INTEXTRA1_PEND       (1 << 1)
0113 #define VIDINTCON1_INTEXTRA0_PEND       (1 << 0)
0114 
0115 /* VIDOSDxA ~ VIDOSDxE */
0116 #define VIDOSD_BASE             0x230
0117 
0118 #define OSD_STRIDE              0x20
0119 
0120 #define VIDOSD_A(_win)              (VIDOSD_BASE + \
0121                         ((_win) * OSD_STRIDE) + 0x00)
0122 #define VIDOSD_B(_win)              (VIDOSD_BASE + \
0123                         ((_win) * OSD_STRIDE) + 0x04)
0124 #define VIDOSD_C(_win)              (VIDOSD_BASE + \
0125                         ((_win) * OSD_STRIDE) + 0x08)
0126 #define VIDOSD_D(_win)              (VIDOSD_BASE + \
0127                         ((_win) * OSD_STRIDE) + 0x0C)
0128 #define VIDOSD_E(_win)              (VIDOSD_BASE + \
0129                         ((_win) * OSD_STRIDE) + 0x10)
0130 
0131 #define VIDOSDxA_TOPLEFT_X_MASK         (0x1fff << 13)
0132 #define VIDOSDxA_TOPLEFT_X_SHIFT        13
0133 #define VIDOSDxA_TOPLEFT_X_LIMIT        0x1fff
0134 #define VIDOSDxA_TOPLEFT_X(_x)          (((_x) & 0x1fff) << 13)
0135 
0136 #define VIDOSDxA_TOPLEFT_Y_MASK         (0x1fff << 0)
0137 #define VIDOSDxA_TOPLEFT_Y_SHIFT        0
0138 #define VIDOSDxA_TOPLEFT_Y_LIMIT        0x1fff
0139 #define VIDOSDxA_TOPLEFT_Y(_x)          (((_x) & 0x1fff) << 0)
0140 
0141 #define VIDOSDxB_BOTRIGHT_X_MASK        (0x1fff << 13)
0142 #define VIDOSDxB_BOTRIGHT_X_SHIFT       13
0143 #define VIDOSDxB_BOTRIGHT_X_LIMIT       0x1fff
0144 #define VIDOSDxB_BOTRIGHT_X(_x)         (((_x) & 0x1fff) << 13)
0145 
0146 #define VIDOSDxB_BOTRIGHT_Y_MASK        (0x1fff << 0)
0147 #define VIDOSDxB_BOTRIGHT_Y_SHIFT       0
0148 #define VIDOSDxB_BOTRIGHT_Y_LIMIT       0x1fff
0149 #define VIDOSDxB_BOTRIGHT_Y(_x)         (((_x) & 0x1fff) << 0)
0150 
0151 #define VIDOSDxC_ALPHA0_R_F(_x)         (((_x) & 0xFF) << 16)
0152 #define VIDOSDxC_ALPHA0_G_F(_x)         (((_x) & 0xFF) << 8)
0153 #define VIDOSDxC_ALPHA0_B_F(_x)         (((_x) & 0xFF) << 0)
0154 
0155 #define VIDOSDxD_ALPHA1_R_F(_x)         (((_x) & 0xFF) << 16)
0156 #define VIDOSDxD_ALPHA1_G_F(_x)         (((_x) & 0xFF) << 8)
0157 #define VIDOSDxD_ALPHA1_B_F(_x)         (((_x) & 0xFF) >> 0)
0158 
0159 /* Window MAP (Color map) */
0160 #define WINxMAP(_win)               (0x340 + ((_win) * 4))
0161 
0162 #define WINxMAP_MAP             (1 << 24)
0163 #define WINxMAP_MAP_COLOUR_MASK         (0xffffff << 0)
0164 #define WINxMAP_MAP_COLOUR_SHIFT        0
0165 #define WINxMAP_MAP_COLOUR_LIMIT        0xffffff
0166 #define WINxMAP_MAP_COLOUR(_x)          ((_x) << 0)
0167 
0168 /* Window colour-key control registers */
0169 #define WKEYCON                 0x370
0170 
0171 #define WKEYCON0                0x00
0172 #define WKEYCON1                0x04
0173 #define WxKEYCON0_KEYBL_EN          (1 << 26)
0174 #define WxKEYCON0_KEYEN_F           (1 << 25)
0175 #define WxKEYCON0_DIRCON            (1 << 24)
0176 #define WxKEYCON0_COMPKEY_MASK          (0xffffff << 0)
0177 #define WxKEYCON0_COMPKEY_SHIFT         0
0178 #define WxKEYCON0_COMPKEY_LIMIT         0xffffff
0179 #define WxKEYCON0_COMPKEY(_x)           ((_x) << 0)
0180 #define WxKEYCON1_COLVAL_MASK           (0xffffff << 0)
0181 #define WxKEYCON1_COLVAL_SHIFT          0
0182 #define WxKEYCON1_COLVAL_LIMIT          0xffffff
0183 #define WxKEYCON1_COLVAL(_x)            ((_x) << 0)
0184 
0185 /* color key control register for hardware window 1 ~ 4. */
0186 #define WKEYCON0_BASE(x)        ((WKEYCON + WKEYCON0) + ((x - 1) * 8))
0187 /* color key value register for hardware window 1 ~ 4. */
0188 #define WKEYCON1_BASE(x)        ((WKEYCON + WKEYCON1) + ((x - 1) * 8))
0189 
0190 /* Window KEY Alpha value */
0191 #define WxKEYALPHA(_win)            (0x3A0 + (((_win) - 1) * 0x4))
0192 
0193 #define Wx_KEYALPHA_R_F_SHIFT           16
0194 #define Wx_KEYALPHA_G_F_SHIFT           8
0195 #define Wx_KEYALPHA_B_F_SHIFT           0
0196 
0197 /* Blending equation */
0198 #define BLENDE(_win)                (0x03C0 + ((_win) * 4))
0199 #define BLENDE_COEF_ZERO            0x0
0200 #define BLENDE_COEF_ONE             0x1
0201 #define BLENDE_COEF_ALPHA_A         0x2
0202 #define BLENDE_COEF_ONE_MINUS_ALPHA_A       0x3
0203 #define BLENDE_COEF_ALPHA_B         0x4
0204 #define BLENDE_COEF_ONE_MINUS_ALPHA_B       0x5
0205 #define BLENDE_COEF_ALPHA0          0x6
0206 #define BLENDE_COEF_A               0xA
0207 #define BLENDE_COEF_ONE_MINUS_A         0xB
0208 #define BLENDE_COEF_B               0xC
0209 #define BLENDE_COEF_ONE_MINUS_B         0xD
0210 #define BLENDE_Q_FUNC(_v)           ((_v) << 18)
0211 #define BLENDE_P_FUNC(_v)           ((_v) << 12)
0212 #define BLENDE_B_FUNC(_v)           ((_v) << 6)
0213 #define BLENDE_A_FUNC(_v)           ((_v) << 0)
0214 
0215 /* Blending equation control */
0216 #define BLENDCON                0x3D8
0217 #define BLENDCON_NEW_MASK           (1 << 0)
0218 #define BLENDCON_NEW_8BIT_ALPHA_VALUE       (1 << 0)
0219 #define BLENDCON_NEW_4BIT_ALPHA_VALUE       (0 << 0)
0220 
0221 /* Interrupt control register */
0222 #define VIDINTCON0              0x500
0223 
0224 #define VIDINTCON0_WAKEUP_MASK          (0x3f << 26)
0225 #define VIDINTCON0_INTEXTRAEN           (1 << 21)
0226 
0227 #define VIDINTCON0_FRAMESEL0_SHIFT      15
0228 #define VIDINTCON0_FRAMESEL0_MASK       (0x3 << 15)
0229 #define VIDINTCON0_FRAMESEL0_BACKPORCH      (0x0 << 15)
0230 #define VIDINTCON0_FRAMESEL0_VSYNC      (0x1 << 15)
0231 #define VIDINTCON0_FRAMESEL0_ACTIVE     (0x2 << 15)
0232 #define VIDINTCON0_FRAMESEL0_FRONTPORCH     (0x3 << 15)
0233 
0234 #define VIDINTCON0_INT_FRAME            (1 << 11)
0235 
0236 #define VIDINTCON0_FIFOLEVEL_MASK       (0x7 << 3)
0237 #define VIDINTCON0_FIFOLEVEL_SHIFT      3
0238 #define VIDINTCON0_FIFOLEVEL_EMPTY      (0x0 << 3)
0239 #define VIDINTCON0_FIFOLEVEL_TO25PC     (0x1 << 3)
0240 #define VIDINTCON0_FIFOLEVEL_TO50PC     (0x2 << 3)
0241 #define VIDINTCON0_FIFOLEVEL_FULL       (0x4 << 3)
0242 
0243 #define VIDINTCON0_FIFOSEL_MAIN_EN      (1 << 1)
0244 #define VIDINTCON0_INT_FIFO         (1 << 1)
0245 
0246 #define VIDINTCON0_INT_ENABLE           (1 << 0)
0247 
0248 /* Interrupt controls and status register */
0249 #define VIDINTCON1              0x504
0250 
0251 #define VIDINTCON1_INT_EXTRA            (1 << 3)
0252 #define VIDINTCON1_INT_I80          (1 << 2)
0253 #define VIDINTCON1_INT_FRAME            (1 << 1)
0254 #define VIDINTCON1_INT_FIFO         (1 << 0)
0255 
0256 /* VIDCON1 */
0257 #define VIDCON1(_x)             (0x0600 + ((_x) * 0x50))
0258 #define VIDCON1_LINECNT_GET(_v)         (((_v) >> 17) & 0x1fff)
0259 #define VIDCON1_VCLK_MASK           (0x3 << 9)
0260 #define VIDCON1_VCLK_HOLD           (0x0 << 9)
0261 #define VIDCON1_VCLK_RUN            (0x1 << 9)
0262 #define VIDCON1_VCLK_RUN_VDEN_DISABLE       (0x3 << 9)
0263 #define VIDCON1_RGB_ORDER_O_MASK        (0x7 << 4)
0264 #define VIDCON1_RGB_ORDER_O_RGB         (0x0 << 4)
0265 #define VIDCON1_RGB_ORDER_O_GBR         (0x1 << 4)
0266 #define VIDCON1_RGB_ORDER_O_BRG         (0x2 << 4)
0267 #define VIDCON1_RGB_ORDER_O_BGR         (0x4 << 4)
0268 #define VIDCON1_RGB_ORDER_O_RBG         (0x5 << 4)
0269 #define VIDCON1_RGB_ORDER_O_GRB         (0x6 << 4)
0270 
0271 /* VIDTCON0 */
0272 #define VIDTCON0                0x610
0273 
0274 #define VIDTCON0_VBPD_MASK          (0xffff << 16)
0275 #define VIDTCON0_VBPD_SHIFT         16
0276 #define VIDTCON0_VBPD_LIMIT         0xffff
0277 #define VIDTCON0_VBPD(_x)           ((_x) << 16)
0278 
0279 #define VIDTCON0_VFPD_MASK          (0xffff << 0)
0280 #define VIDTCON0_VFPD_SHIFT         0
0281 #define VIDTCON0_VFPD_LIMIT         0xffff
0282 #define VIDTCON0_VFPD(_x)           ((_x) << 0)
0283 
0284 /* VIDTCON1 */
0285 #define VIDTCON1                0x614
0286 
0287 #define VIDTCON1_VSPW_MASK          (0xffff << 16)
0288 #define VIDTCON1_VSPW_SHIFT         16
0289 #define VIDTCON1_VSPW_LIMIT         0xffff
0290 #define VIDTCON1_VSPW(_x)           ((_x) << 16)
0291 
0292 /* VIDTCON2 */
0293 #define VIDTCON2                0x618
0294 
0295 #define VIDTCON2_HBPD_MASK          (0xffff << 16)
0296 #define VIDTCON2_HBPD_SHIFT         16
0297 #define VIDTCON2_HBPD_LIMIT         0xffff
0298 #define VIDTCON2_HBPD(_x)           ((_x) << 16)
0299 
0300 #define VIDTCON2_HFPD_MASK          (0xffff << 0)
0301 #define VIDTCON2_HFPD_SHIFT         0
0302 #define VIDTCON2_HFPD_LIMIT         0xffff
0303 #define VIDTCON2_HFPD(_x)           ((_x) << 0)
0304 
0305 /* VIDTCON3 */
0306 #define VIDTCON3                0x61C
0307 
0308 #define VIDTCON3_HSPW_MASK          (0xffff << 16)
0309 #define VIDTCON3_HSPW_SHIFT         16
0310 #define VIDTCON3_HSPW_LIMIT         0xffff
0311 #define VIDTCON3_HSPW(_x)           ((_x) << 16)
0312 
0313 /* VIDTCON4 */
0314 #define VIDTCON4                0x620
0315 
0316 #define VIDTCON4_LINEVAL_MASK           (0xfff << 16)
0317 #define VIDTCON4_LINEVAL_SHIFT          16
0318 #define VIDTCON4_LINEVAL_LIMIT          0xfff
0319 #define VIDTCON4_LINEVAL(_x)            (((_x) & 0xfff) << 16)
0320 
0321 #define VIDTCON4_HOZVAL_MASK            (0xfff << 0)
0322 #define VIDTCON4_HOZVAL_SHIFT           0
0323 #define VIDTCON4_HOZVAL_LIMIT           0xfff
0324 #define VIDTCON4_HOZVAL(_x)         (((_x) & 0xfff) << 0)
0325 
0326 /* LINECNT OP THRSHOLD*/
0327 #define LINECNT_OP_THRESHOLD            0x630
0328 
0329 /* CRCCTRL */
0330 #define CRCCTRL                 0x6C8
0331 #define CRCCTRL_CRCCLKEN            (0x1 << 2)
0332 #define CRCCTRL_CRCSTART_F          (0x1 << 1)
0333 #define CRCCTRL_CRCEN               (0x1 << 0)
0334 
0335 /* DECON_CMU */
0336 #define DECON_CMU               0x704
0337 
0338 #define DECON_CMU_ALL_CLKGATE_ENABLE        0x3
0339 #define DECON_CMU_SE_CLKGATE_ENABLE     (0x1 << 2)
0340 #define DECON_CMU_SFR_CLKGATE_ENABLE        (0x1 << 1)
0341 #define DECON_CMU_MEM_CLKGATE_ENABLE        (0x1 << 0)
0342 
0343 /* DECON_UPDATE */
0344 #define DECON_UPDATE                0x710
0345 
0346 #define DECON_UPDATE_SLAVE_SYNC         (1 << 4)
0347 #define DECON_UPDATE_STANDALONE_F       (1 << 0)
0348 
0349 #endif /* EXYNOS_REGS_DECON7_H */