drm/exynos/regs-decon5433.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Samsung Electronics Co.Ltd
0004  */
0005
0006 #ifndef EXYNOS_REGS_DECON5433_H
0007 #define EXYNOS_REGS_DECON5433_H
0008
0009 /* Exynos543X DECON */
0010 #define DECON_VIDCON0           0x0000
0011 #define DECON_VIDOUTCON0        0x0010
0012 #define DECON_WINCONx(n)        (0x0020 + ((n) * 4))
0013 #define DECON_VIDOSDxH(n)       (0x0080 + ((n) * 4))
0014 #define DECON_SHADOWCON         0x00A0
0015 #define DECON_VIDOSDxA(n)       (0x00B0 + ((n) * 0x20))
0016 #define DECON_VIDOSDxB(n)       (0x00B4 + ((n) * 0x20))
0017 #define DECON_VIDOSDxC(n)       (0x00B8 + ((n) * 0x20))
0018 #define DECON_VIDOSDxD(n)       (0x00BC + ((n) * 0x20))
0019 #define DECON_VIDOSDxE(n)       (0x00C0 + ((n) * 0x20))
0020 #define DECON_VIDW0xADD0B0(n)       (0x0150 + ((n) * 0x10))
0021 #define DECON_VIDW0xADD0B1(n)       (0x0154 + ((n) * 0x10))
0022 #define DECON_VIDW0xADD0B2(n)       (0x0158 + ((n) * 0x10))
0023 #define DECON_VIDW0xADD1B0(n)       (0x01A0 + ((n) * 0x10))
0024 #define DECON_VIDW0xADD1B1(n)       (0x01A4 + ((n) * 0x10))
0025 #define DECON_VIDW0xADD1B2(n)       (0x01A8 + ((n) * 0x10))
0026 #define DECON_VIDW0xADD2(n)     (0x0200 + ((n) * 4))
0027 #define DECON_LOCALxSIZE(n)     (0x0214 + ((n) * 4))
0028 #define DECON_VIDINTCON0        0x0220
0029 #define DECON_VIDINTCON1        0x0224
0030 #define DECON_WxKEYCON0(n)      (0x0230 + ((n - 1) * 8))
0031 #define DECON_WxKEYCON1(n)      (0x0234 + ((n - 1) * 8))
0032 #define DECON_WxKEYALPHA(n)     (0x0250 + ((n - 1) * 4))
0033 #define DECON_WINxMAP(n)        (0x0270 + ((n) * 4))
0034 #define DECON_QOSLUT07_00       0x02C0
0035 #define DECON_QOSLUT15_08       0x02C4
0036 #define DECON_QOSCTRL           0x02C8
0037 #define DECON_BLENDERQx(n)      (0x0300 + ((n - 1) * 4))
0038 #define DECON_BLENDCON          0x0310
0039 #define DECON_OPE_VIDW0xADD0(n)     (0x0400 + ((n) * 4))
0040 #define DECON_OPE_VIDW0xADD1(n)     (0x0414 + ((n) * 4))
0041 #define DECON_FRAMEFIFO_REG7        0x051C
0042 #define DECON_FRAMEFIFO_REG8        0x0520
0043 #define DECON_FRAMEFIFO_STATUS      0x0524
0044 #define DECON_CMU           0x1404
0045 #define DECON_UPDATE            0x1410
0046 #define DECON_CRFMID            0x1414
0047 #define DECON_UPDATE_SCHEME     0x1438
0048 #define DECON_VIDCON1           0x2000
0049 #define DECON_VIDCON2           0x2004
0050 #define DECON_VIDCON3           0x2008
0051 #define DECON_VIDCON4           0x200C
0052 #define DECON_VIDTCON2          0x2028
0053 #define DECON_FRAME_SIZE        0x2038
0054 #define DECON_LINECNT_OP_THRESHOLD  0x203C
0055 #define DECON_TRIGCON           0x2040
0056 #define DECON_TRIGSKIP          0x2050
0057 #define DECON_CRCRDATA          0x20B0
0058 #define DECON_CRCCTRL           0x20B4
0059
0060 /* Exynos5430 DECON */
0061 #define DECON_VIDTCON0          0x2020
0062 #define DECON_VIDTCON1          0x2024
0063
0064 /* Exynos5433 DECON */
0065 #define DECON_VIDTCON00         0x2010
0066 #define DECON_VIDTCON01         0x2014
0067 #define DECON_VIDTCON10         0x2018
0068 #define DECON_VIDTCON11         0x201C
0069
0070 /* Exynos543X DECON Internal */
0071 #define DECON_W013DSTREOCON     0x0320
0072 #define DECON_W233DSTREOCON     0x0324
0073 #define DECON_FRAMEFIFO_REG0        0x0500
0074 #define DECON_ENHANCER_CTRL     0x2100
0075
0076 /* Exynos543X DECON TV */
0077 #define DECON_VCLKCON0          0x0014
0078 #define DECON_VIDINTCON2        0x0228
0079 #define DECON_VIDINTCON3        0x022C
0080
0081 /* VIDCON0 */
0082 #define VIDCON0_SWRESET         (1 << 28)
0083 #define VIDCON0_CLKVALUP        (1 << 14)
0084 #define VIDCON0_VLCKFREE        (1 << 5)
0085 #define VIDCON0_STOP_STATUS     (1 << 2)
0086 #define VIDCON0_ENVID           (1 << 1)
0087 #define VIDCON0_ENVID_F         (1 << 0)
0088
0089 /* VIDOUTCON0 */
0090 #define VIDOUT_INTERLACE_FIELD_F    (1 << 29)
0091 #define VIDOUT_INTERLACE_EN_F       (1 << 28)
0092 #define VIDOUT_LCD_ON           (1 << 24)
0093 #define VIDOUT_IF_F_MASK        (0x3 << 20)
0094 #define VIDOUT_RGB_IF           (0x0 << 20)
0095 #define VIDOUT_COMMAND_IF       (0x2 << 20)
0096
0097 /* WINCONx */
0098 #define WINCONx_HAWSWP_F        (1 << 16)
0099 #define WINCONx_WSWP_F          (1 << 15)
0100 #define WINCONx_BURSTLEN_MASK       (0x3 << 10)
0101 #define WINCONx_BURSTLEN_16WORD     (0x0 << 10)
0102 #define WINCONx_BURSTLEN_8WORD      (0x1 << 10)
0103 #define WINCONx_BURSTLEN_4WORD      (0x2 << 10)
0104 #define WINCONx_ALPHA_MUL_F     (1 << 7)
0105 #define WINCONx_BLD_PIX_F       (1 << 6)
0106 #define WINCONx_BPPMODE_MASK        (0xf << 2)
0107 #define WINCONx_BPPMODE_16BPP_565   (0x5 << 2)
0108 #define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2)
0109 #define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2)
0110 #define WINCONx_BPPMODE_24BPP_888   (0xb << 2)
0111 #define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2)
0112 #define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2)
0113 #define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2)
0114 #define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2)
0115 #define WINCONx_ALPHA_SEL_F     (1 << 1)
0116 #define WINCONx_ENWIN_F         (1 << 0)
0117 #define WINCONx_BLEND_MODE_MASK     (0xc2)
0118
0119 /* SHADOWCON */
0120 #define SHADOWCON_PROTECT_MASK      GENMASK(14, 10)
0121 #define SHADOWCON_Wx_PROTECT(n)     (1 << (10 + (n)))
0122
0123 /* VIDOSDxC */
0124 #define VIDOSDxC_ALPHA0_RGB_MASK    (0xffffff)
0125
0126 /* VIDOSDxD */
0127 #define VIDOSD_Wx_ALPHA_R_F(n)      (((n) & 0xff) << 16)
0128 #define VIDOSD_Wx_ALPHA_G_F(n)      (((n) & 0xff) << 8)
0129 #define VIDOSD_Wx_ALPHA_B_F(n)      (((n) & 0xff) << 0)
0130
0131 /* VIDINTCON0 */
0132 #define VIDINTCON0_FRAMEDONE        (1 << 17)
0133 #define VIDINTCON0_FRAMESEL_BP      (0 << 15)
0134 #define VIDINTCON0_FRAMESEL_VS      (1 << 15)
0135 #define VIDINTCON0_FRAMESEL_AC      (2 << 15)
0136 #define VIDINTCON0_FRAMESEL_FP      (3 << 15)
0137 #define VIDINTCON0_INTFRMEN     (1 << 12)
0138 #define VIDINTCON0_INTEN        (1 << 0)
0139
0140 /* VIDINTCON1 */
0141 #define VIDINTCON1_INTFRMDONEPEND   (1 << 2)
0142 #define VIDINTCON1_INTFRMPEND       (1 << 1)
0143 #define VIDINTCON1_INTFIFOPEND      (1 << 0)
0144
0145 /* DECON_CMU */
0146 #define CMU_CLKGAGE_MODE_SFR_F      (1 << 1)
0147 #define CMU_CLKGAGE_MODE_MEM_F      (1 << 0)
0148
0149 /* DECON_UPDATE */
0150 #define STANDALONE_UPDATE_F     (1 << 0)
0151
0152 /* DECON_VIDCON1 */
0153 #define VIDCON1_LINECNT_MASK        (0x0fff << 16)
0154 #define VIDCON1_I80_ACTIVE      (1 << 15)
0155 #define VIDCON1_VSTATUS_MASK        (0x3 << 13)
0156 #define VIDCON1_VSTATUS_VS      (0 << 13)
0157 #define VIDCON1_VSTATUS_BP      (1 << 13)
0158 #define VIDCON1_VSTATUS_AC      (2 << 13)
0159 #define VIDCON1_VSTATUS_FP      (3 << 13)
0160 #define VIDCON1_VCLK_MASK       (0x3 << 9)
0161 #define VIDCON1_VCLK_RUN_VDEN_DISABLE   (0x3 << 9)
0162 #define VIDCON1_VCLK_HOLD       (0x0 << 9)
0163 #define VIDCON1_VCLK_RUN        (0x1 << 9)
0164
0165
0166 /* DECON_VIDTCON00 */
0167 #define VIDTCON00_VBPD_F(x)     (((x) & 0xfff) << 16)
0168 #define VIDTCON00_VFPD_F(x)     ((x) & 0xfff)
0169
0170 /* DECON_VIDTCON01 */
0171 #define VIDTCON01_VSPW_F(x)     (((x) & 0xfff) << 16)
0172
0173 /* DECON_VIDTCON10 */
0174 #define VIDTCON10_HBPD_F(x)     (((x) & 0xfff) << 16)
0175 #define VIDTCON10_HFPD_F(x)     ((x) & 0xfff)
0176
0177 /* DECON_VIDTCON11 */
0178 #define VIDTCON11_HSPW_F(x)     (((x) & 0xfff) << 16)
0179
0180 /* DECON_VIDTCON2 */
0181 #define VIDTCON2_LINEVAL(x)     (((x) & 0xfff) << 16)
0182 #define VIDTCON2_HOZVAL(x)      ((x) & 0xfff)
0183
0184 /* TRIGCON */
0185 #define TRIGCON_TRIGEN_PER_F        (1 << 31)
0186 #define TRIGCON_TRIGEN_F        (1 << 30)
0187 #define TRIGCON_TE_AUTO_MASK        (1 << 29)
0188 #define TRIGCON_WB_SWTRIGCMD        (1 << 28)
0189 #define TRIGCON_SWTRIGCMD_W4BUF     (1 << 26)
0190 #define TRIGCON_TRIGMODE_W4BUF      (1 << 25)
0191 #define TRIGCON_SWTRIGCMD_W3BUF     (1 << 21)
0192 #define TRIGCON_TRIGMODE_W3BUF      (1 << 20)
0193 #define TRIGCON_SWTRIGCMD_W2BUF     (1 << 16)
0194 #define TRIGCON_TRIGMODE_W2BUF      (1 << 15)
0195 #define TRIGCON_SWTRIGCMD_W1BUF     (1 << 11)
0196 #define TRIGCON_TRIGMODE_W1BUF      (1 << 10)
0197 #define TRIGCON_SWTRIGCMD_W0BUF     (1 << 6)
0198 #define TRIGCON_TRIGMODE_W0BUF      (1 << 5)
0199 #define TRIGCON_HWTRIGMASK      (1 << 4)
0200 #define TRIGCON_HWTRIGEN        (1 << 3)
0201 #define TRIGCON_HWTRIG_INV      (1 << 2)
0202 #define TRIGCON_SWTRIGCMD       (1 << 1)
0203 #define TRIGCON_SWTRIGEN        (1 << 0)
0204
0205 /* DECON_CRCCTRL */
0206 #define CRCCTRL_CRCCLKEN        (0x1 << 2)
0207 #define CRCCTRL_CRCSTART_F      (0x1 << 1)
0208 #define CRCCTRL_CRCEN           (0x1 << 0)
0209 #define CRCCTRL_MASK            (0x7)
0210
0211 /* BLENDCON */
0212 #define BLEND_NEW           (1 << 0)
0213
0214 /* BLENDERQx */
0215 #define BLENDERQ_ZERO           0x0
0216 #define BLENDERQ_ONE            0x1
0217 #define BLENDERQ_ALPHA_A        0x2
0218 #define BLENDERQ_ONE_MINUS_ALPHA_A  0x3
0219 #define BLENDERQ_ALPHA0         0x6
0220 #define BLENDERQ_Q_FUNC_F(n)        (n << 18)
0221 #define BLENDERQ_P_FUNC_F(n)        (n << 12)
0222 #define BLENDERQ_B_FUNC_F(n)        (n << 6)
0223 #define BLENDERQ_A_FUNC_F(n)        (n << 0)
0224
0225 /* BLENDCON */
0226 #define BLEND_NEW           (1 << 0)
0227
0228 #endif /* EXYNOS_REGS_DECON5433_H */