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0008 #include <linux/clk.h>
0009 #include <linux/component.h>
0010 #include <linux/err.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017
0018 #include <drm/drm_blend.h>
0019 #include <drm/drm_fourcc.h>
0020 #include <drm/exynos_drm.h>
0021
0022 #include "exynos_drm_drv.h"
0023 #include "exynos_drm_fb.h"
0024 #include "exynos_drm_ipp.h"
0025 #include "regs-scaler.h"
0026
0027 #define scaler_read(offset) readl(scaler->regs + (offset))
0028 #define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset))
0029 #define SCALER_MAX_CLK 4
0030 #define SCALER_AUTOSUSPEND_DELAY 2000
0031 #define SCALER_RESET_WAIT_RETRIES 100
0032
0033 struct scaler_data {
0034 const char *clk_name[SCALER_MAX_CLK];
0035 unsigned int num_clk;
0036 const struct exynos_drm_ipp_formats *formats;
0037 unsigned int num_formats;
0038 };
0039
0040 struct scaler_context {
0041 struct exynos_drm_ipp ipp;
0042 struct drm_device *drm_dev;
0043 void *dma_priv;
0044 struct device *dev;
0045 void __iomem *regs;
0046 struct clk *clock[SCALER_MAX_CLK];
0047 struct exynos_drm_ipp_task *task;
0048 const struct scaler_data *scaler_data;
0049 };
0050
0051 struct scaler_format {
0052 u32 drm_fmt;
0053 u32 internal_fmt;
0054 u32 chroma_tile_w;
0055 u32 chroma_tile_h;
0056 };
0057
0058 static const struct scaler_format scaler_formats[] = {
0059 { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
0060 { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
0061 { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
0062 { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
0063 { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
0064 { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
0065 { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
0066 { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
0067 { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
0068 { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
0069 { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
0070 { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
0071 { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
0072 { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
0073 { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
0074 { DRM_FORMAT_XRGB4444, SCALER_ARGB4444, 0, 0 },
0075 { DRM_FORMAT_ARGB4444, SCALER_ARGB4444, 0, 0 },
0076 { DRM_FORMAT_XRGB8888, SCALER_ARGB8888, 0, 0 },
0077 { DRM_FORMAT_ARGB8888, SCALER_ARGB8888, 0, 0 },
0078 { DRM_FORMAT_RGBX8888, SCALER_RGBA8888, 0, 0 },
0079 { DRM_FORMAT_RGBA8888, SCALER_RGBA8888, 0, 0 },
0080 };
0081
0082 static const struct scaler_format *scaler_get_format(u32 drm_fmt)
0083 {
0084 int i;
0085
0086 for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
0087 if (scaler_formats[i].drm_fmt == drm_fmt)
0088 return &scaler_formats[i];
0089
0090 return NULL;
0091 }
0092
0093 static inline int scaler_reset(struct scaler_context *scaler)
0094 {
0095 int retry = SCALER_RESET_WAIT_RETRIES;
0096
0097 scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG);
0098 do {
0099 cpu_relax();
0100 } while (--retry > 1 &&
0101 scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET);
0102 do {
0103 cpu_relax();
0104 scaler_write(1, SCALER_INT_EN);
0105 } while (--retry > 0 && scaler_read(SCALER_INT_EN) != 1);
0106
0107 return retry ? 0 : -EIO;
0108 }
0109
0110 static inline void scaler_enable_int(struct scaler_context *scaler)
0111 {
0112 u32 val;
0113
0114 val = SCALER_INT_EN_TIMEOUT |
0115 SCALER_INT_EN_ILLEGAL_BLEND |
0116 SCALER_INT_EN_ILLEGAL_RATIO |
0117 SCALER_INT_EN_ILLEGAL_DST_HEIGHT |
0118 SCALER_INT_EN_ILLEGAL_DST_WIDTH |
0119 SCALER_INT_EN_ILLEGAL_DST_V_POS |
0120 SCALER_INT_EN_ILLEGAL_DST_H_POS |
0121 SCALER_INT_EN_ILLEGAL_DST_C_SPAN |
0122 SCALER_INT_EN_ILLEGAL_DST_Y_SPAN |
0123 SCALER_INT_EN_ILLEGAL_DST_CR_BASE |
0124 SCALER_INT_EN_ILLEGAL_DST_CB_BASE |
0125 SCALER_INT_EN_ILLEGAL_DST_Y_BASE |
0126 SCALER_INT_EN_ILLEGAL_DST_COLOR |
0127 SCALER_INT_EN_ILLEGAL_SRC_HEIGHT |
0128 SCALER_INT_EN_ILLEGAL_SRC_WIDTH |
0129 SCALER_INT_EN_ILLEGAL_SRC_CV_POS |
0130 SCALER_INT_EN_ILLEGAL_SRC_CH_POS |
0131 SCALER_INT_EN_ILLEGAL_SRC_YV_POS |
0132 SCALER_INT_EN_ILLEGAL_SRC_YH_POS |
0133 SCALER_INT_EN_ILLEGAL_DST_SPAN |
0134 SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN |
0135 SCALER_INT_EN_ILLEGAL_SRC_CR_BASE |
0136 SCALER_INT_EN_ILLEGAL_SRC_CB_BASE |
0137 SCALER_INT_EN_ILLEGAL_SRC_Y_BASE |
0138 SCALER_INT_EN_ILLEGAL_SRC_COLOR |
0139 SCALER_INT_EN_FRAME_END;
0140 scaler_write(val, SCALER_INT_EN);
0141 }
0142
0143 static inline void scaler_set_src_fmt(struct scaler_context *scaler,
0144 u32 src_fmt, u32 tile)
0145 {
0146 u32 val;
0147
0148 val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
0149 scaler_write(val, SCALER_SRC_CFG);
0150 }
0151
0152 static inline void scaler_set_src_base(struct scaler_context *scaler,
0153 struct exynos_drm_ipp_buffer *src_buf)
0154 {
0155 static unsigned int bases[] = {
0156 SCALER_SRC_Y_BASE,
0157 SCALER_SRC_CB_BASE,
0158 SCALER_SRC_CR_BASE,
0159 };
0160 int i;
0161
0162 for (i = 0; i < src_buf->format->num_planes; ++i)
0163 scaler_write(src_buf->dma_addr[i], bases[i]);
0164 }
0165
0166 static inline void scaler_set_src_span(struct scaler_context *scaler,
0167 struct exynos_drm_ipp_buffer *src_buf)
0168 {
0169 u32 val;
0170
0171 val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] /
0172 src_buf->format->cpp[0]);
0173
0174 if (src_buf->format->num_planes > 1)
0175 val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]);
0176
0177 scaler_write(val, SCALER_SRC_SPAN);
0178 }
0179
0180 static inline void scaler_set_src_luma_chroma_pos(struct scaler_context *scaler,
0181 struct drm_exynos_ipp_task_rect *src_pos,
0182 const struct scaler_format *fmt)
0183 {
0184 u32 val;
0185
0186 val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
0187 val |= SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2);
0188 scaler_write(val, SCALER_SRC_Y_POS);
0189 val = SCALER_SRC_C_POS_SET_CH_POS(
0190 (src_pos->x * fmt->chroma_tile_w / 16) << 2);
0191 val |= SCALER_SRC_C_POS_SET_CV_POS(
0192 (src_pos->y * fmt->chroma_tile_h / 16) << 2);
0193 scaler_write(val, SCALER_SRC_C_POS);
0194 }
0195
0196 static inline void scaler_set_src_wh(struct scaler_context *scaler,
0197 struct drm_exynos_ipp_task_rect *src_pos)
0198 {
0199 u32 val;
0200
0201 val = SCALER_SRC_WH_SET_WIDTH(src_pos->w);
0202 val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h);
0203 scaler_write(val, SCALER_SRC_WH);
0204 }
0205
0206 static inline void scaler_set_dst_fmt(struct scaler_context *scaler,
0207 u32 dst_fmt)
0208 {
0209 u32 val;
0210
0211 val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt);
0212 scaler_write(val, SCALER_DST_CFG);
0213 }
0214
0215 static inline void scaler_set_dst_base(struct scaler_context *scaler,
0216 struct exynos_drm_ipp_buffer *dst_buf)
0217 {
0218 static unsigned int bases[] = {
0219 SCALER_DST_Y_BASE,
0220 SCALER_DST_CB_BASE,
0221 SCALER_DST_CR_BASE,
0222 };
0223 int i;
0224
0225 for (i = 0; i < dst_buf->format->num_planes; ++i)
0226 scaler_write(dst_buf->dma_addr[i], bases[i]);
0227 }
0228
0229 static inline void scaler_set_dst_span(struct scaler_context *scaler,
0230 struct exynos_drm_ipp_buffer *dst_buf)
0231 {
0232 u32 val;
0233
0234 val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] /
0235 dst_buf->format->cpp[0]);
0236
0237 if (dst_buf->format->num_planes > 1)
0238 val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]);
0239
0240 scaler_write(val, SCALER_DST_SPAN);
0241 }
0242
0243 static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler,
0244 struct drm_exynos_ipp_task_rect *dst_pos)
0245 {
0246 u32 val;
0247
0248 val = SCALER_DST_WH_SET_WIDTH(dst_pos->w);
0249 val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h);
0250 scaler_write(val, SCALER_DST_WH);
0251 }
0252
0253 static inline void scaler_set_dst_wh(struct scaler_context *scaler,
0254 struct drm_exynos_ipp_task_rect *dst_pos)
0255 {
0256 u32 val;
0257
0258 val = SCALER_DST_POS_SET_H_POS(dst_pos->x);
0259 val |= SCALER_DST_POS_SET_V_POS(dst_pos->y);
0260 scaler_write(val, SCALER_DST_POS);
0261 }
0262
0263 static inline void scaler_set_hv_ratio(struct scaler_context *scaler,
0264 unsigned int rotation,
0265 struct drm_exynos_ipp_task_rect *src_pos,
0266 struct drm_exynos_ipp_task_rect *dst_pos)
0267 {
0268 u32 val, h_ratio, v_ratio;
0269
0270 if (drm_rotation_90_or_270(rotation)) {
0271 h_ratio = (src_pos->h << 16) / dst_pos->w;
0272 v_ratio = (src_pos->w << 16) / dst_pos->h;
0273 } else {
0274 h_ratio = (src_pos->w << 16) / dst_pos->w;
0275 v_ratio = (src_pos->h << 16) / dst_pos->h;
0276 }
0277
0278 val = SCALER_H_RATIO_SET(h_ratio);
0279 scaler_write(val, SCALER_H_RATIO);
0280
0281 val = SCALER_V_RATIO_SET(v_ratio);
0282 scaler_write(val, SCALER_V_RATIO);
0283 }
0284
0285 static inline void scaler_set_rotation(struct scaler_context *scaler,
0286 unsigned int rotation)
0287 {
0288 u32 val = 0;
0289
0290 if (rotation & DRM_MODE_ROTATE_90)
0291 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90);
0292 else if (rotation & DRM_MODE_ROTATE_180)
0293 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180);
0294 else if (rotation & DRM_MODE_ROTATE_270)
0295 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270);
0296 if (rotation & DRM_MODE_REFLECT_X)
0297 val |= SCALER_ROT_CFG_FLIP_X_EN;
0298 if (rotation & DRM_MODE_REFLECT_Y)
0299 val |= SCALER_ROT_CFG_FLIP_Y_EN;
0300 scaler_write(val, SCALER_ROT_CFG);
0301 }
0302
0303 static inline void scaler_set_csc(struct scaler_context *scaler,
0304 const struct drm_format_info *fmt)
0305 {
0306 static const u32 csc_mtx[2][3][3] = {
0307 {
0308 {0x254, 0x000, 0x331},
0309 {0x254, 0xf38, 0xe60},
0310 {0x254, 0x409, 0x000},
0311 },
0312 {
0313 {0x084, 0x102, 0x032},
0314 {0xfb4, 0xf6b, 0x0e1},
0315 {0x0e1, 0xf44, 0xfdc},
0316 },
0317 };
0318 int i, j, dir;
0319
0320 switch (fmt->format) {
0321 case DRM_FORMAT_RGB565:
0322 case DRM_FORMAT_XRGB1555:
0323 case DRM_FORMAT_ARGB1555:
0324 case DRM_FORMAT_XRGB4444:
0325 case DRM_FORMAT_ARGB4444:
0326 case DRM_FORMAT_XRGB8888:
0327 case DRM_FORMAT_ARGB8888:
0328 case DRM_FORMAT_RGBX8888:
0329 case DRM_FORMAT_RGBA8888:
0330 dir = 1;
0331 break;
0332 default:
0333 dir = 0;
0334 }
0335
0336 for (i = 0; i < 3; i++)
0337 for (j = 0; j < 3; j++)
0338 scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i));
0339 }
0340
0341 static inline void scaler_set_timer(struct scaler_context *scaler,
0342 unsigned int timer, unsigned int divider)
0343 {
0344 u32 val;
0345
0346 val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE;
0347 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer);
0348 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider);
0349 scaler_write(val, SCALER_TIMEOUT_CTRL);
0350 }
0351
0352 static inline void scaler_start_hw(struct scaler_context *scaler)
0353 {
0354 scaler_write(SCALER_CFG_START_CMD, SCALER_CFG);
0355 }
0356
0357 static int scaler_commit(struct exynos_drm_ipp *ipp,
0358 struct exynos_drm_ipp_task *task)
0359 {
0360 struct scaler_context *scaler =
0361 container_of(ipp, struct scaler_context, ipp);
0362
0363 struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect;
0364 struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect;
0365 const struct scaler_format *src_fmt, *dst_fmt;
0366 int ret = 0;
0367
0368 src_fmt = scaler_get_format(task->src.buf.fourcc);
0369 dst_fmt = scaler_get_format(task->dst.buf.fourcc);
0370
0371 ret = pm_runtime_resume_and_get(scaler->dev);
0372 if (ret < 0)
0373 return ret;
0374
0375 if (scaler_reset(scaler))
0376 return -EIO;
0377
0378 scaler->task = task;
0379
0380 scaler_set_src_fmt(
0381 scaler, src_fmt->internal_fmt, task->src.buf.modifier != 0);
0382 scaler_set_src_base(scaler, &task->src);
0383 scaler_set_src_span(scaler, &task->src);
0384 scaler_set_src_luma_chroma_pos(scaler, src_pos, src_fmt);
0385 scaler_set_src_wh(scaler, src_pos);
0386
0387 scaler_set_dst_fmt(scaler, dst_fmt->internal_fmt);
0388 scaler_set_dst_base(scaler, &task->dst);
0389 scaler_set_dst_span(scaler, &task->dst);
0390 scaler_set_dst_luma_pos(scaler, dst_pos);
0391 scaler_set_dst_wh(scaler, dst_pos);
0392
0393 scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos);
0394 scaler_set_rotation(scaler, task->transform.rotation);
0395
0396 scaler_set_csc(scaler, task->src.format);
0397
0398 scaler_set_timer(scaler, 0xffff, 0xf);
0399
0400 scaler_enable_int(scaler);
0401 scaler_start_hw(scaler);
0402
0403 return 0;
0404 }
0405
0406 static struct exynos_drm_ipp_funcs ipp_funcs = {
0407 .commit = scaler_commit,
0408 };
0409
0410 static inline void scaler_disable_int(struct scaler_context *scaler)
0411 {
0412 scaler_write(0, SCALER_INT_EN);
0413 }
0414
0415 static inline u32 scaler_get_int_status(struct scaler_context *scaler)
0416 {
0417 u32 val = scaler_read(SCALER_INT_STATUS);
0418
0419 scaler_write(val, SCALER_INT_STATUS);
0420
0421 return val;
0422 }
0423
0424 static inline int scaler_task_done(u32 val)
0425 {
0426 return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL;
0427 }
0428
0429 static irqreturn_t scaler_irq_handler(int irq, void *arg)
0430 {
0431 struct scaler_context *scaler = arg;
0432
0433 u32 val = scaler_get_int_status(scaler);
0434
0435 scaler_disable_int(scaler);
0436
0437 if (scaler->task) {
0438 struct exynos_drm_ipp_task *task = scaler->task;
0439
0440 scaler->task = NULL;
0441 pm_runtime_mark_last_busy(scaler->dev);
0442 pm_runtime_put_autosuspend(scaler->dev);
0443 exynos_drm_ipp_task_done(task, scaler_task_done(val));
0444 }
0445
0446 return IRQ_HANDLED;
0447 }
0448
0449 static int scaler_bind(struct device *dev, struct device *master, void *data)
0450 {
0451 struct scaler_context *scaler = dev_get_drvdata(dev);
0452 struct drm_device *drm_dev = data;
0453 struct exynos_drm_ipp *ipp = &scaler->ipp;
0454
0455 scaler->drm_dev = drm_dev;
0456 ipp->drm_dev = drm_dev;
0457 exynos_drm_register_dma(drm_dev, dev, &scaler->dma_priv);
0458
0459 exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
0460 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
0461 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
0462 scaler->scaler_data->formats,
0463 scaler->scaler_data->num_formats, "scaler");
0464
0465 dev_info(dev, "The exynos scaler has been probed successfully\n");
0466
0467 return 0;
0468 }
0469
0470 static void scaler_unbind(struct device *dev, struct device *master,
0471 void *data)
0472 {
0473 struct scaler_context *scaler = dev_get_drvdata(dev);
0474 struct exynos_drm_ipp *ipp = &scaler->ipp;
0475
0476 exynos_drm_ipp_unregister(dev, ipp);
0477 exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev,
0478 &scaler->dma_priv);
0479 }
0480
0481 static const struct component_ops scaler_component_ops = {
0482 .bind = scaler_bind,
0483 .unbind = scaler_unbind,
0484 };
0485
0486 static int scaler_probe(struct platform_device *pdev)
0487 {
0488 struct device *dev = &pdev->dev;
0489 struct scaler_context *scaler;
0490 int irq;
0491 int ret, i;
0492
0493 scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL);
0494 if (!scaler)
0495 return -ENOMEM;
0496
0497 scaler->scaler_data =
0498 (struct scaler_data *)of_device_get_match_data(dev);
0499
0500 scaler->dev = dev;
0501 scaler->regs = devm_platform_ioremap_resource(pdev, 0);
0502 if (IS_ERR(scaler->regs))
0503 return PTR_ERR(scaler->regs);
0504
0505 irq = platform_get_irq(pdev, 0);
0506 if (irq < 0)
0507 return irq;
0508
0509 ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler,
0510 IRQF_ONESHOT, "drm_scaler", scaler);
0511 if (ret < 0) {
0512 dev_err(dev, "failed to request irq\n");
0513 return ret;
0514 }
0515
0516 for (i = 0; i < scaler->scaler_data->num_clk; ++i) {
0517 scaler->clock[i] = devm_clk_get(dev,
0518 scaler->scaler_data->clk_name[i]);
0519 if (IS_ERR(scaler->clock[i])) {
0520 dev_err(dev, "failed to get clock\n");
0521 return PTR_ERR(scaler->clock[i]);
0522 }
0523 }
0524
0525 pm_runtime_use_autosuspend(dev);
0526 pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY);
0527 pm_runtime_enable(dev);
0528 platform_set_drvdata(pdev, scaler);
0529
0530 ret = component_add(dev, &scaler_component_ops);
0531 if (ret)
0532 goto err_ippdrv_register;
0533
0534 return 0;
0535
0536 err_ippdrv_register:
0537 pm_runtime_dont_use_autosuspend(dev);
0538 pm_runtime_disable(dev);
0539 return ret;
0540 }
0541
0542 static int scaler_remove(struct platform_device *pdev)
0543 {
0544 struct device *dev = &pdev->dev;
0545
0546 component_del(dev, &scaler_component_ops);
0547 pm_runtime_dont_use_autosuspend(dev);
0548 pm_runtime_disable(dev);
0549
0550 return 0;
0551 }
0552
0553 #ifdef CONFIG_PM
0554
0555 static int clk_disable_unprepare_wrapper(struct clk *clk)
0556 {
0557 clk_disable_unprepare(clk);
0558
0559 return 0;
0560 }
0561
0562 static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable)
0563 {
0564 int (*clk_fun)(struct clk *clk), i;
0565
0566 clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper;
0567
0568 for (i = 0; i < scaler->scaler_data->num_clk; ++i)
0569 clk_fun(scaler->clock[i]);
0570
0571 return 0;
0572 }
0573
0574 static int scaler_runtime_suspend(struct device *dev)
0575 {
0576 struct scaler_context *scaler = dev_get_drvdata(dev);
0577
0578 return scaler_clk_ctrl(scaler, false);
0579 }
0580
0581 static int scaler_runtime_resume(struct device *dev)
0582 {
0583 struct scaler_context *scaler = dev_get_drvdata(dev);
0584
0585 return scaler_clk_ctrl(scaler, true);
0586 }
0587 #endif
0588
0589 static const struct dev_pm_ops scaler_pm_ops = {
0590 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0591 pm_runtime_force_resume)
0592 SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL)
0593 };
0594
0595 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = {
0596 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
0597 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
0598 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
0599 .v = { 65536 * 1 / 4, 65536 * 16 }) },
0600 };
0601
0602 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = {
0603 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
0604 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) },
0605 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
0606 .v = { 65536 * 1 / 4, 65536 * 16 }) },
0607 };
0608
0609 static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = {
0610 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
0611 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
0612 .v = { 65536 * 1 / 4, 65536 * 16 }) },
0613 };
0614
0615 static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
0616 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
0617 { IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
0618 { IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})},
0619 { }
0620 };
0621
0622 #define IPP_SRCDST_TILE_FORMAT(f, l) \
0623 IPP_SRCDST_MFORMAT(f, DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, (l))
0624
0625 static const struct exynos_drm_ipp_formats exynos5420_formats[] = {
0626
0627 { IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) },
0628
0629
0630 { IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) },
0631
0632
0633 { IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) },
0634
0635
0636 { IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) },
0637
0638
0639 { IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) },
0640
0641
0642 { IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) },
0643
0644
0645 { IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) },
0646
0647
0648 { IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) },
0649
0650
0651 { IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) },
0652
0653
0654 { IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) },
0655
0656
0657 { IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) },
0658
0659
0660 { IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) },
0661
0662
0663 { IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) },
0664
0665
0666 { IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) },
0667
0668
0669 { IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) },
0670
0671
0672 { IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) },
0673
0674
0675 { IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) },
0676
0677
0678 { IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) },
0679
0680
0681 { IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) },
0682
0683
0684 { IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) },
0685
0686
0687 { IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) },
0688
0689
0690 { IPP_SRCDST_TILE_FORMAT(NV21, scaler_5420_tile_limits) },
0691
0692
0693 { IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) },
0694
0695
0696 { IPP_SRCDST_TILE_FORMAT(YUV420, scaler_5420_tile_limits) },
0697
0698
0699 { IPP_SRCDST_TILE_FORMAT(YUYV, scaler_5420_tile_limits) },
0700 };
0701
0702 static const struct scaler_data exynos5420_data = {
0703 .clk_name = {"mscl"},
0704 .num_clk = 1,
0705 .formats = exynos5420_formats,
0706 .num_formats = ARRAY_SIZE(exynos5420_formats),
0707 };
0708
0709 static const struct scaler_data exynos5433_data = {
0710 .clk_name = {"pclk", "aclk", "aclk_xiu"},
0711 .num_clk = 3,
0712 .formats = exynos5420_formats,
0713 .num_formats = ARRAY_SIZE(exynos5420_formats),
0714 };
0715
0716 static const struct of_device_id exynos_scaler_match[] = {
0717 {
0718 .compatible = "samsung,exynos5420-scaler",
0719 .data = &exynos5420_data,
0720 }, {
0721 .compatible = "samsung,exynos5433-scaler",
0722 .data = &exynos5433_data,
0723 }, {
0724 },
0725 };
0726 MODULE_DEVICE_TABLE(of, exynos_scaler_match);
0727
0728 struct platform_driver scaler_driver = {
0729 .probe = scaler_probe,
0730 .remove = scaler_remove,
0731 .driver = {
0732 .name = "exynos-scaler",
0733 .owner = THIS_MODULE,
0734 .pm = &scaler_pm_ops,
0735 .of_match_table = exynos_scaler_match,
0736 },
0737 };
