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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* exynos_drm_fimd.c
0003  *
0004  * Copyright (C) 2011 Samsung Electronics Co.Ltd
0005  * Authors:
0006  *  Joonyoung Shim <jy0922.shim@samsung.com>
0007  *  Inki Dae <inki.dae@samsung.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/component.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/regmap.h>
0019 
0020 #include <video/of_display_timing.h>
0021 #include <video/of_videomode.h>
0022 #include <video/samsung_fimd.h>
0023 
0024 #include <drm/drm_blend.h>
0025 #include <drm/drm_fourcc.h>
0026 #include <drm/drm_framebuffer.h>
0027 #include <drm/drm_vblank.h>
0028 #include <drm/exynos_drm.h>
0029 
0030 #include "exynos_drm_crtc.h"
0031 #include "exynos_drm_drv.h"
0032 #include "exynos_drm_fb.h"
0033 #include "exynos_drm_plane.h"
0034 
0035 /*
0036  * FIMD stands for Fully Interactive Mobile Display and
0037  * as a display controller, it transfers contents drawn on memory
0038  * to a LCD Panel through Display Interfaces such as RGB or
0039  * CPU Interface.
0040  */
0041 
0042 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
0043 
0044 /* position control register for hardware window 0, 2 ~ 4.*/
0045 #define VIDOSD_A(win)       (VIDOSD_BASE + 0x00 + (win) * 16)
0046 #define VIDOSD_B(win)       (VIDOSD_BASE + 0x04 + (win) * 16)
0047 /*
0048  * size control register for hardware windows 0 and alpha control register
0049  * for hardware windows 1 ~ 4
0050  */
0051 #define VIDOSD_C(win)       (VIDOSD_BASE + 0x08 + (win) * 16)
0052 /* size control register for hardware windows 1 ~ 2. */
0053 #define VIDOSD_D(win)       (VIDOSD_BASE + 0x0C + (win) * 16)
0054 
0055 #define VIDWnALPHA0(win)    (VIDW_ALPHA + 0x00 + (win) * 8)
0056 #define VIDWnALPHA1(win)    (VIDW_ALPHA + 0x04 + (win) * 8)
0057 
0058 #define VIDWx_BUF_START(win, buf)   (VIDW_BUF_START(buf) + (win) * 8)
0059 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
0060 #define VIDWx_BUF_END(win, buf)     (VIDW_BUF_END(buf) + (win) * 8)
0061 #define VIDWx_BUF_SIZE(win, buf)    (VIDW_BUF_SIZE(buf) + (win) * 4)
0062 
0063 /* color key control register for hardware window 1 ~ 4. */
0064 #define WKEYCON0_BASE(x)        ((WKEYCON0 + 0x140) + ((x - 1) * 8))
0065 /* color key value register for hardware window 1 ~ 4. */
0066 #define WKEYCON1_BASE(x)        ((WKEYCON1 + 0x140) + ((x - 1) * 8))
0067 
0068 /* I80 trigger control register */
0069 #define TRIGCON             0x1A4
0070 #define TRGMODE_ENABLE          (1 << 0)
0071 #define SWTRGCMD_ENABLE         (1 << 1)
0072 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
0073 #define HWTRGEN_ENABLE          (1 << 3)
0074 #define HWTRGMASK_ENABLE        (1 << 4)
0075 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
0076 #define HWTRIGEN_PER_ENABLE     (1 << 31)
0077 
0078 /* display mode change control register except exynos4 */
0079 #define VIDOUT_CON          0x000
0080 #define VIDOUT_CON_F_I80_LDI0       (0x2 << 8)
0081 
0082 /* I80 interface control for main LDI register */
0083 #define I80IFCONFAx(x)          (0x1B0 + (x) * 4)
0084 #define I80IFCONFBx(x)          (0x1B8 + (x) * 4)
0085 #define LCD_CS_SETUP(x)         ((x) << 16)
0086 #define LCD_WR_SETUP(x)         ((x) << 12)
0087 #define LCD_WR_ACTIVE(x)        ((x) << 8)
0088 #define LCD_WR_HOLD(x)          ((x) << 4)
0089 #define I80IFEN_ENABLE          (1 << 0)
0090 
0091 /* FIMD has totally five hardware windows. */
0092 #define WINDOWS_NR  5
0093 
0094 /* HW trigger flag on i80 panel. */
0095 #define I80_HW_TRG     (1 << 1)
0096 
0097 struct fimd_driver_data {
0098     unsigned int timing_base;
0099     unsigned int lcdblk_offset;
0100     unsigned int lcdblk_vt_shift;
0101     unsigned int lcdblk_bypass_shift;
0102     unsigned int lcdblk_mic_bypass_shift;
0103     unsigned int trg_type;
0104 
0105     unsigned int has_shadowcon:1;
0106     unsigned int has_clksel:1;
0107     unsigned int has_limited_fmt:1;
0108     unsigned int has_vidoutcon:1;
0109     unsigned int has_vtsel:1;
0110     unsigned int has_mic_bypass:1;
0111     unsigned int has_dp_clk:1;
0112     unsigned int has_hw_trigger:1;
0113     unsigned int has_trigger_per_te:1;
0114     unsigned int has_bgr_support:1;
0115 };
0116 
0117 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
0118     .timing_base = 0x0,
0119     .has_clksel = 1,
0120     .has_limited_fmt = 1,
0121 };
0122 
0123 static struct fimd_driver_data s5pv210_fimd_driver_data = {
0124     .timing_base = 0x0,
0125     .has_shadowcon = 1,
0126     .has_clksel = 1,
0127 };
0128 
0129 static struct fimd_driver_data exynos3_fimd_driver_data = {
0130     .timing_base = 0x20000,
0131     .lcdblk_offset = 0x210,
0132     .lcdblk_bypass_shift = 1,
0133     .has_shadowcon = 1,
0134     .has_vidoutcon = 1,
0135 };
0136 
0137 static struct fimd_driver_data exynos4_fimd_driver_data = {
0138     .timing_base = 0x0,
0139     .lcdblk_offset = 0x210,
0140     .lcdblk_vt_shift = 10,
0141     .lcdblk_bypass_shift = 1,
0142     .has_shadowcon = 1,
0143     .has_vtsel = 1,
0144     .has_bgr_support = 1,
0145 };
0146 
0147 static struct fimd_driver_data exynos5_fimd_driver_data = {
0148     .timing_base = 0x20000,
0149     .lcdblk_offset = 0x214,
0150     .lcdblk_vt_shift = 24,
0151     .lcdblk_bypass_shift = 15,
0152     .has_shadowcon = 1,
0153     .has_vidoutcon = 1,
0154     .has_vtsel = 1,
0155     .has_dp_clk = 1,
0156     .has_bgr_support = 1,
0157 };
0158 
0159 static struct fimd_driver_data exynos5420_fimd_driver_data = {
0160     .timing_base = 0x20000,
0161     .lcdblk_offset = 0x214,
0162     .lcdblk_vt_shift = 24,
0163     .lcdblk_bypass_shift = 15,
0164     .lcdblk_mic_bypass_shift = 11,
0165     .has_shadowcon = 1,
0166     .has_vidoutcon = 1,
0167     .has_vtsel = 1,
0168     .has_mic_bypass = 1,
0169     .has_dp_clk = 1,
0170     .has_bgr_support = 1,
0171 };
0172 
0173 struct fimd_context {
0174     struct device           *dev;
0175     struct drm_device       *drm_dev;
0176     void                *dma_priv;
0177     struct exynos_drm_crtc      *crtc;
0178     struct exynos_drm_plane     planes[WINDOWS_NR];
0179     struct exynos_drm_plane_config  configs[WINDOWS_NR];
0180     struct clk          *bus_clk;
0181     struct clk          *lcd_clk;
0182     void __iomem            *regs;
0183     struct regmap           *sysreg;
0184     unsigned long           irq_flags;
0185     u32             vidcon0;
0186     u32             vidcon1;
0187     u32             vidout_con;
0188     u32             i80ifcon;
0189     bool                i80_if;
0190     bool                suspended;
0191     wait_queue_head_t       wait_vsync_queue;
0192     atomic_t            wait_vsync_event;
0193     atomic_t            win_updated;
0194     atomic_t            triggering;
0195     u32             clkdiv;
0196 
0197     const struct fimd_driver_data *driver_data;
0198     struct drm_encoder *encoder;
0199     struct exynos_drm_clk       dp_clk;
0200 };
0201 
0202 static const struct of_device_id fimd_driver_dt_match[] = {
0203     { .compatible = "samsung,s3c6400-fimd",
0204       .data = &s3c64xx_fimd_driver_data },
0205     { .compatible = "samsung,s5pv210-fimd",
0206       .data = &s5pv210_fimd_driver_data },
0207     { .compatible = "samsung,exynos3250-fimd",
0208       .data = &exynos3_fimd_driver_data },
0209     { .compatible = "samsung,exynos4210-fimd",
0210       .data = &exynos4_fimd_driver_data },
0211     { .compatible = "samsung,exynos5250-fimd",
0212       .data = &exynos5_fimd_driver_data },
0213     { .compatible = "samsung,exynos5420-fimd",
0214       .data = &exynos5420_fimd_driver_data },
0215     {},
0216 };
0217 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
0218 
0219 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
0220     DRM_PLANE_TYPE_PRIMARY,
0221     DRM_PLANE_TYPE_OVERLAY,
0222     DRM_PLANE_TYPE_OVERLAY,
0223     DRM_PLANE_TYPE_OVERLAY,
0224     DRM_PLANE_TYPE_CURSOR,
0225 };
0226 
0227 static const uint32_t fimd_formats[] = {
0228     DRM_FORMAT_C8,
0229     DRM_FORMAT_XRGB1555,
0230     DRM_FORMAT_RGB565,
0231     DRM_FORMAT_XRGB8888,
0232     DRM_FORMAT_ARGB8888,
0233 };
0234 
0235 static const uint32_t fimd_extended_formats[] = {
0236     DRM_FORMAT_C8,
0237     DRM_FORMAT_XRGB1555,
0238     DRM_FORMAT_XBGR1555,
0239     DRM_FORMAT_RGB565,
0240     DRM_FORMAT_BGR565,
0241     DRM_FORMAT_XRGB8888,
0242     DRM_FORMAT_XBGR8888,
0243     DRM_FORMAT_ARGB8888,
0244     DRM_FORMAT_ABGR8888,
0245 };
0246 
0247 static const unsigned int capabilities[WINDOWS_NR] = {
0248     0,
0249     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0250     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0251     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0252     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0253 };
0254 
0255 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
0256                  u32 val)
0257 {
0258     val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
0259     writel(val, ctx->regs + reg);
0260 }
0261 
0262 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
0263 {
0264     struct fimd_context *ctx = crtc->ctx;
0265     u32 val;
0266 
0267     if (ctx->suspended)
0268         return -EPERM;
0269 
0270     if (!test_and_set_bit(0, &ctx->irq_flags)) {
0271         val = readl(ctx->regs + VIDINTCON0);
0272 
0273         val |= VIDINTCON0_INT_ENABLE;
0274 
0275         if (ctx->i80_if) {
0276             val |= VIDINTCON0_INT_I80IFDONE;
0277             val |= VIDINTCON0_INT_SYSMAINCON;
0278             val &= ~VIDINTCON0_INT_SYSSUBCON;
0279         } else {
0280             val |= VIDINTCON0_INT_FRAME;
0281 
0282             val &= ~VIDINTCON0_FRAMESEL0_MASK;
0283             val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
0284             val &= ~VIDINTCON0_FRAMESEL1_MASK;
0285             val |= VIDINTCON0_FRAMESEL1_NONE;
0286         }
0287 
0288         writel(val, ctx->regs + VIDINTCON0);
0289     }
0290 
0291     return 0;
0292 }
0293 
0294 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
0295 {
0296     struct fimd_context *ctx = crtc->ctx;
0297     u32 val;
0298 
0299     if (ctx->suspended)
0300         return;
0301 
0302     if (test_and_clear_bit(0, &ctx->irq_flags)) {
0303         val = readl(ctx->regs + VIDINTCON0);
0304 
0305         val &= ~VIDINTCON0_INT_ENABLE;
0306 
0307         if (ctx->i80_if) {
0308             val &= ~VIDINTCON0_INT_I80IFDONE;
0309             val &= ~VIDINTCON0_INT_SYSMAINCON;
0310             val &= ~VIDINTCON0_INT_SYSSUBCON;
0311         } else
0312             val &= ~VIDINTCON0_INT_FRAME;
0313 
0314         writel(val, ctx->regs + VIDINTCON0);
0315     }
0316 }
0317 
0318 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
0319 {
0320     struct fimd_context *ctx = crtc->ctx;
0321 
0322     if (ctx->suspended)
0323         return;
0324 
0325     atomic_set(&ctx->wait_vsync_event, 1);
0326 
0327     /*
0328      * wait for FIMD to signal VSYNC interrupt or return after
0329      * timeout which is set to 50ms (refresh rate of 20).
0330      */
0331     if (!wait_event_timeout(ctx->wait_vsync_queue,
0332                 !atomic_read(&ctx->wait_vsync_event),
0333                 HZ/20))
0334         DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
0335 }
0336 
0337 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
0338                     bool enable)
0339 {
0340     u32 val = readl(ctx->regs + WINCON(win));
0341 
0342     if (enable)
0343         val |= WINCONx_ENWIN;
0344     else
0345         val &= ~WINCONx_ENWIN;
0346 
0347     writel(val, ctx->regs + WINCON(win));
0348 }
0349 
0350 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
0351                         unsigned int win,
0352                         bool enable)
0353 {
0354     u32 val = readl(ctx->regs + SHADOWCON);
0355 
0356     if (enable)
0357         val |= SHADOWCON_CHx_ENABLE(win);
0358     else
0359         val &= ~SHADOWCON_CHx_ENABLE(win);
0360 
0361     writel(val, ctx->regs + SHADOWCON);
0362 }
0363 
0364 static int fimd_clear_channels(struct exynos_drm_crtc *crtc)
0365 {
0366     struct fimd_context *ctx = crtc->ctx;
0367     unsigned int win, ch_enabled = 0;
0368     int ret;
0369 
0370     /* Hardware is in unknown state, so ensure it gets enabled properly */
0371     ret = pm_runtime_resume_and_get(ctx->dev);
0372     if (ret < 0) {
0373         dev_err(ctx->dev, "failed to enable FIMD device.\n");
0374         return ret;
0375     }
0376 
0377     clk_prepare_enable(ctx->bus_clk);
0378     clk_prepare_enable(ctx->lcd_clk);
0379 
0380     /* Check if any channel is enabled. */
0381     for (win = 0; win < WINDOWS_NR; win++) {
0382         u32 val = readl(ctx->regs + WINCON(win));
0383 
0384         if (val & WINCONx_ENWIN) {
0385             fimd_enable_video_output(ctx, win, false);
0386 
0387             if (ctx->driver_data->has_shadowcon)
0388                 fimd_enable_shadow_channel_path(ctx, win,
0389                                 false);
0390 
0391             ch_enabled = 1;
0392         }
0393     }
0394 
0395     /* Wait for vsync, as disable channel takes effect at next vsync */
0396     if (ch_enabled) {
0397         ctx->suspended = false;
0398 
0399         fimd_enable_vblank(ctx->crtc);
0400         fimd_wait_for_vblank(ctx->crtc);
0401         fimd_disable_vblank(ctx->crtc);
0402 
0403         ctx->suspended = true;
0404     }
0405 
0406     clk_disable_unprepare(ctx->lcd_clk);
0407     clk_disable_unprepare(ctx->bus_clk);
0408 
0409     pm_runtime_put(ctx->dev);
0410 
0411     return 0;
0412 }
0413 
0414 
0415 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
0416         struct drm_crtc_state *state)
0417 {
0418     struct drm_display_mode *mode = &state->adjusted_mode;
0419     struct fimd_context *ctx = crtc->ctx;
0420     unsigned long ideal_clk, lcd_rate;
0421     u32 clkdiv;
0422 
0423     if (mode->clock == 0) {
0424         DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
0425         return -EINVAL;
0426     }
0427 
0428     ideal_clk = mode->clock * 1000;
0429 
0430     if (ctx->i80_if) {
0431         /*
0432          * The frame done interrupt should be occurred prior to the
0433          * next TE signal.
0434          */
0435         ideal_clk *= 2;
0436     }
0437 
0438     lcd_rate = clk_get_rate(ctx->lcd_clk);
0439     if (2 * lcd_rate < ideal_clk) {
0440         DRM_DEV_ERROR(ctx->dev,
0441                   "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
0442                   lcd_rate, ideal_clk);
0443         return -EINVAL;
0444     }
0445 
0446     /* Find the clock divider value that gets us closest to ideal_clk */
0447     clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
0448     if (clkdiv >= 0x200) {
0449         DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
0450                   ideal_clk);
0451         return -EINVAL;
0452     }
0453 
0454     ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
0455 
0456     return 0;
0457 }
0458 
0459 static void fimd_setup_trigger(struct fimd_context *ctx)
0460 {
0461     void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
0462     u32 trg_type = ctx->driver_data->trg_type;
0463     u32 val = readl(timing_base + TRIGCON);
0464 
0465     val &= ~(TRGMODE_ENABLE);
0466 
0467     if (trg_type == I80_HW_TRG) {
0468         if (ctx->driver_data->has_hw_trigger)
0469             val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
0470         if (ctx->driver_data->has_trigger_per_te)
0471             val |= HWTRIGEN_PER_ENABLE;
0472     } else {
0473         val |= TRGMODE_ENABLE;
0474     }
0475 
0476     writel(val, timing_base + TRIGCON);
0477 }
0478 
0479 static void fimd_commit(struct exynos_drm_crtc *crtc)
0480 {
0481     struct fimd_context *ctx = crtc->ctx;
0482     struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
0483     const struct fimd_driver_data *driver_data = ctx->driver_data;
0484     void *timing_base = ctx->regs + driver_data->timing_base;
0485     u32 val;
0486 
0487     if (ctx->suspended)
0488         return;
0489 
0490     /* nothing to do if we haven't set the mode yet */
0491     if (mode->htotal == 0 || mode->vtotal == 0)
0492         return;
0493 
0494     if (ctx->i80_if) {
0495         val = ctx->i80ifcon | I80IFEN_ENABLE;
0496         writel(val, timing_base + I80IFCONFAx(0));
0497 
0498         /* disable auto frame rate */
0499         writel(0, timing_base + I80IFCONFBx(0));
0500 
0501         /* set video type selection to I80 interface */
0502         if (driver_data->has_vtsel && ctx->sysreg &&
0503                 regmap_update_bits(ctx->sysreg,
0504                     driver_data->lcdblk_offset,
0505                     0x3 << driver_data->lcdblk_vt_shift,
0506                     0x1 << driver_data->lcdblk_vt_shift)) {
0507             DRM_DEV_ERROR(ctx->dev,
0508                       "Failed to update sysreg for I80 i/f.\n");
0509             return;
0510         }
0511     } else {
0512         int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
0513         u32 vidcon1;
0514 
0515         /* setup polarity values */
0516         vidcon1 = ctx->vidcon1;
0517         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
0518             vidcon1 |= VIDCON1_INV_VSYNC;
0519         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
0520             vidcon1 |= VIDCON1_INV_HSYNC;
0521         writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
0522 
0523         /* setup vertical timing values. */
0524         vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
0525         vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
0526         vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
0527 
0528         val = VIDTCON0_VBPD(vbpd - 1) |
0529             VIDTCON0_VFPD(vfpd - 1) |
0530             VIDTCON0_VSPW(vsync_len - 1);
0531         writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
0532 
0533         /* setup horizontal timing values.  */
0534         hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
0535         hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
0536         hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
0537 
0538         val = VIDTCON1_HBPD(hbpd - 1) |
0539             VIDTCON1_HFPD(hfpd - 1) |
0540             VIDTCON1_HSPW(hsync_len - 1);
0541         writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
0542     }
0543 
0544     if (driver_data->has_vidoutcon)
0545         writel(ctx->vidout_con, timing_base + VIDOUT_CON);
0546 
0547     /* set bypass selection */
0548     if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
0549                 driver_data->lcdblk_offset,
0550                 0x1 << driver_data->lcdblk_bypass_shift,
0551                 0x1 << driver_data->lcdblk_bypass_shift)) {
0552         DRM_DEV_ERROR(ctx->dev,
0553                   "Failed to update sysreg for bypass setting.\n");
0554         return;
0555     }
0556 
0557     /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
0558      * bit should be cleared.
0559      */
0560     if (driver_data->has_mic_bypass && ctx->sysreg &&
0561         regmap_update_bits(ctx->sysreg,
0562                 driver_data->lcdblk_offset,
0563                 0x1 << driver_data->lcdblk_mic_bypass_shift,
0564                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
0565         DRM_DEV_ERROR(ctx->dev,
0566                   "Failed to update sysreg for bypass mic.\n");
0567         return;
0568     }
0569 
0570     /* setup horizontal and vertical display size. */
0571     val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
0572            VIDTCON2_HOZVAL(mode->hdisplay - 1) |
0573            VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
0574            VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
0575     writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
0576 
0577     fimd_setup_trigger(ctx);
0578 
0579     /*
0580      * fields of register with prefix '_F' would be updated
0581      * at vsync(same as dma start)
0582      */
0583     val = ctx->vidcon0;
0584     val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
0585 
0586     if (ctx->driver_data->has_clksel)
0587         val |= VIDCON0_CLKSEL_LCD;
0588 
0589     if (ctx->clkdiv > 1)
0590         val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
0591 
0592     writel(val, ctx->regs + VIDCON0);
0593 }
0594 
0595 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
0596                    unsigned int alpha, unsigned int pixel_alpha)
0597 {
0598     u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
0599     u32 val = 0;
0600 
0601     switch (pixel_alpha) {
0602     case DRM_MODE_BLEND_PIXEL_NONE:
0603     case DRM_MODE_BLEND_COVERAGE:
0604         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
0605         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
0606         break;
0607     case DRM_MODE_BLEND_PREMULTI:
0608     default:
0609         if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
0610             val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
0611             val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
0612         } else {
0613             val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
0614             val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
0615         }
0616         break;
0617     }
0618     fimd_set_bits(ctx, BLENDEQx(win), mask, val);
0619 }
0620 
0621 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
0622                 unsigned int alpha, unsigned int pixel_alpha)
0623 {
0624     u32 win_alpha_l = (alpha >> 8) & 0xf;
0625     u32 win_alpha_h = alpha >> 12;
0626     u32 val = 0;
0627 
0628     switch (pixel_alpha) {
0629     case DRM_MODE_BLEND_PIXEL_NONE:
0630         break;
0631     case DRM_MODE_BLEND_COVERAGE:
0632     case DRM_MODE_BLEND_PREMULTI:
0633     default:
0634         val |= WINCON1_ALPHA_SEL;
0635         val |= WINCON1_BLD_PIX;
0636         val |= WINCON1_ALPHA_MUL;
0637         break;
0638     }
0639     fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
0640 
0641     /* OSD alpha */
0642     val = VIDISD14C_ALPHA0_R(win_alpha_h) |
0643         VIDISD14C_ALPHA0_G(win_alpha_h) |
0644         VIDISD14C_ALPHA0_B(win_alpha_h) |
0645         VIDISD14C_ALPHA1_R(0x0) |
0646         VIDISD14C_ALPHA1_G(0x0) |
0647         VIDISD14C_ALPHA1_B(0x0);
0648     writel(val, ctx->regs + VIDOSD_C(win));
0649 
0650     val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
0651         VIDW_ALPHA_B(win_alpha_l);
0652     writel(val, ctx->regs + VIDWnALPHA0(win));
0653 
0654     val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
0655         VIDW_ALPHA_B(0x0);
0656     writel(val, ctx->regs + VIDWnALPHA1(win));
0657 
0658     fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
0659             BLENDCON_NEW_8BIT_ALPHA_VALUE);
0660 }
0661 
0662 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
0663                 struct drm_framebuffer *fb, int width)
0664 {
0665     struct exynos_drm_plane plane = ctx->planes[win];
0666     struct exynos_drm_plane_state *state =
0667         to_exynos_plane_state(plane.base.state);
0668     uint32_t pixel_format = fb->format->format;
0669     unsigned int alpha = state->base.alpha;
0670     u32 val = WINCONx_ENWIN;
0671     unsigned int pixel_alpha;
0672 
0673     if (fb->format->has_alpha)
0674         pixel_alpha = state->base.pixel_blend_mode;
0675     else
0676         pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
0677 
0678     /*
0679      * In case of s3c64xx, window 0 doesn't support alpha channel.
0680      * So the request format is ARGB8888 then change it to XRGB8888.
0681      */
0682     if (ctx->driver_data->has_limited_fmt && !win) {
0683         if (pixel_format == DRM_FORMAT_ARGB8888)
0684             pixel_format = DRM_FORMAT_XRGB8888;
0685     }
0686 
0687     switch (pixel_format) {
0688     case DRM_FORMAT_C8:
0689         val |= WINCON0_BPPMODE_8BPP_PALETTE;
0690         val |= WINCONx_BURSTLEN_8WORD;
0691         val |= WINCONx_BYTSWP;
0692         break;
0693     case DRM_FORMAT_XRGB1555:
0694     case DRM_FORMAT_XBGR1555:
0695         val |= WINCON0_BPPMODE_16BPP_1555;
0696         val |= WINCONx_HAWSWP;
0697         val |= WINCONx_BURSTLEN_16WORD;
0698         break;
0699     case DRM_FORMAT_RGB565:
0700     case DRM_FORMAT_BGR565:
0701         val |= WINCON0_BPPMODE_16BPP_565;
0702         val |= WINCONx_HAWSWP;
0703         val |= WINCONx_BURSTLEN_16WORD;
0704         break;
0705     case DRM_FORMAT_XRGB8888:
0706     case DRM_FORMAT_XBGR8888:
0707         val |= WINCON0_BPPMODE_24BPP_888;
0708         val |= WINCONx_WSWP;
0709         val |= WINCONx_BURSTLEN_16WORD;
0710         break;
0711     case DRM_FORMAT_ARGB8888:
0712     case DRM_FORMAT_ABGR8888:
0713     default:
0714         val |= WINCON1_BPPMODE_25BPP_A1888;
0715         val |= WINCONx_WSWP;
0716         val |= WINCONx_BURSTLEN_16WORD;
0717         break;
0718     }
0719 
0720     switch (pixel_format) {
0721     case DRM_FORMAT_XBGR1555:
0722     case DRM_FORMAT_XBGR8888:
0723     case DRM_FORMAT_ABGR8888:
0724     case DRM_FORMAT_BGR565:
0725         writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win));
0726         break;
0727     default:
0728         writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win));
0729         break;
0730     }
0731 
0732     /*
0733      * Setting dma-burst to 16Word causes permanent tearing for very small
0734      * buffers, e.g. cursor buffer. Burst Mode switching which based on
0735      * plane size is not recommended as plane size varies alot towards the
0736      * end of the screen and rapid movement causes unstable DMA, but it is
0737      * still better to change dma-burst than displaying garbage.
0738      */
0739 
0740     if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
0741         val &= ~WINCONx_BURSTLEN_MASK;
0742         val |= WINCONx_BURSTLEN_4WORD;
0743     }
0744     fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
0745 
0746     /* hardware window 0 doesn't support alpha channel. */
0747     if (win != 0) {
0748         fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
0749         fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
0750     }
0751 }
0752 
0753 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
0754 {
0755     unsigned int keycon0 = 0, keycon1 = 0;
0756 
0757     keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
0758             WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
0759 
0760     keycon1 = WxKEYCON1_COLVAL(0xffffffff);
0761 
0762     writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
0763     writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
0764 }
0765 
0766 /**
0767  * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync
0768  *
0769  * @ctx: local driver data
0770  * @win: window to protect registers for
0771  * @protect: 1 to protect (disable updates)
0772  */
0773 static void fimd_shadow_protect_win(struct fimd_context *ctx,
0774                     unsigned int win, bool protect)
0775 {
0776     u32 reg, bits, val;
0777 
0778     /*
0779      * SHADOWCON/PRTCON register is used for enabling timing.
0780      *
0781      * for example, once only width value of a register is set,
0782      * if the dma is started then fimd hardware could malfunction so
0783      * with protect window setting, the register fields with prefix '_F'
0784      * wouldn't be updated at vsync also but updated once unprotect window
0785      * is set.
0786      */
0787 
0788     if (ctx->driver_data->has_shadowcon) {
0789         reg = SHADOWCON;
0790         bits = SHADOWCON_WINx_PROTECT(win);
0791     } else {
0792         reg = PRTCON;
0793         bits = PRTCON_PROTECT;
0794     }
0795 
0796     val = readl(ctx->regs + reg);
0797     if (protect)
0798         val |= bits;
0799     else
0800         val &= ~bits;
0801     writel(val, ctx->regs + reg);
0802 }
0803 
0804 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
0805 {
0806     struct fimd_context *ctx = crtc->ctx;
0807     int i;
0808 
0809     if (ctx->suspended)
0810         return;
0811 
0812     for (i = 0; i < WINDOWS_NR; i++)
0813         fimd_shadow_protect_win(ctx, i, true);
0814 }
0815 
0816 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
0817 {
0818     struct fimd_context *ctx = crtc->ctx;
0819     int i;
0820 
0821     if (ctx->suspended)
0822         return;
0823 
0824     for (i = 0; i < WINDOWS_NR; i++)
0825         fimd_shadow_protect_win(ctx, i, false);
0826 
0827     exynos_crtc_handle_event(crtc);
0828 }
0829 
0830 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
0831                   struct exynos_drm_plane *plane)
0832 {
0833     struct exynos_drm_plane_state *state =
0834                 to_exynos_plane_state(plane->base.state);
0835     struct fimd_context *ctx = crtc->ctx;
0836     struct drm_framebuffer *fb = state->base.fb;
0837     dma_addr_t dma_addr;
0838     unsigned long val, size, offset;
0839     unsigned int last_x, last_y, buf_offsize, line_size;
0840     unsigned int win = plane->index;
0841     unsigned int cpp = fb->format->cpp[0];
0842     unsigned int pitch = fb->pitches[0];
0843 
0844     if (ctx->suspended)
0845         return;
0846 
0847     offset = state->src.x * cpp;
0848     offset += state->src.y * pitch;
0849 
0850     /* buffer start address */
0851     dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
0852     val = (unsigned long)dma_addr;
0853     writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
0854 
0855     /* buffer end address */
0856     size = pitch * state->crtc.h;
0857     val = (unsigned long)(dma_addr + size);
0858     writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
0859 
0860     DRM_DEV_DEBUG_KMS(ctx->dev,
0861               "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
0862               (unsigned long)dma_addr, val, size);
0863     DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
0864               state->crtc.w, state->crtc.h);
0865 
0866     /* buffer size */
0867     buf_offsize = pitch - (state->crtc.w * cpp);
0868     line_size = state->crtc.w * cpp;
0869     val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
0870         VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
0871         VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
0872         VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
0873     writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
0874 
0875     /* OSD position */
0876     val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
0877         VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
0878         VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
0879         VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
0880     writel(val, ctx->regs + VIDOSD_A(win));
0881 
0882     last_x = state->crtc.x + state->crtc.w;
0883     if (last_x)
0884         last_x--;
0885     last_y = state->crtc.y + state->crtc.h;
0886     if (last_y)
0887         last_y--;
0888 
0889     val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
0890         VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
0891 
0892     writel(val, ctx->regs + VIDOSD_B(win));
0893 
0894     DRM_DEV_DEBUG_KMS(ctx->dev,
0895               "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
0896               state->crtc.x, state->crtc.y, last_x, last_y);
0897 
0898     /* OSD size */
0899     if (win != 3 && win != 4) {
0900         u32 offset = VIDOSD_D(win);
0901         if (win == 0)
0902             offset = VIDOSD_C(win);
0903         val = state->crtc.w * state->crtc.h;
0904         writel(val, ctx->regs + offset);
0905 
0906         DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
0907                   (unsigned int)val);
0908     }
0909 
0910     fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
0911 
0912     /* hardware window 0 doesn't support color key. */
0913     if (win != 0)
0914         fimd_win_set_colkey(ctx, win);
0915 
0916     fimd_enable_video_output(ctx, win, true);
0917 
0918     if (ctx->driver_data->has_shadowcon)
0919         fimd_enable_shadow_channel_path(ctx, win, true);
0920 
0921     if (ctx->i80_if)
0922         atomic_set(&ctx->win_updated, 1);
0923 }
0924 
0925 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
0926                    struct exynos_drm_plane *plane)
0927 {
0928     struct fimd_context *ctx = crtc->ctx;
0929     unsigned int win = plane->index;
0930 
0931     if (ctx->suspended)
0932         return;
0933 
0934     fimd_enable_video_output(ctx, win, false);
0935 
0936     if (ctx->driver_data->has_shadowcon)
0937         fimd_enable_shadow_channel_path(ctx, win, false);
0938 }
0939 
0940 static void fimd_atomic_enable(struct exynos_drm_crtc *crtc)
0941 {
0942     struct fimd_context *ctx = crtc->ctx;
0943 
0944     if (!ctx->suspended)
0945         return;
0946 
0947     ctx->suspended = false;
0948 
0949     if (pm_runtime_resume_and_get(ctx->dev) < 0) {
0950         dev_warn(ctx->dev, "failed to enable FIMD device.\n");
0951         return;
0952     }
0953 
0954     /* if vblank was enabled status, enable it again. */
0955     if (test_and_clear_bit(0, &ctx->irq_flags))
0956         fimd_enable_vblank(ctx->crtc);
0957 
0958     fimd_commit(ctx->crtc);
0959 }
0960 
0961 static void fimd_atomic_disable(struct exynos_drm_crtc *crtc)
0962 {
0963     struct fimd_context *ctx = crtc->ctx;
0964     int i;
0965 
0966     if (ctx->suspended)
0967         return;
0968 
0969     /*
0970      * We need to make sure that all windows are disabled before we
0971      * suspend that connector. Otherwise we might try to scan from
0972      * a destroyed buffer later.
0973      */
0974     for (i = 0; i < WINDOWS_NR; i++)
0975         fimd_disable_plane(crtc, &ctx->planes[i]);
0976 
0977     fimd_enable_vblank(crtc);
0978     fimd_wait_for_vblank(crtc);
0979     fimd_disable_vblank(crtc);
0980 
0981     writel(0, ctx->regs + VIDCON0);
0982 
0983     pm_runtime_put_sync(ctx->dev);
0984     ctx->suspended = true;
0985 }
0986 
0987 static void fimd_trigger(struct device *dev)
0988 {
0989     struct fimd_context *ctx = dev_get_drvdata(dev);
0990     const struct fimd_driver_data *driver_data = ctx->driver_data;
0991     void *timing_base = ctx->regs + driver_data->timing_base;
0992     u32 reg;
0993 
0994      /*
0995       * Skips triggering if in triggering state, because multiple triggering
0996       * requests can cause panel reset.
0997       */
0998     if (atomic_read(&ctx->triggering))
0999         return;
1000 
1001     /* Enters triggering mode */
1002     atomic_set(&ctx->triggering, 1);
1003 
1004     reg = readl(timing_base + TRIGCON);
1005     reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
1006     writel(reg, timing_base + TRIGCON);
1007 
1008     /*
1009      * Exits triggering mode if vblank is not enabled yet, because when the
1010      * VIDINTCON0 register is not set, it can not exit from triggering mode.
1011      */
1012     if (!test_bit(0, &ctx->irq_flags))
1013         atomic_set(&ctx->triggering, 0);
1014 }
1015 
1016 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
1017 {
1018     struct fimd_context *ctx = crtc->ctx;
1019     u32 trg_type = ctx->driver_data->trg_type;
1020 
1021     /* Checks the crtc is detached already from encoder */
1022     if (!ctx->drm_dev)
1023         return;
1024 
1025     if (trg_type == I80_HW_TRG)
1026         goto out;
1027 
1028     /*
1029      * If there is a page flip request, triggers and handles the page flip
1030      * event so that current fb can be updated into panel GRAM.
1031      */
1032     if (atomic_add_unless(&ctx->win_updated, -1, 0))
1033         fimd_trigger(ctx->dev);
1034 
1035 out:
1036     /* Wakes up vsync event queue */
1037     if (atomic_read(&ctx->wait_vsync_event)) {
1038         atomic_set(&ctx->wait_vsync_event, 0);
1039         wake_up(&ctx->wait_vsync_queue);
1040     }
1041 
1042     if (test_bit(0, &ctx->irq_flags))
1043         drm_crtc_handle_vblank(&ctx->crtc->base);
1044 }
1045 
1046 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
1047 {
1048     struct fimd_context *ctx = container_of(clk, struct fimd_context,
1049                         dp_clk);
1050     u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1051     writel(val, ctx->regs + DP_MIE_CLKCON);
1052 }
1053 
1054 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
1055     .atomic_enable = fimd_atomic_enable,
1056     .atomic_disable = fimd_atomic_disable,
1057     .enable_vblank = fimd_enable_vblank,
1058     .disable_vblank = fimd_disable_vblank,
1059     .atomic_begin = fimd_atomic_begin,
1060     .update_plane = fimd_update_plane,
1061     .disable_plane = fimd_disable_plane,
1062     .atomic_flush = fimd_atomic_flush,
1063     .atomic_check = fimd_atomic_check,
1064     .te_handler = fimd_te_handler,
1065 };
1066 
1067 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1068 {
1069     struct fimd_context *ctx = (struct fimd_context *)dev_id;
1070     u32 val, clear_bit;
1071 
1072     val = readl(ctx->regs + VIDINTCON1);
1073 
1074     clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1075     if (val & clear_bit)
1076         writel(clear_bit, ctx->regs + VIDINTCON1);
1077 
1078     /* check the crtc is detached already from encoder */
1079     if (!ctx->drm_dev)
1080         goto out;
1081 
1082     if (!ctx->i80_if)
1083         drm_crtc_handle_vblank(&ctx->crtc->base);
1084 
1085     if (ctx->i80_if) {
1086         /* Exits triggering mode */
1087         atomic_set(&ctx->triggering, 0);
1088     } else {
1089         /* set wait vsync event to zero and wake up queue. */
1090         if (atomic_read(&ctx->wait_vsync_event)) {
1091             atomic_set(&ctx->wait_vsync_event, 0);
1092             wake_up(&ctx->wait_vsync_queue);
1093         }
1094     }
1095 
1096 out:
1097     return IRQ_HANDLED;
1098 }
1099 
1100 static int fimd_bind(struct device *dev, struct device *master, void *data)
1101 {
1102     struct fimd_context *ctx = dev_get_drvdata(dev);
1103     struct drm_device *drm_dev = data;
1104     struct exynos_drm_plane *exynos_plane;
1105     unsigned int i;
1106     int ret;
1107 
1108     ctx->drm_dev = drm_dev;
1109 
1110     for (i = 0; i < WINDOWS_NR; i++) {
1111         if (ctx->driver_data->has_bgr_support) {
1112             ctx->configs[i].pixel_formats = fimd_extended_formats;
1113             ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats);
1114         } else {
1115             ctx->configs[i].pixel_formats = fimd_formats;
1116             ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1117         }
1118 
1119         ctx->configs[i].zpos = i;
1120         ctx->configs[i].type = fimd_win_types[i];
1121         ctx->configs[i].capabilities = capabilities[i];
1122         ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1123                     &ctx->configs[i]);
1124         if (ret)
1125             return ret;
1126     }
1127 
1128     exynos_plane = &ctx->planes[DEFAULT_WIN];
1129     ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1130             EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1131     if (IS_ERR(ctx->crtc))
1132         return PTR_ERR(ctx->crtc);
1133 
1134     if (ctx->driver_data->has_dp_clk) {
1135         ctx->dp_clk.enable = fimd_dp_clock_enable;
1136         ctx->crtc->pipe_clk = &ctx->dp_clk;
1137     }
1138 
1139     if (ctx->encoder)
1140         exynos_dpi_bind(drm_dev, ctx->encoder);
1141 
1142     if (is_drm_iommu_supported(drm_dev)) {
1143         int ret;
1144 
1145         ret = fimd_clear_channels(ctx->crtc);
1146         if (ret < 0)
1147             return ret;
1148     }
1149 
1150     return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1151 }
1152 
1153 static void fimd_unbind(struct device *dev, struct device *master,
1154             void *data)
1155 {
1156     struct fimd_context *ctx = dev_get_drvdata(dev);
1157 
1158     fimd_atomic_disable(ctx->crtc);
1159 
1160     exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
1161 
1162     if (ctx->encoder)
1163         exynos_dpi_remove(ctx->encoder);
1164 }
1165 
1166 static const struct component_ops fimd_component_ops = {
1167     .bind   = fimd_bind,
1168     .unbind = fimd_unbind,
1169 };
1170 
1171 static int fimd_probe(struct platform_device *pdev)
1172 {
1173     struct device *dev = &pdev->dev;
1174     struct fimd_context *ctx;
1175     struct device_node *i80_if_timings;
1176     int ret;
1177 
1178     if (!dev->of_node)
1179         return -ENODEV;
1180 
1181     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1182     if (!ctx)
1183         return -ENOMEM;
1184 
1185     ctx->dev = dev;
1186     ctx->suspended = true;
1187     ctx->driver_data = of_device_get_match_data(dev);
1188 
1189     if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1190         ctx->vidcon1 |= VIDCON1_INV_VDEN;
1191     if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1192         ctx->vidcon1 |= VIDCON1_INV_VCLK;
1193 
1194     i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1195     if (i80_if_timings) {
1196         u32 val;
1197 
1198         ctx->i80_if = true;
1199 
1200         if (ctx->driver_data->has_vidoutcon)
1201             ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1202         else
1203             ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1204         /*
1205          * The user manual describes that this "DSI_EN" bit is required
1206          * to enable I80 24-bit data interface.
1207          */
1208         ctx->vidcon0 |= VIDCON0_DSI_EN;
1209 
1210         if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1211             val = 0;
1212         ctx->i80ifcon = LCD_CS_SETUP(val);
1213         if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1214             val = 0;
1215         ctx->i80ifcon |= LCD_WR_SETUP(val);
1216         if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1217             val = 1;
1218         ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1219         if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1220             val = 0;
1221         ctx->i80ifcon |= LCD_WR_HOLD(val);
1222     }
1223     of_node_put(i80_if_timings);
1224 
1225     ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1226                             "samsung,sysreg");
1227     if (IS_ERR(ctx->sysreg)) {
1228         dev_warn(dev, "failed to get system register.\n");
1229         ctx->sysreg = NULL;
1230     }
1231 
1232     ctx->bus_clk = devm_clk_get(dev, "fimd");
1233     if (IS_ERR(ctx->bus_clk)) {
1234         dev_err(dev, "failed to get bus clock\n");
1235         return PTR_ERR(ctx->bus_clk);
1236     }
1237 
1238     ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1239     if (IS_ERR(ctx->lcd_clk)) {
1240         dev_err(dev, "failed to get lcd clock\n");
1241         return PTR_ERR(ctx->lcd_clk);
1242     }
1243 
1244     ctx->regs = devm_platform_ioremap_resource(pdev, 0);
1245     if (IS_ERR(ctx->regs))
1246         return PTR_ERR(ctx->regs);
1247 
1248     ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync");
1249     if (ret < 0)
1250         return ret;
1251 
1252     ret = devm_request_irq(dev, ret, fimd_irq_handler, 0, "drm_fimd", ctx);
1253     if (ret) {
1254         dev_err(dev, "irq request failed.\n");
1255         return ret;
1256     }
1257 
1258     init_waitqueue_head(&ctx->wait_vsync_queue);
1259     atomic_set(&ctx->wait_vsync_event, 0);
1260 
1261     platform_set_drvdata(pdev, ctx);
1262 
1263     ctx->encoder = exynos_dpi_probe(dev);
1264     if (IS_ERR(ctx->encoder))
1265         return PTR_ERR(ctx->encoder);
1266 
1267     pm_runtime_enable(dev);
1268 
1269     ret = component_add(dev, &fimd_component_ops);
1270     if (ret)
1271         goto err_disable_pm_runtime;
1272 
1273     return ret;
1274 
1275 err_disable_pm_runtime:
1276     pm_runtime_disable(dev);
1277 
1278     return ret;
1279 }
1280 
1281 static int fimd_remove(struct platform_device *pdev)
1282 {
1283     pm_runtime_disable(&pdev->dev);
1284 
1285     component_del(&pdev->dev, &fimd_component_ops);
1286 
1287     return 0;
1288 }
1289 
1290 #ifdef CONFIG_PM
1291 static int exynos_fimd_suspend(struct device *dev)
1292 {
1293     struct fimd_context *ctx = dev_get_drvdata(dev);
1294 
1295     clk_disable_unprepare(ctx->lcd_clk);
1296     clk_disable_unprepare(ctx->bus_clk);
1297 
1298     return 0;
1299 }
1300 
1301 static int exynos_fimd_resume(struct device *dev)
1302 {
1303     struct fimd_context *ctx = dev_get_drvdata(dev);
1304     int ret;
1305 
1306     ret = clk_prepare_enable(ctx->bus_clk);
1307     if (ret < 0) {
1308         DRM_DEV_ERROR(dev,
1309                   "Failed to prepare_enable the bus clk [%d]\n",
1310                   ret);
1311         return ret;
1312     }
1313 
1314     ret = clk_prepare_enable(ctx->lcd_clk);
1315     if  (ret < 0) {
1316         DRM_DEV_ERROR(dev,
1317                   "Failed to prepare_enable the lcd clk [%d]\n",
1318                   ret);
1319         return ret;
1320     }
1321 
1322     return 0;
1323 }
1324 #endif
1325 
1326 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1327     SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1328     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1329                 pm_runtime_force_resume)
1330 };
1331 
1332 struct platform_driver fimd_driver = {
1333     .probe      = fimd_probe,
1334     .remove     = fimd_remove,
1335     .driver     = {
1336         .name   = "exynos4-fb",
1337         .owner  = THIS_MODULE,
1338         .pm = &exynos_fimd_pm_ops,
1339         .of_match_table = fimd_driver_dt_match,
1340     },
1341 };
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