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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2012 Samsung Electronics Co.Ltd
0004  * Authors:
0005  *  Eunchul Kim <chulspro.kim@samsung.com>
0006  *  Jinyoung Jeon <jy0.jeon@samsung.com>
0007  *  Sangmin Lee <lsmin.lee@samsung.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/component.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/regmap.h>
0018 #include <linux/spinlock.h>
0019 
0020 #include <drm/drm_fourcc.h>
0021 #include <drm/drm_print.h>
0022 #include <drm/exynos_drm.h>
0023 
0024 #include "exynos_drm_drv.h"
0025 #include "exynos_drm_ipp.h"
0026 #include "regs-fimc.h"
0027 
0028 /*
0029  * FIMC stands for Fully Interactive Mobile Camera and
0030  * supports image scaler/rotator and input/output DMA operations.
0031  * input DMA reads image data from the memory.
0032  * output DMA writes image data to memory.
0033  * FIMC supports image rotation and image effect functions.
0034  */
0035 
0036 #define FIMC_MAX_DEVS   4
0037 #define FIMC_MAX_SRC    2
0038 #define FIMC_MAX_DST    32
0039 #define FIMC_SHFACTOR   10
0040 #define FIMC_BUF_STOP   1
0041 #define FIMC_BUF_START  2
0042 #define FIMC_WIDTH_ITU_709  1280
0043 #define FIMC_AUTOSUSPEND_DELAY  2000
0044 
0045 static unsigned int fimc_mask = 0xc;
0046 module_param_named(fimc_devs, fimc_mask, uint, 0644);
0047 MODULE_PARM_DESC(fimc_devs, "Alias mask for assigning FIMC devices to Exynos DRM");
0048 
0049 #define get_fimc_context(dev)   dev_get_drvdata(dev)
0050 
0051 enum {
0052     FIMC_CLK_LCLK,
0053     FIMC_CLK_GATE,
0054     FIMC_CLK_WB_A,
0055     FIMC_CLK_WB_B,
0056     FIMC_CLKS_MAX
0057 };
0058 
0059 static const char * const fimc_clock_names[] = {
0060     [FIMC_CLK_LCLK]   = "sclk_fimc",
0061     [FIMC_CLK_GATE]   = "fimc",
0062     [FIMC_CLK_WB_A]   = "pxl_async0",
0063     [FIMC_CLK_WB_B]   = "pxl_async1",
0064 };
0065 
0066 /*
0067  * A structure of scaler.
0068  *
0069  * @range: narrow, wide.
0070  * @bypass: unused scaler path.
0071  * @up_h: horizontal scale up.
0072  * @up_v: vertical scale up.
0073  * @hratio: horizontal ratio.
0074  * @vratio: vertical ratio.
0075  */
0076 struct fimc_scaler {
0077     bool range;
0078     bool bypass;
0079     bool up_h;
0080     bool up_v;
0081     u32 hratio;
0082     u32 vratio;
0083 };
0084 
0085 /*
0086  * A structure of fimc context.
0087  *
0088  * @regs: memory mapped io registers.
0089  * @lock: locking of operations.
0090  * @clocks: fimc clocks.
0091  * @sc: scaler infomations.
0092  * @pol: porarity of writeback.
0093  * @id: fimc id.
0094  * @irq: irq number.
0095  */
0096 struct fimc_context {
0097     struct exynos_drm_ipp ipp;
0098     struct drm_device *drm_dev;
0099     void        *dma_priv;
0100     struct device   *dev;
0101     struct exynos_drm_ipp_task  *task;
0102     struct exynos_drm_ipp_formats   *formats;
0103     unsigned int            num_formats;
0104 
0105     void __iomem    *regs;
0106     spinlock_t  lock;
0107     struct clk  *clocks[FIMC_CLKS_MAX];
0108     struct fimc_scaler  sc;
0109     int id;
0110     int irq;
0111 };
0112 
0113 static u32 fimc_read(struct fimc_context *ctx, u32 reg)
0114 {
0115     return readl(ctx->regs + reg);
0116 }
0117 
0118 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
0119 {
0120     writel(val, ctx->regs + reg);
0121 }
0122 
0123 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
0124 {
0125     void __iomem *r = ctx->regs + reg;
0126 
0127     writel(readl(r) | bits, r);
0128 }
0129 
0130 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
0131 {
0132     void __iomem *r = ctx->regs + reg;
0133 
0134     writel(readl(r) & ~bits, r);
0135 }
0136 
0137 static void fimc_sw_reset(struct fimc_context *ctx)
0138 {
0139     u32 cfg;
0140 
0141     /* stop dma operation */
0142     cfg = fimc_read(ctx, EXYNOS_CISTATUS);
0143     if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
0144         fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
0145 
0146     fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
0147 
0148     /* disable image capture */
0149     fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
0150         EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
0151 
0152     /* s/w reset */
0153     fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
0154 
0155     /* s/w reset complete */
0156     fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
0157 
0158     /* reset sequence */
0159     fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
0160 }
0161 
0162 static void fimc_set_type_ctrl(struct fimc_context *ctx)
0163 {
0164     u32 cfg;
0165 
0166     cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
0167     cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
0168         EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
0169         EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
0170         EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
0171         EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
0172         EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
0173 
0174     cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
0175         EXYNOS_CIGCTRL_SELWRITEBACK_A |
0176         EXYNOS_CIGCTRL_SELCAM_MIPI_A |
0177         EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
0178 
0179     fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
0180 }
0181 
0182 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
0183 {
0184     u32 cfg;
0185 
0186     DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]\n", enable);
0187 
0188     cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
0189     if (enable)
0190         cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
0191     else
0192         cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
0193 
0194     fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
0195 }
0196 
0197 static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
0198 {
0199     u32 cfg;
0200 
0201     DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]\n", enable);
0202 
0203     cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
0204     if (enable) {
0205         cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
0206         cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
0207     } else
0208         cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
0209     fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
0210 }
0211 
0212 static void fimc_clear_irq(struct fimc_context *ctx)
0213 {
0214     fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
0215 }
0216 
0217 static bool fimc_check_ovf(struct fimc_context *ctx)
0218 {
0219     u32 status, flag;
0220 
0221     status = fimc_read(ctx, EXYNOS_CISTATUS);
0222     flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
0223         EXYNOS_CISTATUS_OVFICR;
0224 
0225     DRM_DEV_DEBUG_KMS(ctx->dev, "flag[0x%x]\n", flag);
0226 
0227     if (status & flag) {
0228         fimc_set_bits(ctx, EXYNOS_CIWDOFST,
0229             EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
0230             EXYNOS_CIWDOFST_CLROVFICR);
0231 
0232         DRM_DEV_ERROR(ctx->dev,
0233                   "occurred overflow at %d, status 0x%x.\n",
0234                   ctx->id, status);
0235         return true;
0236     }
0237 
0238     return false;
0239 }
0240 
0241 static bool fimc_check_frame_end(struct fimc_context *ctx)
0242 {
0243     u32 cfg;
0244 
0245     cfg = fimc_read(ctx, EXYNOS_CISTATUS);
0246 
0247     DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]\n", cfg);
0248 
0249     if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
0250         return false;
0251 
0252     cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
0253     fimc_write(ctx, cfg, EXYNOS_CISTATUS);
0254 
0255     return true;
0256 }
0257 
0258 static int fimc_get_buf_id(struct fimc_context *ctx)
0259 {
0260     u32 cfg;
0261     int frame_cnt, buf_id;
0262 
0263     cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
0264     frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
0265 
0266     if (frame_cnt == 0)
0267         frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
0268 
0269     DRM_DEV_DEBUG_KMS(ctx->dev, "present[%d]before[%d]\n",
0270               EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
0271               EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
0272 
0273     if (frame_cnt == 0) {
0274         DRM_DEV_ERROR(ctx->dev, "failed to get frame count.\n");
0275         return -EIO;
0276     }
0277 
0278     buf_id = frame_cnt - 1;
0279     DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id[%d]\n", buf_id);
0280 
0281     return buf_id;
0282 }
0283 
0284 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
0285 {
0286     u32 cfg;
0287 
0288     DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]\n", enable);
0289 
0290     cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
0291     if (enable)
0292         cfg |= EXYNOS_CIOCTRL_LASTENDEN;
0293     else
0294         cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
0295 
0296     fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
0297 }
0298 
0299 static void fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
0300 {
0301     u32 cfg;
0302 
0303     DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
0304 
0305     /* RGB */
0306     cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
0307     cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
0308 
0309     switch (fmt) {
0310     case DRM_FORMAT_RGB565:
0311         cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
0312         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
0313         return;
0314     case DRM_FORMAT_RGB888:
0315     case DRM_FORMAT_XRGB8888:
0316         cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
0317         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
0318         return;
0319     default:
0320         /* bypass */
0321         break;
0322     }
0323 
0324     /* YUV */
0325     cfg = fimc_read(ctx, EXYNOS_MSCTRL);
0326     cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
0327         EXYNOS_MSCTRL_C_INT_IN_2PLANE |
0328         EXYNOS_MSCTRL_ORDER422_YCBYCR);
0329 
0330     switch (fmt) {
0331     case DRM_FORMAT_YUYV:
0332         cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
0333         break;
0334     case DRM_FORMAT_YVYU:
0335         cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
0336         break;
0337     case DRM_FORMAT_UYVY:
0338         cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
0339         break;
0340     case DRM_FORMAT_VYUY:
0341     case DRM_FORMAT_YUV444:
0342         cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
0343         break;
0344     case DRM_FORMAT_NV21:
0345     case DRM_FORMAT_NV61:
0346         cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
0347             EXYNOS_MSCTRL_C_INT_IN_2PLANE);
0348         break;
0349     case DRM_FORMAT_YUV422:
0350     case DRM_FORMAT_YUV420:
0351     case DRM_FORMAT_YVU420:
0352         cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
0353         break;
0354     case DRM_FORMAT_NV12:
0355     case DRM_FORMAT_NV16:
0356         cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
0357             EXYNOS_MSCTRL_C_INT_IN_2PLANE);
0358         break;
0359     }
0360 
0361     fimc_write(ctx, cfg, EXYNOS_MSCTRL);
0362 }
0363 
0364 static void fimc_src_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled)
0365 {
0366     u32 cfg;
0367 
0368     DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
0369 
0370     cfg = fimc_read(ctx, EXYNOS_MSCTRL);
0371     cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
0372 
0373     switch (fmt) {
0374     case DRM_FORMAT_RGB565:
0375     case DRM_FORMAT_RGB888:
0376     case DRM_FORMAT_XRGB8888:
0377         cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
0378         break;
0379     case DRM_FORMAT_YUV444:
0380         cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
0381         break;
0382     case DRM_FORMAT_YUYV:
0383     case DRM_FORMAT_YVYU:
0384     case DRM_FORMAT_UYVY:
0385     case DRM_FORMAT_VYUY:
0386         cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
0387         break;
0388     case DRM_FORMAT_NV16:
0389     case DRM_FORMAT_NV61:
0390     case DRM_FORMAT_YUV422:
0391         cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
0392         break;
0393     case DRM_FORMAT_YUV420:
0394     case DRM_FORMAT_YVU420:
0395     case DRM_FORMAT_NV12:
0396     case DRM_FORMAT_NV21:
0397         cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
0398         break;
0399     }
0400 
0401     fimc_write(ctx, cfg, EXYNOS_MSCTRL);
0402 
0403     cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
0404     cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
0405 
0406     if (tiled)
0407         cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
0408     else
0409         cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
0410 
0411     fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
0412 
0413     fimc_src_set_fmt_order(ctx, fmt);
0414 }
0415 
0416 static void fimc_src_set_transf(struct fimc_context *ctx, unsigned int rotation)
0417 {
0418     unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
0419     u32 cfg1, cfg2;
0420 
0421     DRM_DEV_DEBUG_KMS(ctx->dev, "rotation[%x]\n", rotation);
0422 
0423     cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
0424     cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
0425         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
0426 
0427     cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
0428     cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
0429 
0430     switch (degree) {
0431     case DRM_MODE_ROTATE_0:
0432         if (rotation & DRM_MODE_REFLECT_X)
0433             cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
0434         if (rotation & DRM_MODE_REFLECT_Y)
0435             cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
0436         break;
0437     case DRM_MODE_ROTATE_90:
0438         cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
0439         if (rotation & DRM_MODE_REFLECT_X)
0440             cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
0441         if (rotation & DRM_MODE_REFLECT_Y)
0442             cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
0443         break;
0444     case DRM_MODE_ROTATE_180:
0445         cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
0446             EXYNOS_MSCTRL_FLIP_Y_MIRROR);
0447         if (rotation & DRM_MODE_REFLECT_X)
0448             cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
0449         if (rotation & DRM_MODE_REFLECT_Y)
0450             cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
0451         break;
0452     case DRM_MODE_ROTATE_270:
0453         cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
0454             EXYNOS_MSCTRL_FLIP_Y_MIRROR);
0455         cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
0456         if (rotation & DRM_MODE_REFLECT_X)
0457             cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
0458         if (rotation & DRM_MODE_REFLECT_Y)
0459             cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
0460         break;
0461     }
0462 
0463     fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
0464     fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
0465 }
0466 
0467 static void fimc_set_window(struct fimc_context *ctx,
0468                 struct exynos_drm_ipp_buffer *buf)
0469 {
0470     unsigned int real_width = buf->buf.pitch[0] / buf->format->cpp[0];
0471     u32 cfg, h1, h2, v1, v2;
0472 
0473     /* cropped image */
0474     h1 = buf->rect.x;
0475     h2 = real_width - buf->rect.w - buf->rect.x;
0476     v1 = buf->rect.y;
0477     v2 = buf->buf.height - buf->rect.h - buf->rect.y;
0478 
0479     DRM_DEV_DEBUG_KMS(ctx->dev, "x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
0480               buf->rect.x, buf->rect.y, buf->rect.w, buf->rect.h,
0481               real_width, buf->buf.height);
0482     DRM_DEV_DEBUG_KMS(ctx->dev, "h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1,
0483               v2);
0484 
0485     /*
0486      * set window offset 1, 2 size
0487      * check figure 43-21 in user manual
0488      */
0489     cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
0490     cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
0491         EXYNOS_CIWDOFST_WINVEROFST_MASK);
0492     cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
0493         EXYNOS_CIWDOFST_WINVEROFST(v1));
0494     cfg |= EXYNOS_CIWDOFST_WINOFSEN;
0495     fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
0496 
0497     cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
0498         EXYNOS_CIWDOFST2_WINVEROFST2(v2));
0499     fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
0500 }
0501 
0502 static void fimc_src_set_size(struct fimc_context *ctx,
0503                   struct exynos_drm_ipp_buffer *buf)
0504 {
0505     unsigned int real_width = buf->buf.pitch[0] / buf->format->cpp[0];
0506     u32 cfg;
0507 
0508     DRM_DEV_DEBUG_KMS(ctx->dev, "hsize[%d]vsize[%d]\n", real_width,
0509               buf->buf.height);
0510 
0511     /* original size */
0512     cfg = (EXYNOS_ORGISIZE_HORIZONTAL(real_width) |
0513         EXYNOS_ORGISIZE_VERTICAL(buf->buf.height));
0514 
0515     fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
0516 
0517     DRM_DEV_DEBUG_KMS(ctx->dev, "x[%d]y[%d]w[%d]h[%d]\n", buf->rect.x,
0518               buf->rect.y, buf->rect.w, buf->rect.h);
0519 
0520     /* set input DMA image size */
0521     cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
0522     cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
0523         EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
0524     cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(buf->rect.w) |
0525         EXYNOS_CIREAL_ISIZE_HEIGHT(buf->rect.h));
0526     fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
0527 
0528     /*
0529      * set input FIFO image size
0530      * for now, we support only ITU601 8 bit mode
0531      */
0532     cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
0533         EXYNOS_CISRCFMT_SOURCEHSIZE(real_width) |
0534         EXYNOS_CISRCFMT_SOURCEVSIZE(buf->buf.height));
0535     fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
0536 
0537     /* offset Y(RGB), Cb, Cr */
0538     cfg = (EXYNOS_CIIYOFF_HORIZONTAL(buf->rect.x) |
0539         EXYNOS_CIIYOFF_VERTICAL(buf->rect.y));
0540     fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
0541     cfg = (EXYNOS_CIICBOFF_HORIZONTAL(buf->rect.x) |
0542         EXYNOS_CIICBOFF_VERTICAL(buf->rect.y));
0543     fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
0544     cfg = (EXYNOS_CIICROFF_HORIZONTAL(buf->rect.x) |
0545         EXYNOS_CIICROFF_VERTICAL(buf->rect.y));
0546     fimc_write(ctx, cfg, EXYNOS_CIICROFF);
0547 
0548     fimc_set_window(ctx, buf);
0549 }
0550 
0551 static void fimc_src_set_addr(struct fimc_context *ctx,
0552                   struct exynos_drm_ipp_buffer *buf)
0553 {
0554     fimc_write(ctx, buf->dma_addr[0], EXYNOS_CIIYSA(0));
0555     fimc_write(ctx, buf->dma_addr[1], EXYNOS_CIICBSA(0));
0556     fimc_write(ctx, buf->dma_addr[2], EXYNOS_CIICRSA(0));
0557 }
0558 
0559 static void fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
0560 {
0561     u32 cfg;
0562 
0563     DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
0564 
0565     /* RGB */
0566     cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
0567     cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
0568 
0569     switch (fmt) {
0570     case DRM_FORMAT_RGB565:
0571         cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
0572         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
0573         return;
0574     case DRM_FORMAT_RGB888:
0575         cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
0576         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
0577         return;
0578     case DRM_FORMAT_XRGB8888:
0579         cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
0580             EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
0581         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
0582         break;
0583     default:
0584         /* bypass */
0585         break;
0586     }
0587 
0588     /* YUV */
0589     cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
0590     cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
0591         EXYNOS_CIOCTRL_ORDER422_MASK |
0592         EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
0593 
0594     switch (fmt) {
0595     case DRM_FORMAT_XRGB8888:
0596         cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
0597         break;
0598     case DRM_FORMAT_YUYV:
0599         cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
0600         break;
0601     case DRM_FORMAT_YVYU:
0602         cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
0603         break;
0604     case DRM_FORMAT_UYVY:
0605         cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
0606         break;
0607     case DRM_FORMAT_VYUY:
0608         cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
0609         break;
0610     case DRM_FORMAT_NV21:
0611     case DRM_FORMAT_NV61:
0612         cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
0613         cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
0614         break;
0615     case DRM_FORMAT_YUV422:
0616     case DRM_FORMAT_YUV420:
0617     case DRM_FORMAT_YVU420:
0618         cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
0619         break;
0620     case DRM_FORMAT_NV12:
0621     case DRM_FORMAT_NV16:
0622         cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
0623         cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
0624         break;
0625     }
0626 
0627     fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
0628 }
0629 
0630 static void fimc_dst_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled)
0631 {
0632     u32 cfg;
0633 
0634     DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
0635 
0636     cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
0637 
0638     if (fmt == DRM_FORMAT_AYUV) {
0639         cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
0640         fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
0641     } else {
0642         cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
0643         fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
0644 
0645         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
0646         cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
0647 
0648         switch (fmt) {
0649         case DRM_FORMAT_RGB565:
0650         case DRM_FORMAT_RGB888:
0651         case DRM_FORMAT_XRGB8888:
0652             cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
0653             break;
0654         case DRM_FORMAT_YUYV:
0655         case DRM_FORMAT_YVYU:
0656         case DRM_FORMAT_UYVY:
0657         case DRM_FORMAT_VYUY:
0658             cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
0659             break;
0660         case DRM_FORMAT_NV16:
0661         case DRM_FORMAT_NV61:
0662         case DRM_FORMAT_YUV422:
0663             cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
0664             break;
0665         case DRM_FORMAT_YUV420:
0666         case DRM_FORMAT_YVU420:
0667         case DRM_FORMAT_NV12:
0668         case DRM_FORMAT_NV21:
0669             cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
0670             break;
0671         }
0672 
0673         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
0674     }
0675 
0676     cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
0677     cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
0678 
0679     if (tiled)
0680         cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
0681     else
0682         cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
0683 
0684     fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
0685 
0686     fimc_dst_set_fmt_order(ctx, fmt);
0687 }
0688 
0689 static void fimc_dst_set_transf(struct fimc_context *ctx, unsigned int rotation)
0690 {
0691     unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
0692     u32 cfg;
0693 
0694     DRM_DEV_DEBUG_KMS(ctx->dev, "rotation[0x%x]\n", rotation);
0695 
0696     cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
0697     cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
0698     cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
0699 
0700     switch (degree) {
0701     case DRM_MODE_ROTATE_0:
0702         if (rotation & DRM_MODE_REFLECT_X)
0703             cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
0704         if (rotation & DRM_MODE_REFLECT_Y)
0705             cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
0706         break;
0707     case DRM_MODE_ROTATE_90:
0708         cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
0709         if (rotation & DRM_MODE_REFLECT_X)
0710             cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
0711         if (rotation & DRM_MODE_REFLECT_Y)
0712             cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
0713         break;
0714     case DRM_MODE_ROTATE_180:
0715         cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
0716             EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
0717         if (rotation & DRM_MODE_REFLECT_X)
0718             cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
0719         if (rotation & DRM_MODE_REFLECT_Y)
0720             cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
0721         break;
0722     case DRM_MODE_ROTATE_270:
0723         cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
0724             EXYNOS_CITRGFMT_FLIP_X_MIRROR |
0725             EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
0726         if (rotation & DRM_MODE_REFLECT_X)
0727             cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
0728         if (rotation & DRM_MODE_REFLECT_Y)
0729             cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
0730         break;
0731     }
0732 
0733     fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
0734 }
0735 
0736 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
0737                   struct drm_exynos_ipp_task_rect *src,
0738                   struct drm_exynos_ipp_task_rect *dst)
0739 {
0740     u32 cfg, cfg_ext, shfactor;
0741     u32 pre_dst_width, pre_dst_height;
0742     u32 hfactor, vfactor;
0743     int ret = 0;
0744     u32 src_w, src_h, dst_w, dst_h;
0745 
0746     cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
0747     if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
0748         src_w = src->h;
0749         src_h = src->w;
0750     } else {
0751         src_w = src->w;
0752         src_h = src->h;
0753     }
0754 
0755     if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
0756         dst_w = dst->h;
0757         dst_h = dst->w;
0758     } else {
0759         dst_w = dst->w;
0760         dst_h = dst->h;
0761     }
0762 
0763     /* fimc_ippdrv_check_property assures that dividers are not null */
0764     hfactor = fls(src_w / dst_w / 2);
0765     if (hfactor > FIMC_SHFACTOR / 2) {
0766         dev_err(ctx->dev, "failed to get ratio horizontal.\n");
0767         return -EINVAL;
0768     }
0769 
0770     vfactor = fls(src_h / dst_h / 2);
0771     if (vfactor > FIMC_SHFACTOR / 2) {
0772         dev_err(ctx->dev, "failed to get ratio vertical.\n");
0773         return -EINVAL;
0774     }
0775 
0776     pre_dst_width = src_w >> hfactor;
0777     pre_dst_height = src_h >> vfactor;
0778     DRM_DEV_DEBUG_KMS(ctx->dev, "pre_dst_width[%d]pre_dst_height[%d]\n",
0779               pre_dst_width, pre_dst_height);
0780     DRM_DEV_DEBUG_KMS(ctx->dev, "hfactor[%d]vfactor[%d]\n", hfactor,
0781               vfactor);
0782 
0783     sc->hratio = (src_w << 14) / (dst_w << hfactor);
0784     sc->vratio = (src_h << 14) / (dst_h << vfactor);
0785     sc->up_h = (dst_w >= src_w);
0786     sc->up_v = (dst_h >= src_h);
0787     DRM_DEV_DEBUG_KMS(ctx->dev, "hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
0788               sc->hratio, sc->vratio, sc->up_h, sc->up_v);
0789 
0790     shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
0791     DRM_DEV_DEBUG_KMS(ctx->dev, "shfactor[%d]\n", shfactor);
0792 
0793     cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
0794         EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
0795         EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
0796     fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
0797 
0798     cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
0799         EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
0800     fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
0801 
0802     return ret;
0803 }
0804 
0805 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
0806 {
0807     u32 cfg, cfg_ext;
0808 
0809     DRM_DEV_DEBUG_KMS(ctx->dev, "range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
0810               sc->range, sc->bypass, sc->up_h, sc->up_v);
0811     DRM_DEV_DEBUG_KMS(ctx->dev, "hratio[%d]vratio[%d]\n",
0812               sc->hratio, sc->vratio);
0813 
0814     cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
0815     cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
0816         EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
0817         EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
0818         EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
0819         EXYNOS_CISCCTRL_CSCR2Y_WIDE |
0820         EXYNOS_CISCCTRL_CSCY2R_WIDE);
0821 
0822     if (sc->range)
0823         cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
0824             EXYNOS_CISCCTRL_CSCY2R_WIDE);
0825     if (sc->bypass)
0826         cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
0827     if (sc->up_h)
0828         cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
0829     if (sc->up_v)
0830         cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
0831 
0832     cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
0833         EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
0834     fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
0835 
0836     cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
0837     cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
0838     cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
0839     cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
0840         EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
0841     fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
0842 }
0843 
0844 static void fimc_dst_set_size(struct fimc_context *ctx,
0845                  struct exynos_drm_ipp_buffer *buf)
0846 {
0847     unsigned int real_width = buf->buf.pitch[0] / buf->format->cpp[0];
0848     u32 cfg, cfg_ext;
0849 
0850     DRM_DEV_DEBUG_KMS(ctx->dev, "hsize[%d]vsize[%d]\n", real_width,
0851               buf->buf.height);
0852 
0853     /* original size */
0854     cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(real_width) |
0855         EXYNOS_ORGOSIZE_VERTICAL(buf->buf.height));
0856 
0857     fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
0858 
0859     DRM_DEV_DEBUG_KMS(ctx->dev, "x[%d]y[%d]w[%d]h[%d]\n", buf->rect.x,
0860               buf->rect.y,
0861               buf->rect.w, buf->rect.h);
0862 
0863     /* CSC ITU */
0864     cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
0865     cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
0866 
0867     if (buf->buf.width >= FIMC_WIDTH_ITU_709)
0868         cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
0869     else
0870         cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
0871 
0872     fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
0873 
0874     cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
0875 
0876     /* target image size */
0877     cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
0878     cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
0879         EXYNOS_CITRGFMT_TARGETV_MASK);
0880     if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE)
0881         cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(buf->rect.h) |
0882             EXYNOS_CITRGFMT_TARGETVSIZE(buf->rect.w));
0883     else
0884         cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(buf->rect.w) |
0885             EXYNOS_CITRGFMT_TARGETVSIZE(buf->rect.h));
0886     fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
0887 
0888     /* target area */
0889     cfg = EXYNOS_CITAREA_TARGET_AREA(buf->rect.w * buf->rect.h);
0890     fimc_write(ctx, cfg, EXYNOS_CITAREA);
0891 
0892     /* offset Y(RGB), Cb, Cr */
0893     cfg = (EXYNOS_CIOYOFF_HORIZONTAL(buf->rect.x) |
0894         EXYNOS_CIOYOFF_VERTICAL(buf->rect.y));
0895     fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
0896     cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(buf->rect.x) |
0897         EXYNOS_CIOCBOFF_VERTICAL(buf->rect.y));
0898     fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
0899     cfg = (EXYNOS_CIOCROFF_HORIZONTAL(buf->rect.x) |
0900         EXYNOS_CIOCROFF_VERTICAL(buf->rect.y));
0901     fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
0902 }
0903 
0904 static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
0905         bool enqueue)
0906 {
0907     unsigned long flags;
0908     u32 buf_num;
0909     u32 cfg;
0910 
0911     DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id[%d]enqueu[%d]\n", buf_id, enqueue);
0912 
0913     spin_lock_irqsave(&ctx->lock, flags);
0914 
0915     cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
0916 
0917     if (enqueue)
0918         cfg |= (1 << buf_id);
0919     else
0920         cfg &= ~(1 << buf_id);
0921 
0922     fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
0923 
0924     buf_num = hweight32(cfg);
0925 
0926     if (enqueue && buf_num >= FIMC_BUF_START)
0927         fimc_mask_irq(ctx, true);
0928     else if (!enqueue && buf_num <= FIMC_BUF_STOP)
0929         fimc_mask_irq(ctx, false);
0930 
0931     spin_unlock_irqrestore(&ctx->lock, flags);
0932 }
0933 
0934 static void fimc_dst_set_addr(struct fimc_context *ctx,
0935                  struct exynos_drm_ipp_buffer *buf)
0936 {
0937     fimc_write(ctx, buf->dma_addr[0], EXYNOS_CIOYSA(0));
0938     fimc_write(ctx, buf->dma_addr[1], EXYNOS_CIOCBSA(0));
0939     fimc_write(ctx, buf->dma_addr[2], EXYNOS_CIOCRSA(0));
0940 
0941     fimc_dst_set_buf_seq(ctx, 0, true);
0942 }
0943 
0944 static void fimc_stop(struct fimc_context *ctx);
0945 
0946 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
0947 {
0948     struct fimc_context *ctx = dev_id;
0949     int buf_id;
0950 
0951     DRM_DEV_DEBUG_KMS(ctx->dev, "fimc id[%d]\n", ctx->id);
0952 
0953     fimc_clear_irq(ctx);
0954     if (fimc_check_ovf(ctx))
0955         return IRQ_NONE;
0956 
0957     if (!fimc_check_frame_end(ctx))
0958         return IRQ_NONE;
0959 
0960     buf_id = fimc_get_buf_id(ctx);
0961     if (buf_id < 0)
0962         return IRQ_HANDLED;
0963 
0964     DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id[%d]\n", buf_id);
0965 
0966     if (ctx->task) {
0967         struct exynos_drm_ipp_task *task = ctx->task;
0968 
0969         ctx->task = NULL;
0970         pm_runtime_mark_last_busy(ctx->dev);
0971         pm_runtime_put_autosuspend(ctx->dev);
0972         exynos_drm_ipp_task_done(task, 0);
0973     }
0974 
0975     fimc_dst_set_buf_seq(ctx, buf_id, false);
0976     fimc_stop(ctx);
0977 
0978     return IRQ_HANDLED;
0979 }
0980 
0981 static void fimc_clear_addr(struct fimc_context *ctx)
0982 {
0983     int i;
0984 
0985     for (i = 0; i < FIMC_MAX_SRC; i++) {
0986         fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
0987         fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
0988         fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
0989     }
0990 
0991     for (i = 0; i < FIMC_MAX_DST; i++) {
0992         fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
0993         fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
0994         fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
0995     }
0996 }
0997 
0998 static void fimc_reset(struct fimc_context *ctx)
0999 {
1000     /* reset h/w block */
1001     fimc_sw_reset(ctx);
1002 
1003     /* reset scaler capability */
1004     memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1005 
1006     fimc_clear_addr(ctx);
1007 }
1008 
1009 static void fimc_start(struct fimc_context *ctx)
1010 {
1011     u32 cfg0, cfg1;
1012 
1013     fimc_mask_irq(ctx, true);
1014 
1015     /* If set true, we can save jpeg about screen */
1016     fimc_handle_jpeg(ctx, false);
1017     fimc_set_scaler(ctx, &ctx->sc);
1018 
1019     fimc_set_type_ctrl(ctx);
1020     fimc_handle_lastend(ctx, false);
1021 
1022     /* setup dma */
1023     cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1024     cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1025     cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1026     fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1027 
1028     /* Reset status */
1029     fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1030 
1031     cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1032     cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1033     cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1034 
1035     /* Scaler */
1036     cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1037     cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1038     cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1039         EXYNOS_CISCCTRL_SCALERSTART);
1040 
1041     fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1042 
1043     /* Enable image capture*/
1044     cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1045     fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1046 
1047     /* Disable frame end irq */
1048     fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1049 
1050     fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1051 
1052     fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1053 }
1054 
1055 static void fimc_stop(struct fimc_context *ctx)
1056 {
1057     u32 cfg;
1058 
1059     /* Source clear */
1060     cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1061     cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1062     cfg &= ~EXYNOS_MSCTRL_ENVID;
1063     fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1064 
1065     fimc_mask_irq(ctx, false);
1066 
1067     /* reset sequence */
1068     fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1069 
1070     /* Scaler disable */
1071     fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1072 
1073     /* Disable image capture */
1074     fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1075         EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1076 
1077     /* Enable frame end irq */
1078     fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1079 }
1080 
1081 static int fimc_commit(struct exynos_drm_ipp *ipp,
1082               struct exynos_drm_ipp_task *task)
1083 {
1084     struct fimc_context *ctx =
1085             container_of(ipp, struct fimc_context, ipp);
1086     int ret;
1087 
1088     ret = pm_runtime_resume_and_get(ctx->dev);
1089     if (ret < 0) {
1090         dev_err(ctx->dev, "failed to enable FIMC device.\n");
1091         return ret;
1092     }
1093 
1094     ctx->task = task;
1095 
1096     fimc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier);
1097     fimc_src_set_size(ctx, &task->src);
1098     fimc_src_set_transf(ctx, DRM_MODE_ROTATE_0);
1099     fimc_src_set_addr(ctx, &task->src);
1100     fimc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier);
1101     fimc_dst_set_transf(ctx, task->transform.rotation);
1102     fimc_dst_set_size(ctx, &task->dst);
1103     fimc_dst_set_addr(ctx, &task->dst);
1104     fimc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
1105     fimc_start(ctx);
1106 
1107     return 0;
1108 }
1109 
1110 static void fimc_abort(struct exynos_drm_ipp *ipp,
1111               struct exynos_drm_ipp_task *task)
1112 {
1113     struct fimc_context *ctx =
1114             container_of(ipp, struct fimc_context, ipp);
1115 
1116     fimc_reset(ctx);
1117 
1118     if (ctx->task) {
1119         struct exynos_drm_ipp_task *task = ctx->task;
1120 
1121         ctx->task = NULL;
1122         pm_runtime_mark_last_busy(ctx->dev);
1123         pm_runtime_put_autosuspend(ctx->dev);
1124         exynos_drm_ipp_task_done(task, -EIO);
1125     }
1126 }
1127 
1128 static struct exynos_drm_ipp_funcs ipp_funcs = {
1129     .commit = fimc_commit,
1130     .abort = fimc_abort,
1131 };
1132 
1133 static int fimc_bind(struct device *dev, struct device *master, void *data)
1134 {
1135     struct fimc_context *ctx = dev_get_drvdata(dev);
1136     struct drm_device *drm_dev = data;
1137     struct exynos_drm_ipp *ipp = &ctx->ipp;
1138 
1139     ctx->drm_dev = drm_dev;
1140     ipp->drm_dev = drm_dev;
1141     exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1142 
1143     exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
1144             DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
1145             DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
1146             ctx->formats, ctx->num_formats, "fimc");
1147 
1148     dev_info(dev, "The exynos fimc has been probed successfully\n");
1149 
1150     return 0;
1151 }
1152 
1153 static void fimc_unbind(struct device *dev, struct device *master,
1154             void *data)
1155 {
1156     struct fimc_context *ctx = dev_get_drvdata(dev);
1157     struct drm_device *drm_dev = data;
1158     struct exynos_drm_ipp *ipp = &ctx->ipp;
1159 
1160     exynos_drm_ipp_unregister(dev, ipp);
1161     exynos_drm_unregister_dma(drm_dev, dev, &ctx->dma_priv);
1162 }
1163 
1164 static const struct component_ops fimc_component_ops = {
1165     .bind   = fimc_bind,
1166     .unbind = fimc_unbind,
1167 };
1168 
1169 static void fimc_put_clocks(struct fimc_context *ctx)
1170 {
1171     int i;
1172 
1173     for (i = 0; i < FIMC_CLKS_MAX; i++) {
1174         if (IS_ERR(ctx->clocks[i]))
1175             continue;
1176         clk_put(ctx->clocks[i]);
1177         ctx->clocks[i] = ERR_PTR(-EINVAL);
1178     }
1179 }
1180 
1181 static int fimc_setup_clocks(struct fimc_context *ctx)
1182 {
1183     struct device *fimc_dev = ctx->dev;
1184     struct device *dev;
1185     int ret, i;
1186 
1187     for (i = 0; i < FIMC_CLKS_MAX; i++)
1188         ctx->clocks[i] = ERR_PTR(-EINVAL);
1189 
1190     for (i = 0; i < FIMC_CLKS_MAX; i++) {
1191         if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1192             dev = fimc_dev->parent;
1193         else
1194             dev = fimc_dev;
1195 
1196         ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1197         if (IS_ERR(ctx->clocks[i])) {
1198             ret = PTR_ERR(ctx->clocks[i]);
1199             dev_err(fimc_dev, "failed to get clock: %s\n",
1200                         fimc_clock_names[i]);
1201             goto e_clk_free;
1202         }
1203     }
1204 
1205     ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1206     if (!ret)
1207         return ret;
1208 e_clk_free:
1209     fimc_put_clocks(ctx);
1210     return ret;
1211 }
1212 
1213 int exynos_drm_check_fimc_device(struct device *dev)
1214 {
1215     int id = of_alias_get_id(dev->of_node, "fimc");
1216 
1217     if (id >= 0 && (BIT(id) & fimc_mask))
1218         return 0;
1219     return -ENODEV;
1220 }
1221 
1222 static const unsigned int fimc_formats[] = {
1223     DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565,
1224     DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
1225     DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
1226     DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
1227     DRM_FORMAT_YUV444,
1228 };
1229 
1230 static const unsigned int fimc_tiled_formats[] = {
1231     DRM_FORMAT_NV12, DRM_FORMAT_NV21,
1232 };
1233 
1234 static const struct drm_exynos_ipp_limit fimc_4210_limits_v1[] = {
1235     { IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) },
1236     { IPP_SIZE_LIMIT(AREA, .h = { 16, 4224, 2 }, .v = { 16, 0, 2 }) },
1237     { IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1920 }, .v = { 128, 0 }) },
1238     { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 },
1239               .v = { (1 << 16) / 64, (1 << 16) * 64 }) },
1240 };
1241 
1242 static const struct drm_exynos_ipp_limit fimc_4210_limits_v2[] = {
1243     { IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) },
1244     { IPP_SIZE_LIMIT(AREA, .h = { 16, 1920, 2 }, .v = { 16, 0, 2 }) },
1245     { IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1366 }, .v = { 128, 0 }) },
1246     { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 },
1247               .v = { (1 << 16) / 64, (1 << 16) * 64 }) },
1248 };
1249 
1250 static const struct drm_exynos_ipp_limit fimc_4210_limits_tiled_v1[] = {
1251     { IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) },
1252     { IPP_SIZE_LIMIT(AREA, .h = { 128, 1920, 2 }, .v = { 128, 0, 2 }) },
1253     { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 },
1254               .v = { (1 << 16) / 64, (1 << 16) * 64 }) },
1255 };
1256 
1257 static const struct drm_exynos_ipp_limit fimc_4210_limits_tiled_v2[] = {
1258     { IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) },
1259     { IPP_SIZE_LIMIT(AREA, .h = { 128, 1366, 2 }, .v = { 128, 0, 2 }) },
1260     { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 },
1261               .v = { (1 << 16) / 64, (1 << 16) * 64 }) },
1262 };
1263 
1264 static int fimc_probe(struct platform_device *pdev)
1265 {
1266     const struct drm_exynos_ipp_limit *limits;
1267     struct exynos_drm_ipp_formats *formats;
1268     struct device *dev = &pdev->dev;
1269     struct fimc_context *ctx;
1270     int ret;
1271     int i, j, num_limits, num_formats;
1272 
1273     if (exynos_drm_check_fimc_device(dev) != 0)
1274         return -ENODEV;
1275 
1276     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1277     if (!ctx)
1278         return -ENOMEM;
1279 
1280     ctx->dev = dev;
1281     ctx->id = of_alias_get_id(dev->of_node, "fimc");
1282 
1283     /* construct formats/limits array */
1284     num_formats = ARRAY_SIZE(fimc_formats) + ARRAY_SIZE(fimc_tiled_formats);
1285     formats = devm_kcalloc(dev, num_formats, sizeof(*formats),
1286                    GFP_KERNEL);
1287     if (!formats)
1288         return -ENOMEM;
1289 
1290     /* linear formats */
1291     if (ctx->id < 3) {
1292         limits = fimc_4210_limits_v1;
1293         num_limits = ARRAY_SIZE(fimc_4210_limits_v1);
1294     } else {
1295         limits = fimc_4210_limits_v2;
1296         num_limits = ARRAY_SIZE(fimc_4210_limits_v2);
1297     }
1298     for (i = 0; i < ARRAY_SIZE(fimc_formats); i++) {
1299         formats[i].fourcc = fimc_formats[i];
1300         formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1301                   DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1302         formats[i].limits = limits;
1303         formats[i].num_limits = num_limits;
1304     }
1305 
1306     /* tiled formats */
1307     if (ctx->id < 3) {
1308         limits = fimc_4210_limits_tiled_v1;
1309         num_limits = ARRAY_SIZE(fimc_4210_limits_tiled_v1);
1310     } else {
1311         limits = fimc_4210_limits_tiled_v2;
1312         num_limits = ARRAY_SIZE(fimc_4210_limits_tiled_v2);
1313     }
1314     for (j = i, i = 0; i < ARRAY_SIZE(fimc_tiled_formats); j++, i++) {
1315         formats[j].fourcc = fimc_tiled_formats[i];
1316         formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_64_32_TILE;
1317         formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1318                   DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1319         formats[j].limits = limits;
1320         formats[j].num_limits = num_limits;
1321     }
1322 
1323     ctx->formats = formats;
1324     ctx->num_formats = num_formats;
1325 
1326     /* resource memory */
1327     ctx->regs = devm_platform_ioremap_resource(pdev, 0);
1328     if (IS_ERR(ctx->regs))
1329         return PTR_ERR(ctx->regs);
1330 
1331     /* resource irq */
1332     ret = platform_get_irq(pdev, 0);
1333     if (ret < 0)
1334         return ret;
1335 
1336     ret = devm_request_irq(dev, ret, fimc_irq_handler,
1337                    0, dev_name(dev), ctx);
1338     if (ret < 0) {
1339         dev_err(dev, "failed to request irq.\n");
1340         return ret;
1341     }
1342 
1343     ret = fimc_setup_clocks(ctx);
1344     if (ret < 0)
1345         return ret;
1346 
1347     spin_lock_init(&ctx->lock);
1348     platform_set_drvdata(pdev, ctx);
1349 
1350     pm_runtime_use_autosuspend(dev);
1351     pm_runtime_set_autosuspend_delay(dev, FIMC_AUTOSUSPEND_DELAY);
1352     pm_runtime_enable(dev);
1353 
1354     ret = component_add(dev, &fimc_component_ops);
1355     if (ret)
1356         goto err_pm_dis;
1357 
1358     dev_info(dev, "drm fimc registered successfully.\n");
1359 
1360     return 0;
1361 
1362 err_pm_dis:
1363     pm_runtime_dont_use_autosuspend(dev);
1364     pm_runtime_disable(dev);
1365     fimc_put_clocks(ctx);
1366 
1367     return ret;
1368 }
1369 
1370 static int fimc_remove(struct platform_device *pdev)
1371 {
1372     struct device *dev = &pdev->dev;
1373     struct fimc_context *ctx = get_fimc_context(dev);
1374 
1375     component_del(dev, &fimc_component_ops);
1376     pm_runtime_dont_use_autosuspend(dev);
1377     pm_runtime_disable(dev);
1378 
1379     fimc_put_clocks(ctx);
1380 
1381     return 0;
1382 }
1383 
1384 #ifdef CONFIG_PM
1385 static int fimc_runtime_suspend(struct device *dev)
1386 {
1387     struct fimc_context *ctx = get_fimc_context(dev);
1388 
1389     DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1390     clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1391     return 0;
1392 }
1393 
1394 static int fimc_runtime_resume(struct device *dev)
1395 {
1396     struct fimc_context *ctx = get_fimc_context(dev);
1397 
1398     DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1399     return clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1400 }
1401 #endif
1402 
1403 static const struct dev_pm_ops fimc_pm_ops = {
1404     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1405                 pm_runtime_force_resume)
1406     SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1407 };
1408 
1409 static const struct of_device_id fimc_of_match[] = {
1410     { .compatible = "samsung,exynos4210-fimc" },
1411     { .compatible = "samsung,exynos4212-fimc" },
1412     { },
1413 };
1414 MODULE_DEVICE_TABLE(of, fimc_of_match);
1415 
1416 struct platform_driver fimc_driver = {
1417     .probe      = fimc_probe,
1418     .remove     = fimc_remove,
1419     .driver     = {
1420         .of_match_table = fimc_of_match,
1421         .name   = "exynos-drm-fimc",
1422         .owner  = THIS_MODULE,
1423         .pm = &fimc_pm_ops,
1424     },
1425 };
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