drm/exynos/exynos_drm_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* exynos_drm_drv.h
0003  *
0004  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0005  * Authors:
0006  *  Inki Dae <inki.dae@samsung.com>
0007  *  Joonyoung Shim <jy0922.shim@samsung.com>
0008  *  Seung-Woo Kim <sw0312.kim@samsung.com>
0009  */
0010
0011 #ifndef _EXYNOS_DRM_DRV_H_
0012 #define _EXYNOS_DRM_DRV_H_
0013
0014 #include <linux/module.h>
0015
0016 #include <drm/drm_crtc.h>
0017 #include <drm/drm_device.h>
0018 #include <drm/drm_plane.h>
0019
0020 #define MAX_CRTC    3
0021 #define MAX_PLANE   5
0022 #define MAX_FB_BUFFER   4
0023
0024 #define DEFAULT_WIN 0
0025
0026 struct drm_crtc_state;
0027 struct drm_display_mode;
0028
0029 #define to_exynos_crtc(x)   container_of(x, struct exynos_drm_crtc, base)
0030 #define to_exynos_plane(x)  container_of(x, struct exynos_drm_plane, base)
0031
0032 /* this enumerates display type. */
0033 enum exynos_drm_output_type {
0034     EXYNOS_DISPLAY_TYPE_NONE,
0035     /* RGB or CPU Interface. */
0036     EXYNOS_DISPLAY_TYPE_LCD,
0037     /* HDMI Interface. */
0038     EXYNOS_DISPLAY_TYPE_HDMI,
0039     /* Virtual Display Interface. */
0040     EXYNOS_DISPLAY_TYPE_VIDI,
0041 };
0042
0043 struct exynos_drm_rect {
0044     unsigned int x, y;
0045     unsigned int w, h;
0046 };
0047
0048 /*
0049  * Exynos drm plane state structure.
0050  *
0051  * @base: plane_state object (contains drm_framebuffer pointer)
0052  * @src: rectangle of the source image data to be displayed (clipped to
0053  *       visible part).
0054  * @crtc: rectangle of the target image position on hardware screen
0055  *       (clipped to visible part).
0056  * @h_ratio: horizontal scaling ratio, 16.16 fixed point
0057  * @v_ratio: vertical scaling ratio, 16.16 fixed point
0058  *
0059  * this structure consists plane state data that will be applied to hardware
0060  * specific overlay info.
0061  */
0062
0063 struct exynos_drm_plane_state {
0064     struct drm_plane_state base;
0065     struct exynos_drm_rect crtc;
0066     struct exynos_drm_rect src;
0067     unsigned int h_ratio;
0068     unsigned int v_ratio;
0069 };
0070
0071 static inline struct exynos_drm_plane_state *
0072 to_exynos_plane_state(struct drm_plane_state *state)
0073 {
0074     return container_of(state, struct exynos_drm_plane_state, base);
0075 }
0076
0077 /*
0078  * Exynos drm common overlay structure.
0079  *
0080  * @base: plane object
0081  * @index: hardware index of the overlay layer
0082  *
0083  * this structure is common to exynos SoC and its contents would be copied
0084  * to hardware specific overlay info.
0085  */
0086
0087 struct exynos_drm_plane {
0088     struct drm_plane base;
0089     const struct exynos_drm_plane_config *config;
0090     unsigned int index;
0091 };
0092
0093 #define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0)
0094 #define EXYNOS_DRM_PLANE_CAP_SCALE  (1 << 1)
0095 #define EXYNOS_DRM_PLANE_CAP_ZPOS   (1 << 2)
0096 #define EXYNOS_DRM_PLANE_CAP_TILE   (1 << 3)
0097 #define EXYNOS_DRM_PLANE_CAP_PIX_BLEND  (1 << 4)
0098 #define EXYNOS_DRM_PLANE_CAP_WIN_BLEND  (1 << 5)
0099
0100 /*
0101  * Exynos DRM plane configuration structure.
0102  *
0103  * @zpos: initial z-position of the plane.
0104  * @type: type of the plane (primary, cursor or overlay).
0105  * @pixel_formats: supported pixel formats.
0106  * @num_pixel_formats: number of elements in 'pixel_formats'.
0107  * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*)
0108  */
0109
0110 struct exynos_drm_plane_config {
0111     unsigned int zpos;
0112     enum drm_plane_type type;
0113     const uint32_t *pixel_formats;
0114     unsigned int num_pixel_formats;
0115     unsigned int capabilities;
0116 };
0117
0118 /*
0119  * Exynos drm crtc ops
0120  *
0121  * @atomic_enable: enable the device
0122  * @atomic_disable: disable the device
0123  * @enable_vblank: specific driver callback for enabling vblank interrupt.
0124  * @disable_vblank: specific driver callback for disabling vblank interrupt.
0125  * @mode_valid: specific driver callback for mode validation
0126  * @atomic_check: validate state
0127  * @atomic_begin: prepare device to receive an update
0128  * @atomic_flush: mark the end of device update
0129  * @update_plane: apply hardware specific overlay data to registers.
0130  * @disable_plane: disable hardware specific overlay.
0131  * @te_handler: trigger to transfer video image at the tearing effect
0132  *  synchronization signal if there is a page flip request.
0133  */
0134 struct exynos_drm_crtc;
0135 struct exynos_drm_crtc_ops {
0136     void (*atomic_enable)(struct exynos_drm_crtc *crtc);
0137     void (*atomic_disable)(struct exynos_drm_crtc *crtc);
0138     int (*enable_vblank)(struct exynos_drm_crtc *crtc);
0139     void (*disable_vblank)(struct exynos_drm_crtc *crtc);
0140     enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
0141         const struct drm_display_mode *mode);
0142     bool (*mode_fixup)(struct exynos_drm_crtc *crtc,
0143                const struct drm_display_mode *mode,
0144                struct drm_display_mode *adjusted_mode);
0145     int (*atomic_check)(struct exynos_drm_crtc *crtc,
0146                 struct drm_crtc_state *state);
0147     void (*atomic_begin)(struct exynos_drm_crtc *crtc);
0148     void (*update_plane)(struct exynos_drm_crtc *crtc,
0149                  struct exynos_drm_plane *plane);
0150     void (*disable_plane)(struct exynos_drm_crtc *crtc,
0151                   struct exynos_drm_plane *plane);
0152     void (*atomic_flush)(struct exynos_drm_crtc *crtc);
0153     void (*te_handler)(struct exynos_drm_crtc *crtc);
0154 };
0155
0156 struct exynos_drm_clk {
0157     void (*enable)(struct exynos_drm_clk *clk, bool enable);
0158 };
0159
0160 /*
0161  * Exynos specific crtc structure.
0162  *
0163  * @base: crtc object.
0164  * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI.
0165  * @ops: pointer to callbacks for exynos drm specific functionality
0166  * @ctx: A pointer to the crtc's implementation specific context
0167  * @pipe_clk: A pointer to the crtc's pipeline clock.
0168  */
0169 struct exynos_drm_crtc {
0170     struct drm_crtc         base;
0171     enum exynos_drm_output_type type;
0172     const struct exynos_drm_crtc_ops    *ops;
0173     void                *ctx;
0174     struct exynos_drm_clk       *pipe_clk;
0175     bool                i80_mode : 1;
0176 };
0177
0178 static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc,
0179                           bool enable)
0180 {
0181     if (crtc->pipe_clk)
0182         crtc->pipe_clk->enable(crtc->pipe_clk, enable);
0183 }
0184
0185 struct drm_exynos_file_private {
0186     /* for g2d api */
0187     struct list_head    inuse_cmdlist;
0188     struct list_head    event_list;
0189     struct list_head    userptr_list;
0190 };
0191
0192 /*
0193  * Exynos drm private structure.
0194  *
0195  * @pending: the crtcs that have pending updates to finish
0196  * @lock: protect access to @pending
0197  * @wait: wait an atomic commit to finish
0198  */
0199 struct exynos_drm_private {
0200     struct drm_fb_helper *fb_helper;
0201
0202     struct device *g2d_dev;
0203     struct device *dma_dev;
0204     void *mapping;
0205
0206     /* for atomic commit */
0207     u32         pending;
0208     spinlock_t      lock;
0209     wait_queue_head_t   wait;
0210 };
0211
0212 static inline struct device *to_dma_dev(struct drm_device *dev)
0213 {
0214     struct exynos_drm_private *priv = dev->dev_private;
0215
0216     return priv->dma_dev;
0217 }
0218
0219 static inline bool is_drm_iommu_supported(struct drm_device *drm_dev)
0220 {
0221     struct exynos_drm_private *priv = drm_dev->dev_private;
0222
0223     return priv->mapping ? true : false;
0224 }
0225
0226 int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
0227                 void **dma_priv);
0228 void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev,
0229                    void **dma_priv);
0230 void exynos_drm_cleanup_dma(struct drm_device *drm);
0231
0232 #ifdef CONFIG_DRM_EXYNOS_DPI
0233 struct drm_encoder *exynos_dpi_probe(struct device *dev);
0234 int exynos_dpi_remove(struct drm_encoder *encoder);
0235 int exynos_dpi_bind(struct drm_device *dev, struct drm_encoder *encoder);
0236 #else
0237 static inline struct drm_encoder *
0238 exynos_dpi_probe(struct device *dev) { return NULL; }
0239 static inline int exynos_dpi_remove(struct drm_encoder *encoder)
0240 {
0241     return 0;
0242 }
0243 static inline int exynos_dpi_bind(struct drm_device *dev,
0244                   struct drm_encoder *encoder)
0245 {
0246     return 0;
0247 }
0248 #endif
0249
0250 #ifdef CONFIG_DRM_EXYNOS_FIMC
0251 int exynos_drm_check_fimc_device(struct device *dev);
0252 #else
0253 static inline int exynos_drm_check_fimc_device(struct device *dev)
0254 {
0255     return 0;
0256 }
0257 #endif
0258
0259 int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state,
0260              bool nonblock);
0261
0262
0263 extern struct platform_driver fimd_driver;
0264 extern struct platform_driver exynos5433_decon_driver;
0265 extern struct platform_driver decon_driver;
0266 extern struct platform_driver dp_driver;
0267 extern struct platform_driver dsi_driver;
0268 extern struct platform_driver mixer_driver;
0269 extern struct platform_driver hdmi_driver;
0270 extern struct platform_driver vidi_driver;
0271 extern struct platform_driver g2d_driver;
0272 extern struct platform_driver fimc_driver;
0273 extern struct platform_driver rotator_driver;
0274 extern struct platform_driver scaler_driver;
0275 extern struct platform_driver gsc_driver;
0276 extern struct platform_driver mic_driver;
0277 #endif