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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* drivers/gpu/drm/exynos5433_drm_decon.c
0003  *
0004  * Copyright (C) 2015 Samsung Electronics Co.Ltd
0005  * Authors:
0006  *  Joonyoung Shim <jy0922.shim@samsung.com>
0007  *  Hyungwon Hwang <human.hwang@samsung.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/component.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/irq.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/regmap.h>
0019 
0020 #include <drm/drm_blend.h>
0021 #include <drm/drm_fourcc.h>
0022 #include <drm/drm_framebuffer.h>
0023 #include <drm/drm_vblank.h>
0024 
0025 #include "exynos_drm_crtc.h"
0026 #include "exynos_drm_drv.h"
0027 #include "exynos_drm_fb.h"
0028 #include "exynos_drm_plane.h"
0029 #include "regs-decon5433.h"
0030 
0031 #define DSD_CFG_MUX 0x1004
0032 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
0033 
0034 #define WINDOWS_NR  5
0035 #define PRIMARY_WIN 2
0036 #define CURSON_WIN  4
0037 
0038 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
0039 
0040 #define I80_HW_TRG  (1 << 0)
0041 #define IFTYPE_HDMI (1 << 1)
0042 
0043 static const char * const decon_clks_name[] = {
0044     "pclk",
0045     "aclk_decon",
0046     "aclk_smmu_decon0x",
0047     "aclk_xiu_decon0x",
0048     "pclk_smmu_decon0x",
0049     "aclk_smmu_decon1x",
0050     "aclk_xiu_decon1x",
0051     "pclk_smmu_decon1x",
0052     "sclk_decon_vclk",
0053     "sclk_decon_eclk",
0054 };
0055 
0056 struct decon_context {
0057     struct device           *dev;
0058     struct drm_device       *drm_dev;
0059     void                *dma_priv;
0060     struct exynos_drm_crtc      *crtc;
0061     struct exynos_drm_plane     planes[WINDOWS_NR];
0062     struct exynos_drm_plane_config  configs[WINDOWS_NR];
0063     void __iomem            *addr;
0064     struct regmap           *sysreg;
0065     struct clk          *clks[ARRAY_SIZE(decon_clks_name)];
0066     unsigned int            irq;
0067     unsigned int            irq_vsync;
0068     unsigned int            irq_lcd_sys;
0069     unsigned int            te_irq;
0070     unsigned long           out_type;
0071     int             first_win;
0072     spinlock_t          vblank_lock;
0073     u32             frame_id;
0074 };
0075 
0076 static const uint32_t decon_formats[] = {
0077     DRM_FORMAT_XRGB1555,
0078     DRM_FORMAT_RGB565,
0079     DRM_FORMAT_XRGB8888,
0080     DRM_FORMAT_ARGB8888,
0081 };
0082 
0083 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
0084     [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
0085     [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
0086 };
0087 
0088 static const unsigned int capabilities[WINDOWS_NR] = {
0089     0,
0090     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0091     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0092     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0093     EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
0094 };
0095 
0096 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
0097                   u32 val)
0098 {
0099     val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
0100     writel(val, ctx->addr + reg);
0101 }
0102 
0103 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
0104 {
0105     struct decon_context *ctx = crtc->ctx;
0106     u32 val;
0107 
0108     val = VIDINTCON0_INTEN;
0109     if (crtc->i80_mode)
0110         val |= VIDINTCON0_FRAMEDONE;
0111     else
0112         val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
0113 
0114     writel(val, ctx->addr + DECON_VIDINTCON0);
0115 
0116     enable_irq(ctx->irq);
0117     if (!(ctx->out_type & I80_HW_TRG))
0118         enable_irq(ctx->te_irq);
0119 
0120     return 0;
0121 }
0122 
0123 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
0124 {
0125     struct decon_context *ctx = crtc->ctx;
0126 
0127     if (!(ctx->out_type & I80_HW_TRG))
0128         disable_irq_nosync(ctx->te_irq);
0129     disable_irq_nosync(ctx->irq);
0130 
0131     writel(0, ctx->addr + DECON_VIDINTCON0);
0132 }
0133 
0134 /* return number of starts/ends of frame transmissions since reset */
0135 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
0136 {
0137     u32 frm, pfrm, status, cnt = 2;
0138 
0139     /* To get consistent result repeat read until frame id is stable.
0140      * Usually the loop will be executed once, in rare cases when the loop
0141      * is executed at frame change time 2nd pass will be needed.
0142      */
0143     frm = readl(ctx->addr + DECON_CRFMID);
0144     do {
0145         status = readl(ctx->addr + DECON_VIDCON1);
0146         pfrm = frm;
0147         frm = readl(ctx->addr + DECON_CRFMID);
0148     } while (frm != pfrm && --cnt);
0149 
0150     /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
0151      * of RGB, it should be taken into account.
0152      */
0153     if (!frm)
0154         return 0;
0155 
0156     switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
0157     case VIDCON1_VSTATUS_VS:
0158         if (!(ctx->crtc->i80_mode))
0159             --frm;
0160         break;
0161     case VIDCON1_VSTATUS_BP:
0162         --frm;
0163         break;
0164     case VIDCON1_I80_ACTIVE:
0165     case VIDCON1_VSTATUS_AC:
0166         if (end)
0167             --frm;
0168         break;
0169     default:
0170         break;
0171     }
0172 
0173     return frm;
0174 }
0175 
0176 static void decon_setup_trigger(struct decon_context *ctx)
0177 {
0178     if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
0179         return;
0180 
0181     if (!(ctx->out_type & I80_HW_TRG)) {
0182         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
0183                TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
0184                ctx->addr + DECON_TRIGCON);
0185         return;
0186     }
0187 
0188     writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
0189            | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
0190 
0191     if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
0192                    DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
0193         DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
0194 }
0195 
0196 static void decon_commit(struct exynos_drm_crtc *crtc)
0197 {
0198     struct decon_context *ctx = crtc->ctx;
0199     struct drm_display_mode *m = &crtc->base.mode;
0200     bool interlaced = false;
0201     u32 val;
0202 
0203     if (ctx->out_type & IFTYPE_HDMI) {
0204         m->crtc_hsync_start = m->crtc_hdisplay + 10;
0205         m->crtc_hsync_end = m->crtc_htotal - 92;
0206         m->crtc_vsync_start = m->crtc_vdisplay + 1;
0207         m->crtc_vsync_end = m->crtc_vsync_start + 1;
0208         if (m->flags & DRM_MODE_FLAG_INTERLACE)
0209             interlaced = true;
0210     }
0211 
0212     decon_setup_trigger(ctx);
0213 
0214     /* lcd on and use command if */
0215     val = VIDOUT_LCD_ON;
0216     if (interlaced)
0217         val |= VIDOUT_INTERLACE_EN_F;
0218     if (crtc->i80_mode) {
0219         val |= VIDOUT_COMMAND_IF;
0220     } else {
0221         val |= VIDOUT_RGB_IF;
0222     }
0223 
0224     writel(val, ctx->addr + DECON_VIDOUTCON0);
0225 
0226     if (interlaced)
0227         val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
0228             VIDTCON2_HOZVAL(m->hdisplay - 1);
0229     else
0230         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
0231             VIDTCON2_HOZVAL(m->hdisplay - 1);
0232     writel(val, ctx->addr + DECON_VIDTCON2);
0233 
0234     if (!crtc->i80_mode) {
0235         int vbp = m->crtc_vtotal - m->crtc_vsync_end;
0236         int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
0237 
0238         if (interlaced)
0239             vbp = vbp / 2 - 1;
0240         val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
0241         writel(val, ctx->addr + DECON_VIDTCON00);
0242 
0243         val = VIDTCON01_VSPW_F(
0244                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
0245         writel(val, ctx->addr + DECON_VIDTCON01);
0246 
0247         val = VIDTCON10_HBPD_F(
0248                 m->crtc_htotal - m->crtc_hsync_end - 1) |
0249             VIDTCON10_HFPD_F(
0250                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
0251         writel(val, ctx->addr + DECON_VIDTCON10);
0252 
0253         val = VIDTCON11_HSPW_F(
0254                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
0255         writel(val, ctx->addr + DECON_VIDTCON11);
0256     }
0257 
0258     /* enable output and display signal */
0259     decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
0260 
0261     decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
0262 }
0263 
0264 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
0265                 unsigned int alpha, unsigned int pixel_alpha)
0266 {
0267     u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
0268     u32 val = 0;
0269 
0270     switch (pixel_alpha) {
0271     case DRM_MODE_BLEND_PIXEL_NONE:
0272     case DRM_MODE_BLEND_COVERAGE:
0273         val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
0274         val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
0275         break;
0276     case DRM_MODE_BLEND_PREMULTI:
0277     default:
0278         if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
0279             val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
0280             val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
0281         } else {
0282             val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
0283             val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
0284         }
0285         break;
0286     }
0287     decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
0288 }
0289 
0290 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
0291                  unsigned int alpha, unsigned int pixel_alpha)
0292 {
0293     u32 win_alpha = alpha >> 8;
0294     u32 val = 0;
0295 
0296     switch (pixel_alpha) {
0297     case DRM_MODE_BLEND_PIXEL_NONE:
0298         break;
0299     case DRM_MODE_BLEND_COVERAGE:
0300     case DRM_MODE_BLEND_PREMULTI:
0301     default:
0302         val |= WINCONx_ALPHA_SEL_F;
0303         val |= WINCONx_BLD_PIX_F;
0304         val |= WINCONx_ALPHA_MUL_F;
0305         break;
0306     }
0307     decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
0308 
0309     if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
0310         val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
0311               VIDOSD_Wx_ALPHA_G_F(win_alpha) |
0312               VIDOSD_Wx_ALPHA_B_F(win_alpha);
0313         decon_set_bits(ctx, DECON_VIDOSDxC(win),
0314                    VIDOSDxC_ALPHA0_RGB_MASK, val);
0315         decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
0316     }
0317 }
0318 
0319 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
0320                  struct drm_framebuffer *fb)
0321 {
0322     struct exynos_drm_plane plane = ctx->planes[win];
0323     struct exynos_drm_plane_state *state =
0324         to_exynos_plane_state(plane.base.state);
0325     unsigned int alpha = state->base.alpha;
0326     unsigned int pixel_alpha;
0327     unsigned long val;
0328 
0329     if (fb->format->has_alpha)
0330         pixel_alpha = state->base.pixel_blend_mode;
0331     else
0332         pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
0333 
0334     val = readl(ctx->addr + DECON_WINCONx(win));
0335     val &= WINCONx_ENWIN_F;
0336 
0337     switch (fb->format->format) {
0338     case DRM_FORMAT_XRGB1555:
0339         val |= WINCONx_BPPMODE_16BPP_I1555;
0340         val |= WINCONx_HAWSWP_F;
0341         val |= WINCONx_BURSTLEN_16WORD;
0342         break;
0343     case DRM_FORMAT_RGB565:
0344         val |= WINCONx_BPPMODE_16BPP_565;
0345         val |= WINCONx_HAWSWP_F;
0346         val |= WINCONx_BURSTLEN_16WORD;
0347         break;
0348     case DRM_FORMAT_XRGB8888:
0349         val |= WINCONx_BPPMODE_24BPP_888;
0350         val |= WINCONx_WSWP_F;
0351         val |= WINCONx_BURSTLEN_16WORD;
0352         break;
0353     case DRM_FORMAT_ARGB8888:
0354     default:
0355         val |= WINCONx_BPPMODE_32BPP_A8888;
0356         val |= WINCONx_WSWP_F;
0357         val |= WINCONx_BURSTLEN_16WORD;
0358         break;
0359     }
0360 
0361     DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
0362 
0363     /*
0364      * In case of exynos, setting dma-burst to 16Word causes permanent
0365      * tearing for very small buffers, e.g. cursor buffer. Burst Mode
0366      * switching which is based on plane size is not recommended as
0367      * plane size varies a lot towards the end of the screen and rapid
0368      * movement causes unstable DMA which results into iommu crash/tear.
0369      */
0370 
0371     if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
0372         val &= ~WINCONx_BURSTLEN_MASK;
0373         val |= WINCONx_BURSTLEN_8WORD;
0374     }
0375     decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
0376 
0377     if (win > 0) {
0378         decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
0379         decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
0380     }
0381 }
0382 
0383 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
0384 {
0385     decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
0386                protect ? ~0 : 0);
0387 }
0388 
0389 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
0390 {
0391     struct decon_context *ctx = crtc->ctx;
0392 
0393     decon_shadow_protect(ctx, true);
0394 }
0395 
0396 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
0397 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
0398 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
0399 
0400 static void decon_update_plane(struct exynos_drm_crtc *crtc,
0401                    struct exynos_drm_plane *plane)
0402 {
0403     struct exynos_drm_plane_state *state =
0404                 to_exynos_plane_state(plane->base.state);
0405     struct decon_context *ctx = crtc->ctx;
0406     struct drm_framebuffer *fb = state->base.fb;
0407     unsigned int win = plane->index;
0408     unsigned int cpp = fb->format->cpp[0];
0409     unsigned int pitch = fb->pitches[0];
0410     dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
0411     u32 val;
0412 
0413     if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
0414         val = COORDINATE_X(state->crtc.x) |
0415             COORDINATE_Y(state->crtc.y / 2);
0416         writel(val, ctx->addr + DECON_VIDOSDxA(win));
0417 
0418         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
0419             COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
0420         writel(val, ctx->addr + DECON_VIDOSDxB(win));
0421     } else {
0422         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
0423         writel(val, ctx->addr + DECON_VIDOSDxA(win));
0424 
0425         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
0426                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
0427         writel(val, ctx->addr + DECON_VIDOSDxB(win));
0428     }
0429 
0430     val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
0431         VIDOSD_Wx_ALPHA_B_F(0xff);
0432     writel(val, ctx->addr + DECON_VIDOSDxC(win));
0433 
0434     val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
0435         VIDOSD_Wx_ALPHA_B_F(0x0);
0436     writel(val, ctx->addr + DECON_VIDOSDxD(win));
0437 
0438     writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
0439 
0440     val = dma_addr + pitch * state->src.h;
0441     writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
0442 
0443     if (!(ctx->out_type & IFTYPE_HDMI))
0444         val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
0445             | BIT_VAL(state->crtc.w * cpp, 13, 0);
0446     else
0447         val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
0448             | BIT_VAL(state->crtc.w * cpp, 14, 0);
0449     writel(val, ctx->addr + DECON_VIDW0xADD2(win));
0450 
0451     decon_win_set_pixfmt(ctx, win, fb);
0452 
0453     /* window enable */
0454     decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
0455 }
0456 
0457 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
0458                 struct exynos_drm_plane *plane)
0459 {
0460     struct decon_context *ctx = crtc->ctx;
0461     unsigned int win = plane->index;
0462 
0463     decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
0464 }
0465 
0466 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
0467 {
0468     struct decon_context *ctx = crtc->ctx;
0469     unsigned long flags;
0470 
0471     spin_lock_irqsave(&ctx->vblank_lock, flags);
0472 
0473     decon_shadow_protect(ctx, false);
0474 
0475     decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
0476 
0477     ctx->frame_id = decon_get_frame_count(ctx, true);
0478 
0479     exynos_crtc_handle_event(crtc);
0480 
0481     spin_unlock_irqrestore(&ctx->vblank_lock, flags);
0482 }
0483 
0484 static void decon_swreset(struct decon_context *ctx)
0485 {
0486     unsigned long flags;
0487     u32 val;
0488     int ret;
0489 
0490     writel(0, ctx->addr + DECON_VIDCON0);
0491     readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
0492                ~val & VIDCON0_STOP_STATUS, 12, 20000);
0493 
0494     writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
0495     ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
0496                  ~val & VIDCON0_SWRESET, 12, 20000);
0497 
0498     WARN(ret < 0, "failed to software reset DECON\n");
0499 
0500     spin_lock_irqsave(&ctx->vblank_lock, flags);
0501     ctx->frame_id = 0;
0502     spin_unlock_irqrestore(&ctx->vblank_lock, flags);
0503 
0504     if (!(ctx->out_type & IFTYPE_HDMI))
0505         return;
0506 
0507     writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
0508     decon_set_bits(ctx, DECON_CMU,
0509                CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
0510     writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
0511     writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
0512            ctx->addr + DECON_CRCCTRL);
0513 }
0514 
0515 static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
0516 {
0517     struct decon_context *ctx = crtc->ctx;
0518     int ret;
0519 
0520     ret = pm_runtime_resume_and_get(ctx->dev);
0521     if (ret < 0) {
0522         DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n");
0523         return;
0524     }
0525 
0526     exynos_drm_pipe_clk_enable(crtc, true);
0527 
0528     decon_swreset(ctx);
0529 
0530     decon_commit(ctx->crtc);
0531 }
0532 
0533 static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
0534 {
0535     struct decon_context *ctx = crtc->ctx;
0536     int i;
0537 
0538     if (!(ctx->out_type & I80_HW_TRG))
0539         synchronize_irq(ctx->te_irq);
0540     synchronize_irq(ctx->irq);
0541 
0542     /*
0543      * We need to make sure that all windows are disabled before we
0544      * suspend that connector. Otherwise we might try to scan from
0545      * a destroyed buffer later.
0546      */
0547     for (i = ctx->first_win; i < WINDOWS_NR; i++)
0548         decon_disable_plane(crtc, &ctx->planes[i]);
0549 
0550     decon_swreset(ctx);
0551 
0552     exynos_drm_pipe_clk_enable(crtc, false);
0553 
0554     pm_runtime_put_sync(ctx->dev);
0555 }
0556 
0557 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
0558 {
0559     struct decon_context *ctx = dev_id;
0560 
0561     decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
0562 
0563     return IRQ_HANDLED;
0564 }
0565 
0566 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
0567 {
0568     struct decon_context *ctx = crtc->ctx;
0569     int win, i, ret;
0570 
0571     for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
0572         ret = clk_prepare_enable(ctx->clks[i]);
0573         if (ret < 0)
0574             goto err;
0575     }
0576 
0577     decon_shadow_protect(ctx, true);
0578     for (win = 0; win < WINDOWS_NR; win++)
0579         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
0580     decon_shadow_protect(ctx, false);
0581 
0582     decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
0583 
0584     /* TODO: wait for possible vsync */
0585     msleep(50);
0586 
0587 err:
0588     while (--i >= 0)
0589         clk_disable_unprepare(ctx->clks[i]);
0590 }
0591 
0592 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
0593         const struct drm_display_mode *mode)
0594 {
0595     struct decon_context *ctx = crtc->ctx;
0596 
0597     ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
0598 
0599     if (ctx->irq)
0600         return MODE_OK;
0601 
0602     dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
0603             crtc->i80_mode ? "command" : "video");
0604 
0605     return MODE_BAD;
0606 }
0607 
0608 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
0609     .atomic_enable      = decon_atomic_enable,
0610     .atomic_disable     = decon_atomic_disable,
0611     .enable_vblank      = decon_enable_vblank,
0612     .disable_vblank     = decon_disable_vblank,
0613     .atomic_begin       = decon_atomic_begin,
0614     .update_plane       = decon_update_plane,
0615     .disable_plane      = decon_disable_plane,
0616     .mode_valid     = decon_mode_valid,
0617     .atomic_flush       = decon_atomic_flush,
0618 };
0619 
0620 static int decon_bind(struct device *dev, struct device *master, void *data)
0621 {
0622     struct decon_context *ctx = dev_get_drvdata(dev);
0623     struct drm_device *drm_dev = data;
0624     struct exynos_drm_plane *exynos_plane;
0625     enum exynos_drm_output_type out_type;
0626     unsigned int win;
0627     int ret;
0628 
0629     ctx->drm_dev = drm_dev;
0630 
0631     for (win = ctx->first_win; win < WINDOWS_NR; win++) {
0632         ctx->configs[win].pixel_formats = decon_formats;
0633         ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
0634         ctx->configs[win].zpos = win - ctx->first_win;
0635         ctx->configs[win].type = decon_win_types[win];
0636         ctx->configs[win].capabilities = capabilities[win];
0637 
0638         ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
0639                     &ctx->configs[win]);
0640         if (ret)
0641             return ret;
0642     }
0643 
0644     exynos_plane = &ctx->planes[PRIMARY_WIN];
0645     out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
0646                           : EXYNOS_DISPLAY_TYPE_LCD;
0647     ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
0648             out_type, &decon_crtc_ops, ctx);
0649     if (IS_ERR(ctx->crtc))
0650         return PTR_ERR(ctx->crtc);
0651 
0652     decon_clear_channels(ctx->crtc);
0653 
0654     return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
0655 }
0656 
0657 static void decon_unbind(struct device *dev, struct device *master, void *data)
0658 {
0659     struct decon_context *ctx = dev_get_drvdata(dev);
0660 
0661     decon_atomic_disable(ctx->crtc);
0662 
0663     /* detach this sub driver from iommu mapping if supported. */
0664     exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
0665 }
0666 
0667 static const struct component_ops decon_component_ops = {
0668     .bind   = decon_bind,
0669     .unbind = decon_unbind,
0670 };
0671 
0672 static void decon_handle_vblank(struct decon_context *ctx)
0673 {
0674     u32 frm;
0675 
0676     spin_lock(&ctx->vblank_lock);
0677 
0678     frm = decon_get_frame_count(ctx, true);
0679 
0680     if (frm != ctx->frame_id) {
0681         /* handle only if incremented, take care of wrap-around */
0682         if ((s32)(frm - ctx->frame_id) > 0)
0683             drm_crtc_handle_vblank(&ctx->crtc->base);
0684         ctx->frame_id = frm;
0685     }
0686 
0687     spin_unlock(&ctx->vblank_lock);
0688 }
0689 
0690 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
0691 {
0692     struct decon_context *ctx = dev_id;
0693     u32 val;
0694 
0695     val = readl(ctx->addr + DECON_VIDINTCON1);
0696     val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
0697 
0698     if (val) {
0699         writel(val, ctx->addr + DECON_VIDINTCON1);
0700         if (ctx->out_type & IFTYPE_HDMI) {
0701             val = readl(ctx->addr + DECON_VIDOUTCON0);
0702             val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
0703             if (val ==
0704                 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
0705                 return IRQ_HANDLED;
0706         }
0707         decon_handle_vblank(ctx);
0708     }
0709 
0710     return IRQ_HANDLED;
0711 }
0712 
0713 #ifdef CONFIG_PM
0714 static int exynos5433_decon_suspend(struct device *dev)
0715 {
0716     struct decon_context *ctx = dev_get_drvdata(dev);
0717     int i = ARRAY_SIZE(decon_clks_name);
0718 
0719     while (--i >= 0)
0720         clk_disable_unprepare(ctx->clks[i]);
0721 
0722     return 0;
0723 }
0724 
0725 static int exynos5433_decon_resume(struct device *dev)
0726 {
0727     struct decon_context *ctx = dev_get_drvdata(dev);
0728     int i, ret;
0729 
0730     for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
0731         ret = clk_prepare_enable(ctx->clks[i]);
0732         if (ret < 0)
0733             goto err;
0734     }
0735 
0736     return 0;
0737 
0738 err:
0739     while (--i >= 0)
0740         clk_disable_unprepare(ctx->clks[i]);
0741 
0742     return ret;
0743 }
0744 #endif
0745 
0746 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
0747     SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
0748                NULL)
0749     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0750                      pm_runtime_force_resume)
0751 };
0752 
0753 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
0754     {
0755         .compatible = "samsung,exynos5433-decon",
0756         .data = (void *)I80_HW_TRG
0757     },
0758     {
0759         .compatible = "samsung,exynos5433-decon-tv",
0760         .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
0761     },
0762     {},
0763 };
0764 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
0765 
0766 static int decon_conf_irq(struct decon_context *ctx, const char *name,
0767         irq_handler_t handler, unsigned long int flags)
0768 {
0769     struct platform_device *pdev = to_platform_device(ctx->dev);
0770     int ret, irq = platform_get_irq_byname(pdev, name);
0771 
0772     if (irq < 0) {
0773         switch (irq) {
0774         case -EPROBE_DEFER:
0775             return irq;
0776         case -ENODATA:
0777         case -ENXIO:
0778             return 0;
0779         default:
0780             dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
0781             return irq;
0782         }
0783     }
0784     ret = devm_request_irq(ctx->dev, irq, handler,
0785                    flags | IRQF_NO_AUTOEN, "drm_decon", ctx);
0786     if (ret < 0) {
0787         dev_err(ctx->dev, "IRQ %s request failed\n", name);
0788         return ret;
0789     }
0790 
0791     return irq;
0792 }
0793 
0794 static int exynos5433_decon_probe(struct platform_device *pdev)
0795 {
0796     struct device *dev = &pdev->dev;
0797     struct decon_context *ctx;
0798     int ret;
0799     int i;
0800 
0801     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
0802     if (!ctx)
0803         return -ENOMEM;
0804 
0805     ctx->dev = dev;
0806     ctx->out_type = (unsigned long)of_device_get_match_data(dev);
0807     spin_lock_init(&ctx->vblank_lock);
0808 
0809     if (ctx->out_type & IFTYPE_HDMI)
0810         ctx->first_win = 1;
0811 
0812     for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
0813         struct clk *clk;
0814 
0815         clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
0816         if (IS_ERR(clk))
0817             return PTR_ERR(clk);
0818 
0819         ctx->clks[i] = clk;
0820     }
0821 
0822     ctx->addr = devm_platform_ioremap_resource(pdev, 0);
0823     if (IS_ERR(ctx->addr))
0824         return PTR_ERR(ctx->addr);
0825 
0826     ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
0827     if (ret < 0)
0828         return ret;
0829     ctx->irq_vsync = ret;
0830 
0831     ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
0832     if (ret < 0)
0833         return ret;
0834     ctx->irq_lcd_sys = ret;
0835 
0836     ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
0837             IRQF_TRIGGER_RISING);
0838     if (ret < 0)
0839             return ret;
0840     if (ret) {
0841         ctx->te_irq = ret;
0842         ctx->out_type &= ~I80_HW_TRG;
0843     }
0844 
0845     if (ctx->out_type & I80_HW_TRG) {
0846         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
0847                             "samsung,disp-sysreg");
0848         if (IS_ERR(ctx->sysreg)) {
0849             dev_err(dev, "failed to get system register\n");
0850             return PTR_ERR(ctx->sysreg);
0851         }
0852     }
0853 
0854     platform_set_drvdata(pdev, ctx);
0855 
0856     pm_runtime_enable(dev);
0857 
0858     ret = component_add(dev, &decon_component_ops);
0859     if (ret)
0860         goto err_disable_pm_runtime;
0861 
0862     return 0;
0863 
0864 err_disable_pm_runtime:
0865     pm_runtime_disable(dev);
0866 
0867     return ret;
0868 }
0869 
0870 static int exynos5433_decon_remove(struct platform_device *pdev)
0871 {
0872     pm_runtime_disable(&pdev->dev);
0873 
0874     component_del(&pdev->dev, &decon_component_ops);
0875 
0876     return 0;
0877 }
0878 
0879 struct platform_driver exynos5433_decon_driver = {
0880     .probe      = exynos5433_decon_probe,
0881     .remove     = exynos5433_decon_remove,
0882     .driver     = {
0883         .name   = "exynos5433-decon",
0884         .pm = &exynos5433_decon_pm_ops,
0885         .of_match_table = exynos5433_decon_driver_dt_match,
0886     },
0887 };
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