drm/etnaviv/etnaviv_gpu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2015-2018 Etnaviv Project
0004  */
0005
0006 #ifndef __ETNAVIV_GPU_H__
0007 #define __ETNAVIV_GPU_H__
0008
0009 #include "etnaviv_cmdbuf.h"
0010 #include "etnaviv_gem.h"
0011 #include "etnaviv_mmu.h"
0012 #include "etnaviv_drv.h"
0013
0014 struct etnaviv_gem_submit;
0015 struct etnaviv_vram_mapping;
0016
0017 struct etnaviv_chip_identity {
0018     u32 model;
0019     u32 revision;
0020     u32 product_id;
0021     u32 customer_id;
0022     u32 eco_id;
0023
0024     /* Supported feature fields. */
0025     u32 features;
0026
0027     /* Supported minor feature fields. */
0028     u32 minor_features0;
0029     u32 minor_features1;
0030     u32 minor_features2;
0031     u32 minor_features3;
0032     u32 minor_features4;
0033     u32 minor_features5;
0034     u32 minor_features6;
0035     u32 minor_features7;
0036     u32 minor_features8;
0037     u32 minor_features9;
0038     u32 minor_features10;
0039     u32 minor_features11;
0040
0041     /* Number of streams supported. */
0042     u32 stream_count;
0043
0044     /* Total number of temporary registers per thread. */
0045     u32 register_max;
0046
0047     /* Maximum number of threads. */
0048     u32 thread_count;
0049
0050     /* Number of shader cores. */
0051     u32 shader_core_count;
0052
0053     /* Size of the vertex cache. */
0054     u32 vertex_cache_size;
0055
0056     /* Number of entries in the vertex output buffer. */
0057     u32 vertex_output_buffer_size;
0058
0059     /* Number of pixel pipes. */
0060     u32 pixel_pipes;
0061
0062     /* Number of instructions. */
0063     u32 instruction_count;
0064
0065     /* Number of constants. */
0066     u32 num_constants;
0067
0068     /* Buffer size */
0069     u32 buffer_size;
0070
0071     /* Number of varyings */
0072     u8 varyings_count;
0073 };
0074
0075 enum etnaviv_sec_mode {
0076     ETNA_SEC_NONE = 0,
0077     ETNA_SEC_KERNEL,
0078     ETNA_SEC_TZ
0079 };
0080
0081 struct etnaviv_event {
0082     struct dma_fence *fence;
0083     struct etnaviv_gem_submit *submit;
0084
0085     void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
0086 };
0087
0088 struct etnaviv_cmdbuf_suballoc;
0089 struct regulator;
0090 struct clk;
0091
0092 #define ETNA_NR_EVENTS 30
0093
0094 struct etnaviv_gpu {
0095     struct drm_device *drm;
0096     struct thermal_cooling_device *cooling;
0097     struct device *dev;
0098     struct mutex lock;
0099     struct etnaviv_chip_identity identity;
0100     enum etnaviv_sec_mode sec_mode;
0101     struct workqueue_struct *wq;
0102     struct drm_gpu_scheduler sched;
0103     bool initialized;
0104     bool fe_running;
0105
0106     /* 'ring'-buffer: */
0107     struct etnaviv_cmdbuf buffer;
0108     int exec_state;
0109
0110     /* event management: */
0111     DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
0112     struct etnaviv_event event[ETNA_NR_EVENTS];
0113     struct completion event_free;
0114     spinlock_t event_spinlock;
0115
0116     u32 idle_mask;
0117
0118     /* Fencing support */
0119     struct mutex fence_lock;
0120     struct idr fence_idr;
0121     u32 next_fence;
0122     u32 completed_fence;
0123     wait_queue_head_t fence_event;
0124     u64 fence_context;
0125     spinlock_t fence_spinlock;
0126
0127     /* worker for handling 'sync' points: */
0128     struct work_struct sync_point_work;
0129     int sync_point_event;
0130
0131     /* hang detection */
0132     u32 hangcheck_dma_addr;
0133     u32 hangcheck_fence;
0134
0135     void __iomem *mmio;
0136     int irq;
0137
0138     struct etnaviv_iommu_context *mmu_context;
0139     unsigned int flush_seq;
0140
0141     /* Power Control: */
0142     struct clk *clk_bus;
0143     struct clk *clk_reg;
0144     struct clk *clk_core;
0145     struct clk *clk_shader;
0146
0147     unsigned int freq_scale;
0148     unsigned long base_rate_core;
0149     unsigned long base_rate_shader;
0150 };
0151
0152 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
0153 {
0154     writel(data, gpu->mmio + reg);
0155 }
0156
0157 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
0158 {
0159     return readl(gpu->mmio + reg);
0160 }
0161
0162 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
0163
0164 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
0165 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
0166
0167 #ifdef CONFIG_DEBUG_FS
0168 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
0169 #endif
0170
0171 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
0172 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
0173 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
0174     u32 fence, struct drm_etnaviv_timespec *timeout);
0175 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
0176     struct etnaviv_gem_object *etnaviv_obj,
0177     struct drm_etnaviv_timespec *timeout);
0178 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
0179 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
0180 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
0181 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
0182 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
0183
0184 extern struct platform_driver etnaviv_gpu_driver;
0185
0186 #endif /* __ETNAVIV_GPU_H__ */