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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2015-2018 Etnaviv Project
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/component.h>
0008 #include <linux/delay.h>
0009 #include <linux/dma-fence.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/thermal.h>
0017 
0018 #include "etnaviv_cmdbuf.h"
0019 #include "etnaviv_dump.h"
0020 #include "etnaviv_gpu.h"
0021 #include "etnaviv_gem.h"
0022 #include "etnaviv_mmu.h"
0023 #include "etnaviv_perfmon.h"
0024 #include "etnaviv_sched.h"
0025 #include "common.xml.h"
0026 #include "state.xml.h"
0027 #include "state_hi.xml.h"
0028 #include "cmdstream.xml.h"
0029 
0030 static const struct platform_device_id gpu_ids[] = {
0031     { .name = "etnaviv-gpu,2d" },
0032     { },
0033 };
0034 
0035 /*
0036  * Driver functions:
0037  */
0038 
0039 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
0040 {
0041     struct etnaviv_drm_private *priv = gpu->drm->dev_private;
0042 
0043     switch (param) {
0044     case ETNAVIV_PARAM_GPU_MODEL:
0045         *value = gpu->identity.model;
0046         break;
0047 
0048     case ETNAVIV_PARAM_GPU_REVISION:
0049         *value = gpu->identity.revision;
0050         break;
0051 
0052     case ETNAVIV_PARAM_GPU_FEATURES_0:
0053         *value = gpu->identity.features;
0054         break;
0055 
0056     case ETNAVIV_PARAM_GPU_FEATURES_1:
0057         *value = gpu->identity.minor_features0;
0058         break;
0059 
0060     case ETNAVIV_PARAM_GPU_FEATURES_2:
0061         *value = gpu->identity.minor_features1;
0062         break;
0063 
0064     case ETNAVIV_PARAM_GPU_FEATURES_3:
0065         *value = gpu->identity.minor_features2;
0066         break;
0067 
0068     case ETNAVIV_PARAM_GPU_FEATURES_4:
0069         *value = gpu->identity.minor_features3;
0070         break;
0071 
0072     case ETNAVIV_PARAM_GPU_FEATURES_5:
0073         *value = gpu->identity.minor_features4;
0074         break;
0075 
0076     case ETNAVIV_PARAM_GPU_FEATURES_6:
0077         *value = gpu->identity.minor_features5;
0078         break;
0079 
0080     case ETNAVIV_PARAM_GPU_FEATURES_7:
0081         *value = gpu->identity.minor_features6;
0082         break;
0083 
0084     case ETNAVIV_PARAM_GPU_FEATURES_8:
0085         *value = gpu->identity.minor_features7;
0086         break;
0087 
0088     case ETNAVIV_PARAM_GPU_FEATURES_9:
0089         *value = gpu->identity.minor_features8;
0090         break;
0091 
0092     case ETNAVIV_PARAM_GPU_FEATURES_10:
0093         *value = gpu->identity.minor_features9;
0094         break;
0095 
0096     case ETNAVIV_PARAM_GPU_FEATURES_11:
0097         *value = gpu->identity.minor_features10;
0098         break;
0099 
0100     case ETNAVIV_PARAM_GPU_FEATURES_12:
0101         *value = gpu->identity.minor_features11;
0102         break;
0103 
0104     case ETNAVIV_PARAM_GPU_STREAM_COUNT:
0105         *value = gpu->identity.stream_count;
0106         break;
0107 
0108     case ETNAVIV_PARAM_GPU_REGISTER_MAX:
0109         *value = gpu->identity.register_max;
0110         break;
0111 
0112     case ETNAVIV_PARAM_GPU_THREAD_COUNT:
0113         *value = gpu->identity.thread_count;
0114         break;
0115 
0116     case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
0117         *value = gpu->identity.vertex_cache_size;
0118         break;
0119 
0120     case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
0121         *value = gpu->identity.shader_core_count;
0122         break;
0123 
0124     case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
0125         *value = gpu->identity.pixel_pipes;
0126         break;
0127 
0128     case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
0129         *value = gpu->identity.vertex_output_buffer_size;
0130         break;
0131 
0132     case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
0133         *value = gpu->identity.buffer_size;
0134         break;
0135 
0136     case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
0137         *value = gpu->identity.instruction_count;
0138         break;
0139 
0140     case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
0141         *value = gpu->identity.num_constants;
0142         break;
0143 
0144     case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
0145         *value = gpu->identity.varyings_count;
0146         break;
0147 
0148     case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
0149         if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
0150             *value = ETNAVIV_SOFTPIN_START_ADDRESS;
0151         else
0152             *value = ~0ULL;
0153         break;
0154 
0155     case ETNAVIV_PARAM_GPU_PRODUCT_ID:
0156         *value = gpu->identity.product_id;
0157         break;
0158 
0159     case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
0160         *value = gpu->identity.customer_id;
0161         break;
0162 
0163     case ETNAVIV_PARAM_GPU_ECO_ID:
0164         *value = gpu->identity.eco_id;
0165         break;
0166 
0167     default:
0168         DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
0169         return -EINVAL;
0170     }
0171 
0172     return 0;
0173 }
0174 
0175 
0176 #define etnaviv_is_model_rev(gpu, mod, rev) \
0177     ((gpu)->identity.model == chipModel_##mod && \
0178      (gpu)->identity.revision == rev)
0179 #define etnaviv_field(val, field) \
0180     (((val) & field##__MASK) >> field##__SHIFT)
0181 
0182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
0183 {
0184     if (gpu->identity.minor_features0 &
0185         chipMinorFeatures0_MORE_MINOR_FEATURES) {
0186         u32 specs[4];
0187         unsigned int streams;
0188 
0189         specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
0190         specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
0191         specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
0192         specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
0193 
0194         gpu->identity.stream_count = etnaviv_field(specs[0],
0195                     VIVS_HI_CHIP_SPECS_STREAM_COUNT);
0196         gpu->identity.register_max = etnaviv_field(specs[0],
0197                     VIVS_HI_CHIP_SPECS_REGISTER_MAX);
0198         gpu->identity.thread_count = etnaviv_field(specs[0],
0199                     VIVS_HI_CHIP_SPECS_THREAD_COUNT);
0200         gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
0201                     VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
0202         gpu->identity.shader_core_count = etnaviv_field(specs[0],
0203                     VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
0204         gpu->identity.pixel_pipes = etnaviv_field(specs[0],
0205                     VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
0206         gpu->identity.vertex_output_buffer_size =
0207             etnaviv_field(specs[0],
0208                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
0209 
0210         gpu->identity.buffer_size = etnaviv_field(specs[1],
0211                     VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
0212         gpu->identity.instruction_count = etnaviv_field(specs[1],
0213                     VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
0214         gpu->identity.num_constants = etnaviv_field(specs[1],
0215                     VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
0216 
0217         gpu->identity.varyings_count = etnaviv_field(specs[2],
0218                     VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
0219 
0220         /* This overrides the value from older register if non-zero */
0221         streams = etnaviv_field(specs[3],
0222                     VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
0223         if (streams)
0224             gpu->identity.stream_count = streams;
0225     }
0226 
0227     /* Fill in the stream count if not specified */
0228     if (gpu->identity.stream_count == 0) {
0229         if (gpu->identity.model >= 0x1000)
0230             gpu->identity.stream_count = 4;
0231         else
0232             gpu->identity.stream_count = 1;
0233     }
0234 
0235     /* Convert the register max value */
0236     if (gpu->identity.register_max)
0237         gpu->identity.register_max = 1 << gpu->identity.register_max;
0238     else if (gpu->identity.model == chipModel_GC400)
0239         gpu->identity.register_max = 32;
0240     else
0241         gpu->identity.register_max = 64;
0242 
0243     /* Convert thread count */
0244     if (gpu->identity.thread_count)
0245         gpu->identity.thread_count = 1 << gpu->identity.thread_count;
0246     else if (gpu->identity.model == chipModel_GC400)
0247         gpu->identity.thread_count = 64;
0248     else if (gpu->identity.model == chipModel_GC500 ||
0249          gpu->identity.model == chipModel_GC530)
0250         gpu->identity.thread_count = 128;
0251     else
0252         gpu->identity.thread_count = 256;
0253 
0254     if (gpu->identity.vertex_cache_size == 0)
0255         gpu->identity.vertex_cache_size = 8;
0256 
0257     if (gpu->identity.shader_core_count == 0) {
0258         if (gpu->identity.model >= 0x1000)
0259             gpu->identity.shader_core_count = 2;
0260         else
0261             gpu->identity.shader_core_count = 1;
0262     }
0263 
0264     if (gpu->identity.pixel_pipes == 0)
0265         gpu->identity.pixel_pipes = 1;
0266 
0267     /* Convert virtex buffer size */
0268     if (gpu->identity.vertex_output_buffer_size) {
0269         gpu->identity.vertex_output_buffer_size =
0270             1 << gpu->identity.vertex_output_buffer_size;
0271     } else if (gpu->identity.model == chipModel_GC400) {
0272         if (gpu->identity.revision < 0x4000)
0273             gpu->identity.vertex_output_buffer_size = 512;
0274         else if (gpu->identity.revision < 0x4200)
0275             gpu->identity.vertex_output_buffer_size = 256;
0276         else
0277             gpu->identity.vertex_output_buffer_size = 128;
0278     } else {
0279         gpu->identity.vertex_output_buffer_size = 512;
0280     }
0281 
0282     switch (gpu->identity.instruction_count) {
0283     case 0:
0284         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
0285             gpu->identity.model == chipModel_GC880)
0286             gpu->identity.instruction_count = 512;
0287         else
0288             gpu->identity.instruction_count = 256;
0289         break;
0290 
0291     case 1:
0292         gpu->identity.instruction_count = 1024;
0293         break;
0294 
0295     case 2:
0296         gpu->identity.instruction_count = 2048;
0297         break;
0298 
0299     default:
0300         gpu->identity.instruction_count = 256;
0301         break;
0302     }
0303 
0304     if (gpu->identity.num_constants == 0)
0305         gpu->identity.num_constants = 168;
0306 
0307     if (gpu->identity.varyings_count == 0) {
0308         if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
0309             gpu->identity.varyings_count = 12;
0310         else
0311             gpu->identity.varyings_count = 8;
0312     }
0313 
0314     /*
0315      * For some cores, two varyings are consumed for position, so the
0316      * maximum varying count needs to be reduced by one.
0317      */
0318     if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
0319         etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
0320         etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
0321         etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
0322         etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
0323         etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
0324         etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
0325         etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
0326         etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
0327         etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
0328         etnaviv_is_model_rev(gpu, GC880, 0x5106))
0329         gpu->identity.varyings_count -= 1;
0330 }
0331 
0332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
0333 {
0334     u32 chipIdentity;
0335 
0336     chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
0337 
0338     /* Special case for older graphic cores. */
0339     if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
0340         gpu->identity.model    = chipModel_GC500;
0341         gpu->identity.revision = etnaviv_field(chipIdentity,
0342                      VIVS_HI_CHIP_IDENTITY_REVISION);
0343     } else {
0344         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
0345 
0346         gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
0347         gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
0348         gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
0349 
0350         /*
0351          * Reading these two registers on GC600 rev 0x19 result in a
0352          * unhandled fault: external abort on non-linefetch
0353          */
0354         if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
0355             gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
0356             gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
0357         }
0358 
0359         /*
0360          * !!!! HACK ALERT !!!!
0361          * Because people change device IDs without letting software
0362          * know about it - here is the hack to make it all look the
0363          * same.  Only for GC400 family.
0364          */
0365         if ((gpu->identity.model & 0xff00) == 0x0400 &&
0366             gpu->identity.model != chipModel_GC420) {
0367             gpu->identity.model = gpu->identity.model & 0x0400;
0368         }
0369 
0370         /* Another special case */
0371         if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
0372             u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
0373 
0374             if (chipDate == 0x20080814 && chipTime == 0x12051100) {
0375                 /*
0376                  * This IP has an ECO; put the correct
0377                  * revision in it.
0378                  */
0379                 gpu->identity.revision = 0x1051;
0380             }
0381         }
0382 
0383         /*
0384          * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
0385          * reality it's just a re-branded GC3000. We can identify this
0386          * core by the upper half of the revision register being all 1.
0387          * Fix model/rev here, so all other places can refer to this
0388          * core by its real identity.
0389          */
0390         if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
0391             gpu->identity.model = chipModel_GC3000;
0392             gpu->identity.revision &= 0xffff;
0393         }
0394 
0395         if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
0396             gpu->identity.eco_id = 1;
0397 
0398         if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
0399             gpu->identity.eco_id = 1;
0400     }
0401 
0402     dev_info(gpu->dev, "model: GC%x, revision: %x\n",
0403          gpu->identity.model, gpu->identity.revision);
0404 
0405     gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
0406     /*
0407      * If there is a match in the HWDB, we aren't interested in the
0408      * remaining register values, as they might be wrong.
0409      */
0410     if (etnaviv_fill_identity_from_hwdb(gpu))
0411         return;
0412 
0413     gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
0414 
0415     /* Disable fast clear on GC700. */
0416     if (gpu->identity.model == chipModel_GC700)
0417         gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
0418 
0419     if ((gpu->identity.model == chipModel_GC500 &&
0420          gpu->identity.revision < 2) ||
0421         (gpu->identity.model == chipModel_GC300 &&
0422          gpu->identity.revision < 0x2000)) {
0423 
0424         /*
0425          * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
0426          * registers.
0427          */
0428         gpu->identity.minor_features0 = 0;
0429         gpu->identity.minor_features1 = 0;
0430         gpu->identity.minor_features2 = 0;
0431         gpu->identity.minor_features3 = 0;
0432         gpu->identity.minor_features4 = 0;
0433         gpu->identity.minor_features5 = 0;
0434     } else
0435         gpu->identity.minor_features0 =
0436                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
0437 
0438     if (gpu->identity.minor_features0 &
0439         chipMinorFeatures0_MORE_MINOR_FEATURES) {
0440         gpu->identity.minor_features1 =
0441                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
0442         gpu->identity.minor_features2 =
0443                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
0444         gpu->identity.minor_features3 =
0445                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
0446         gpu->identity.minor_features4 =
0447                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
0448         gpu->identity.minor_features5 =
0449                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
0450     }
0451 
0452     /* GC600 idle register reports zero bits where modules aren't present */
0453     if (gpu->identity.model == chipModel_GC600)
0454         gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
0455                  VIVS_HI_IDLE_STATE_RA |
0456                  VIVS_HI_IDLE_STATE_SE |
0457                  VIVS_HI_IDLE_STATE_PA |
0458                  VIVS_HI_IDLE_STATE_SH |
0459                  VIVS_HI_IDLE_STATE_PE |
0460                  VIVS_HI_IDLE_STATE_DE |
0461                  VIVS_HI_IDLE_STATE_FE;
0462 
0463     etnaviv_hw_specs(gpu);
0464 }
0465 
0466 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
0467 {
0468     gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
0469           VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
0470     gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
0471 }
0472 
0473 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
0474 {
0475     if (gpu->identity.minor_features2 &
0476         chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
0477         clk_set_rate(gpu->clk_core,
0478                  gpu->base_rate_core >> gpu->freq_scale);
0479         clk_set_rate(gpu->clk_shader,
0480                  gpu->base_rate_shader >> gpu->freq_scale);
0481     } else {
0482         unsigned int fscale = 1 << (6 - gpu->freq_scale);
0483         u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
0484 
0485         clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
0486         clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
0487         etnaviv_gpu_load_clock(gpu, clock);
0488     }
0489 }
0490 
0491 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
0492 {
0493     u32 control, idle;
0494     unsigned long timeout;
0495     bool failed = true;
0496 
0497     /* We hope that the GPU resets in under one second */
0498     timeout = jiffies + msecs_to_jiffies(1000);
0499 
0500     while (time_is_after_jiffies(timeout)) {
0501         /* enable clock */
0502         unsigned int fscale = 1 << (6 - gpu->freq_scale);
0503         control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
0504         etnaviv_gpu_load_clock(gpu, control);
0505 
0506         /* isolate the GPU. */
0507         control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
0508         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
0509 
0510         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
0511             gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
0512                       VIVS_MMUv2_AHB_CONTROL_RESET);
0513         } else {
0514             /* set soft reset. */
0515             control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
0516             gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
0517         }
0518 
0519         /* wait for reset. */
0520         usleep_range(10, 20);
0521 
0522         /* reset soft reset bit. */
0523         control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
0524         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
0525 
0526         /* reset GPU isolation. */
0527         control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
0528         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
0529 
0530         /* read idle register. */
0531         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
0532 
0533         /* try resetting again if FE is not idle */
0534         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
0535             dev_dbg(gpu->dev, "FE is not idle\n");
0536             continue;
0537         }
0538 
0539         /* read reset register. */
0540         control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
0541 
0542         /* is the GPU idle? */
0543         if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
0544             ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
0545             dev_dbg(gpu->dev, "GPU is not idle\n");
0546             continue;
0547         }
0548 
0549         /* disable debug registers, as they are not normally needed */
0550         control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
0551         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
0552 
0553         failed = false;
0554         break;
0555     }
0556 
0557     if (failed) {
0558         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
0559         control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
0560 
0561         dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
0562             idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
0563             control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
0564             control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
0565 
0566         return -EBUSY;
0567     }
0568 
0569     /* We rely on the GPU running, so program the clock */
0570     etnaviv_gpu_update_clock(gpu);
0571 
0572     gpu->fe_running = false;
0573     gpu->exec_state = -1;
0574     if (gpu->mmu_context)
0575         etnaviv_iommu_context_put(gpu->mmu_context);
0576     gpu->mmu_context = NULL;
0577 
0578     return 0;
0579 }
0580 
0581 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
0582 {
0583     u32 pmc, ppc;
0584 
0585     /* enable clock gating */
0586     ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
0587     ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
0588 
0589     /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
0590     if (gpu->identity.revision == 0x4301 ||
0591         gpu->identity.revision == 0x4302)
0592         ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
0593 
0594     gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
0595 
0596     pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
0597 
0598     /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
0599     if (gpu->identity.model >= chipModel_GC400 &&
0600         gpu->identity.model != chipModel_GC420 &&
0601         !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
0602         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
0603 
0604     /*
0605      * Disable PE clock gating on revs < 5.0.0.0 when HZ is
0606      * present without a bug fix.
0607      */
0608     if (gpu->identity.revision < 0x5000 &&
0609         gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
0610         !(gpu->identity.minor_features1 &
0611           chipMinorFeatures1_DISABLE_PE_GATING))
0612         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
0613 
0614     if (gpu->identity.revision < 0x5422)
0615         pmc |= BIT(15); /* Unknown bit */
0616 
0617     /* Disable TX clock gating on affected core revisions. */
0618     if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
0619         etnaviv_is_model_rev(gpu, GC2000, 0x5108))
0620         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
0621 
0622     /* Disable SE, RA and TX clock gating on affected core revisions. */
0623     if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
0624         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
0625                VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |
0626                VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
0627 
0628     pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
0629     pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
0630 
0631     gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
0632 }
0633 
0634 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
0635 {
0636     gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
0637     gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
0638           VIVS_FE_COMMAND_CONTROL_ENABLE |
0639           VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
0640 
0641     if (gpu->sec_mode == ETNA_SEC_KERNEL) {
0642         gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
0643               VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
0644               VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
0645     }
0646 
0647     gpu->fe_running = true;
0648 }
0649 
0650 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
0651                       struct etnaviv_iommu_context *context)
0652 {
0653     u16 prefetch;
0654     u32 address;
0655 
0656     /* setup the MMU */
0657     etnaviv_iommu_restore(gpu, context);
0658 
0659     /* Start command processor */
0660     prefetch = etnaviv_buffer_init(gpu);
0661     address = etnaviv_cmdbuf_get_va(&gpu->buffer,
0662                     &gpu->mmu_context->cmdbuf_mapping);
0663 
0664     etnaviv_gpu_start_fe(gpu, address, prefetch);
0665 }
0666 
0667 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
0668 {
0669     /*
0670      * Base value for VIVS_PM_PULSE_EATER register on models where it
0671      * cannot be read, extracted from vivante kernel driver.
0672      */
0673     u32 pulse_eater = 0x01590880;
0674 
0675     if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
0676         etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
0677         pulse_eater |= BIT(23);
0678 
0679     }
0680 
0681     if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
0682         etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
0683         pulse_eater &= ~BIT(16);
0684         pulse_eater |= BIT(17);
0685     }
0686 
0687     if ((gpu->identity.revision > 0x5420) &&
0688         (gpu->identity.features & chipFeatures_PIPE_3D))
0689     {
0690         /* Performance fix: disable internal DFS */
0691         pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
0692         pulse_eater |= BIT(18);
0693     }
0694 
0695     gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
0696 }
0697 
0698 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
0699 {
0700     if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
0701          etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
0702         gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
0703         u32 mc_memory_debug;
0704 
0705         mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
0706 
0707         if (gpu->identity.revision == 0x5007)
0708             mc_memory_debug |= 0x0c;
0709         else
0710             mc_memory_debug |= 0x08;
0711 
0712         gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
0713     }
0714 
0715     /* enable module-level clock gating */
0716     etnaviv_gpu_enable_mlcg(gpu);
0717 
0718     /*
0719      * Update GPU AXI cache atttribute to "cacheable, no allocate".
0720      * This is necessary to prevent the iMX6 SoC locking up.
0721      */
0722     gpu_write(gpu, VIVS_HI_AXI_CONFIG,
0723           VIVS_HI_AXI_CONFIG_AWCACHE(2) |
0724           VIVS_HI_AXI_CONFIG_ARCACHE(2));
0725 
0726     /* GC2000 rev 5108 needs a special bus config */
0727     if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
0728         u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
0729         bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
0730                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
0731         bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
0732                   VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
0733         gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
0734     }
0735 
0736     if (gpu->sec_mode == ETNA_SEC_KERNEL) {
0737         u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
0738         val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
0739         gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
0740     }
0741 
0742     /* setup the pulse eater */
0743     etnaviv_gpu_setup_pulse_eater(gpu);
0744 
0745     gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
0746 }
0747 
0748 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
0749 {
0750     struct etnaviv_drm_private *priv = gpu->drm->dev_private;
0751     dma_addr_t cmdbuf_paddr;
0752     int ret, i;
0753 
0754     ret = pm_runtime_get_sync(gpu->dev);
0755     if (ret < 0) {
0756         dev_err(gpu->dev, "Failed to enable GPU power domain\n");
0757         goto pm_put;
0758     }
0759 
0760     etnaviv_hw_identify(gpu);
0761 
0762     if (gpu->identity.model == 0) {
0763         dev_err(gpu->dev, "Unknown GPU model\n");
0764         ret = -ENXIO;
0765         goto fail;
0766     }
0767 
0768     /* Exclude VG cores with FE2.0 */
0769     if (gpu->identity.features & chipFeatures_PIPE_VG &&
0770         gpu->identity.features & chipFeatures_FE20) {
0771         dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
0772         ret = -ENXIO;
0773         goto fail;
0774     }
0775 
0776     /*
0777      * On cores with security features supported, we claim control over the
0778      * security states.
0779      */
0780     if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
0781         (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
0782         gpu->sec_mode = ETNA_SEC_KERNEL;
0783 
0784     ret = etnaviv_hw_reset(gpu);
0785     if (ret) {
0786         dev_err(gpu->dev, "GPU reset failed\n");
0787         goto fail;
0788     }
0789 
0790     ret = etnaviv_iommu_global_init(gpu);
0791     if (ret)
0792         goto fail;
0793 
0794     /*
0795      * If the GPU is part of a system with DMA addressing limitations,
0796      * request pages for our SHM backend buffers from the DMA32 zone to
0797      * hopefully avoid performance killing SWIOTLB bounce buffering.
0798      */
0799     if (dma_addressing_limited(gpu->dev))
0800         priv->shm_gfp_mask |= GFP_DMA32;
0801 
0802     /* Create buffer: */
0803     ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
0804                   PAGE_SIZE);
0805     if (ret) {
0806         dev_err(gpu->dev, "could not create command buffer\n");
0807         goto fail;
0808     }
0809 
0810     /*
0811      * Set the GPU linear window to cover the cmdbuf region, as the GPU
0812      * won't be able to start execution otherwise. The alignment to 128M is
0813      * chosen arbitrarily but helps in debugging, as the MMU offset
0814      * calculations are much more straight forward this way.
0815      *
0816      * On MC1.0 cores the linear window offset is ignored by the TS engine,
0817      * leading to inconsistent memory views. Avoid using the offset on those
0818      * cores if possible, otherwise disable the TS feature.
0819      */
0820     cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
0821 
0822     if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
0823         (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
0824         if (cmdbuf_paddr >= SZ_2G)
0825             priv->mmu_global->memory_base = SZ_2G;
0826         else
0827             priv->mmu_global->memory_base = cmdbuf_paddr;
0828     } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
0829         dev_info(gpu->dev,
0830              "Need to move linear window on MC1.0, disabling TS\n");
0831         gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
0832         priv->mmu_global->memory_base = SZ_2G;
0833     }
0834 
0835     /* Setup event management */
0836     spin_lock_init(&gpu->event_spinlock);
0837     init_completion(&gpu->event_free);
0838     bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
0839     for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
0840         complete(&gpu->event_free);
0841 
0842     /* Now program the hardware */
0843     mutex_lock(&gpu->lock);
0844     etnaviv_gpu_hw_init(gpu);
0845     mutex_unlock(&gpu->lock);
0846 
0847     pm_runtime_mark_last_busy(gpu->dev);
0848     pm_runtime_put_autosuspend(gpu->dev);
0849 
0850     gpu->initialized = true;
0851 
0852     return 0;
0853 
0854 fail:
0855     pm_runtime_mark_last_busy(gpu->dev);
0856 pm_put:
0857     pm_runtime_put_autosuspend(gpu->dev);
0858 
0859     return ret;
0860 }
0861 
0862 #ifdef CONFIG_DEBUG_FS
0863 struct dma_debug {
0864     u32 address[2];
0865     u32 state[2];
0866 };
0867 
0868 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
0869 {
0870     u32 i;
0871 
0872     debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
0873     debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
0874 
0875     for (i = 0; i < 500; i++) {
0876         debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
0877         debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
0878 
0879         if (debug->address[0] != debug->address[1])
0880             break;
0881 
0882         if (debug->state[0] != debug->state[1])
0883             break;
0884     }
0885 }
0886 
0887 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
0888 {
0889     struct dma_debug debug;
0890     u32 dma_lo, dma_hi, axi, idle;
0891     int ret;
0892 
0893     seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
0894 
0895     ret = pm_runtime_get_sync(gpu->dev);
0896     if (ret < 0)
0897         goto pm_put;
0898 
0899     dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
0900     dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
0901     axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
0902     idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
0903 
0904     verify_dma(gpu, &debug);
0905 
0906     seq_puts(m, "\tidentity\n");
0907     seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
0908     seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
0909     seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
0910     seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
0911     seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
0912 
0913     seq_puts(m, "\tfeatures\n");
0914     seq_printf(m, "\t major_features: 0x%08x\n",
0915            gpu->identity.features);
0916     seq_printf(m, "\t minor_features0: 0x%08x\n",
0917            gpu->identity.minor_features0);
0918     seq_printf(m, "\t minor_features1: 0x%08x\n",
0919            gpu->identity.minor_features1);
0920     seq_printf(m, "\t minor_features2: 0x%08x\n",
0921            gpu->identity.minor_features2);
0922     seq_printf(m, "\t minor_features3: 0x%08x\n",
0923            gpu->identity.minor_features3);
0924     seq_printf(m, "\t minor_features4: 0x%08x\n",
0925            gpu->identity.minor_features4);
0926     seq_printf(m, "\t minor_features5: 0x%08x\n",
0927            gpu->identity.minor_features5);
0928     seq_printf(m, "\t minor_features6: 0x%08x\n",
0929            gpu->identity.minor_features6);
0930     seq_printf(m, "\t minor_features7: 0x%08x\n",
0931            gpu->identity.minor_features7);
0932     seq_printf(m, "\t minor_features8: 0x%08x\n",
0933            gpu->identity.minor_features8);
0934     seq_printf(m, "\t minor_features9: 0x%08x\n",
0935            gpu->identity.minor_features9);
0936     seq_printf(m, "\t minor_features10: 0x%08x\n",
0937            gpu->identity.minor_features10);
0938     seq_printf(m, "\t minor_features11: 0x%08x\n",
0939            gpu->identity.minor_features11);
0940 
0941     seq_puts(m, "\tspecs\n");
0942     seq_printf(m, "\t stream_count:  %d\n",
0943             gpu->identity.stream_count);
0944     seq_printf(m, "\t register_max: %d\n",
0945             gpu->identity.register_max);
0946     seq_printf(m, "\t thread_count: %d\n",
0947             gpu->identity.thread_count);
0948     seq_printf(m, "\t vertex_cache_size: %d\n",
0949             gpu->identity.vertex_cache_size);
0950     seq_printf(m, "\t shader_core_count: %d\n",
0951             gpu->identity.shader_core_count);
0952     seq_printf(m, "\t pixel_pipes: %d\n",
0953             gpu->identity.pixel_pipes);
0954     seq_printf(m, "\t vertex_output_buffer_size: %d\n",
0955             gpu->identity.vertex_output_buffer_size);
0956     seq_printf(m, "\t buffer_size: %d\n",
0957             gpu->identity.buffer_size);
0958     seq_printf(m, "\t instruction_count: %d\n",
0959             gpu->identity.instruction_count);
0960     seq_printf(m, "\t num_constants: %d\n",
0961             gpu->identity.num_constants);
0962     seq_printf(m, "\t varyings_count: %d\n",
0963             gpu->identity.varyings_count);
0964 
0965     seq_printf(m, "\taxi: 0x%08x\n", axi);
0966     seq_printf(m, "\tidle: 0x%08x\n", idle);
0967     idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
0968     if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
0969         seq_puts(m, "\t FE is not idle\n");
0970     if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
0971         seq_puts(m, "\t DE is not idle\n");
0972     if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
0973         seq_puts(m, "\t PE is not idle\n");
0974     if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
0975         seq_puts(m, "\t SH is not idle\n");
0976     if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
0977         seq_puts(m, "\t PA is not idle\n");
0978     if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
0979         seq_puts(m, "\t SE is not idle\n");
0980     if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
0981         seq_puts(m, "\t RA is not idle\n");
0982     if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
0983         seq_puts(m, "\t TX is not idle\n");
0984     if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
0985         seq_puts(m, "\t VG is not idle\n");
0986     if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
0987         seq_puts(m, "\t IM is not idle\n");
0988     if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
0989         seq_puts(m, "\t FP is not idle\n");
0990     if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
0991         seq_puts(m, "\t TS is not idle\n");
0992     if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
0993         seq_puts(m, "\t BL is not idle\n");
0994     if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
0995         seq_puts(m, "\t ASYNCFE is not idle\n");
0996     if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
0997         seq_puts(m, "\t MC is not idle\n");
0998     if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
0999         seq_puts(m, "\t PPA is not idle\n");
1000     if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1001         seq_puts(m, "\t WD is not idle\n");
1002     if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1003         seq_puts(m, "\t NN is not idle\n");
1004     if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1005         seq_puts(m, "\t TP is not idle\n");
1006     if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1007         seq_puts(m, "\t AXI low power mode\n");
1008 
1009     if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1010         u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1011         u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1012         u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1013 
1014         seq_puts(m, "\tMC\n");
1015         seq_printf(m, "\t read0: 0x%08x\n", read0);
1016         seq_printf(m, "\t read1: 0x%08x\n", read1);
1017         seq_printf(m, "\t write: 0x%08x\n", write);
1018     }
1019 
1020     seq_puts(m, "\tDMA ");
1021 
1022     if (debug.address[0] == debug.address[1] &&
1023         debug.state[0] == debug.state[1]) {
1024         seq_puts(m, "seems to be stuck\n");
1025     } else if (debug.address[0] == debug.address[1]) {
1026         seq_puts(m, "address is constant\n");
1027     } else {
1028         seq_puts(m, "is running\n");
1029     }
1030 
1031     seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1032     seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1033     seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1034     seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1035     seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1036            dma_lo, dma_hi);
1037 
1038     ret = 0;
1039 
1040     pm_runtime_mark_last_busy(gpu->dev);
1041 pm_put:
1042     pm_runtime_put_autosuspend(gpu->dev);
1043 
1044     return ret;
1045 }
1046 #endif
1047 
1048 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
1049 {
1050     unsigned int i;
1051 
1052     dev_err(gpu->dev, "recover hung GPU!\n");
1053 
1054     if (pm_runtime_get_sync(gpu->dev) < 0)
1055         goto pm_put;
1056 
1057     mutex_lock(&gpu->lock);
1058 
1059     etnaviv_hw_reset(gpu);
1060 
1061     /* complete all events, the GPU won't do it after the reset */
1062     spin_lock(&gpu->event_spinlock);
1063     for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1064         complete(&gpu->event_free);
1065     bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1066     spin_unlock(&gpu->event_spinlock);
1067 
1068     etnaviv_gpu_hw_init(gpu);
1069 
1070     mutex_unlock(&gpu->lock);
1071     pm_runtime_mark_last_busy(gpu->dev);
1072 pm_put:
1073     pm_runtime_put_autosuspend(gpu->dev);
1074 }
1075 
1076 /* fence object management */
1077 struct etnaviv_fence {
1078     struct etnaviv_gpu *gpu;
1079     struct dma_fence base;
1080 };
1081 
1082 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1083 {
1084     return container_of(fence, struct etnaviv_fence, base);
1085 }
1086 
1087 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1088 {
1089     return "etnaviv";
1090 }
1091 
1092 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1093 {
1094     struct etnaviv_fence *f = to_etnaviv_fence(fence);
1095 
1096     return dev_name(f->gpu->dev);
1097 }
1098 
1099 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1100 {
1101     struct etnaviv_fence *f = to_etnaviv_fence(fence);
1102 
1103     return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1104 }
1105 
1106 static void etnaviv_fence_release(struct dma_fence *fence)
1107 {
1108     struct etnaviv_fence *f = to_etnaviv_fence(fence);
1109 
1110     kfree_rcu(f, base.rcu);
1111 }
1112 
1113 static const struct dma_fence_ops etnaviv_fence_ops = {
1114     .get_driver_name = etnaviv_fence_get_driver_name,
1115     .get_timeline_name = etnaviv_fence_get_timeline_name,
1116     .signaled = etnaviv_fence_signaled,
1117     .release = etnaviv_fence_release,
1118 };
1119 
1120 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1121 {
1122     struct etnaviv_fence *f;
1123 
1124     /*
1125      * GPU lock must already be held, otherwise fence completion order might
1126      * not match the seqno order assigned here.
1127      */
1128     lockdep_assert_held(&gpu->lock);
1129 
1130     f = kzalloc(sizeof(*f), GFP_KERNEL);
1131     if (!f)
1132         return NULL;
1133 
1134     f->gpu = gpu;
1135 
1136     dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1137                gpu->fence_context, ++gpu->next_fence);
1138 
1139     return &f->base;
1140 }
1141 
1142 /* returns true if fence a comes after fence b */
1143 static inline bool fence_after(u32 a, u32 b)
1144 {
1145     return (s32)(a - b) > 0;
1146 }
1147 
1148 /*
1149  * event management:
1150  */
1151 
1152 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1153     unsigned int *events)
1154 {
1155     unsigned long timeout = msecs_to_jiffies(10 * 10000);
1156     unsigned i, acquired = 0;
1157 
1158     for (i = 0; i < nr_events; i++) {
1159         unsigned long ret;
1160 
1161         ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1162 
1163         if (!ret) {
1164             dev_err(gpu->dev, "wait_for_completion_timeout failed");
1165             goto out;
1166         }
1167 
1168         acquired++;
1169         timeout = ret;
1170     }
1171 
1172     spin_lock(&gpu->event_spinlock);
1173 
1174     for (i = 0; i < nr_events; i++) {
1175         int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1176 
1177         events[i] = event;
1178         memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1179         set_bit(event, gpu->event_bitmap);
1180     }
1181 
1182     spin_unlock(&gpu->event_spinlock);
1183 
1184     return 0;
1185 
1186 out:
1187     for (i = 0; i < acquired; i++)
1188         complete(&gpu->event_free);
1189 
1190     return -EBUSY;
1191 }
1192 
1193 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1194 {
1195     if (!test_bit(event, gpu->event_bitmap)) {
1196         dev_warn(gpu->dev, "event %u is already marked as free",
1197              event);
1198     } else {
1199         clear_bit(event, gpu->event_bitmap);
1200         complete(&gpu->event_free);
1201     }
1202 }
1203 
1204 /*
1205  * Cmdstream submission/retirement:
1206  */
1207 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1208     u32 id, struct drm_etnaviv_timespec *timeout)
1209 {
1210     struct dma_fence *fence;
1211     int ret;
1212 
1213     /*
1214      * Look up the fence and take a reference. We might still find a fence
1215      * whose refcount has already dropped to zero. dma_fence_get_rcu
1216      * pretends we didn't find a fence in that case.
1217      */
1218     rcu_read_lock();
1219     fence = idr_find(&gpu->fence_idr, id);
1220     if (fence)
1221         fence = dma_fence_get_rcu(fence);
1222     rcu_read_unlock();
1223 
1224     if (!fence)
1225         return 0;
1226 
1227     if (!timeout) {
1228         /* No timeout was requested: just test for completion */
1229         ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1230     } else {
1231         unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1232 
1233         ret = dma_fence_wait_timeout(fence, true, remaining);
1234         if (ret == 0)
1235             ret = -ETIMEDOUT;
1236         else if (ret != -ERESTARTSYS)
1237             ret = 0;
1238 
1239     }
1240 
1241     dma_fence_put(fence);
1242     return ret;
1243 }
1244 
1245 /*
1246  * Wait for an object to become inactive.  This, on it's own, is not race
1247  * free: the object is moved by the scheduler off the active list, and
1248  * then the iova is put.  Moreover, the object could be re-submitted just
1249  * after we notice that it's become inactive.
1250  *
1251  * Although the retirement happens under the gpu lock, we don't want to hold
1252  * that lock in this function while waiting.
1253  */
1254 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1255     struct etnaviv_gem_object *etnaviv_obj,
1256     struct drm_etnaviv_timespec *timeout)
1257 {
1258     unsigned long remaining;
1259     long ret;
1260 
1261     if (!timeout)
1262         return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1263 
1264     remaining = etnaviv_timeout_to_jiffies(timeout);
1265 
1266     ret = wait_event_interruptible_timeout(gpu->fence_event,
1267                            !is_active(etnaviv_obj),
1268                            remaining);
1269     if (ret > 0)
1270         return 0;
1271     else if (ret == -ERESTARTSYS)
1272         return -ERESTARTSYS;
1273     else
1274         return -ETIMEDOUT;
1275 }
1276 
1277 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1278     struct etnaviv_event *event, unsigned int flags)
1279 {
1280     const struct etnaviv_gem_submit *submit = event->submit;
1281     unsigned int i;
1282 
1283     for (i = 0; i < submit->nr_pmrs; i++) {
1284         const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1285 
1286         if (pmr->flags == flags)
1287             etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1288     }
1289 }
1290 
1291 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1292     struct etnaviv_event *event)
1293 {
1294     u32 val;
1295 
1296     /* disable clock gating */
1297     val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1298     val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1299     gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1300 
1301     /* enable debug register */
1302     val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1303     val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1304     gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1305 
1306     sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1307 }
1308 
1309 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1310     struct etnaviv_event *event)
1311 {
1312     const struct etnaviv_gem_submit *submit = event->submit;
1313     unsigned int i;
1314     u32 val;
1315 
1316     sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1317 
1318     for (i = 0; i < submit->nr_pmrs; i++) {
1319         const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1320 
1321         *pmr->bo_vma = pmr->sequence;
1322     }
1323 
1324     /* disable debug register */
1325     val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1326     val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1327     gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1328 
1329     /* enable clock gating */
1330     val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1331     val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1332     gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1333 }
1334 
1335 
1336 /* add bo's to gpu's ring, and kick gpu: */
1337 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1338 {
1339     struct etnaviv_gpu *gpu = submit->gpu;
1340     struct dma_fence *gpu_fence;
1341     unsigned int i, nr_events = 1, event[3];
1342     int ret;
1343 
1344     if (!submit->runtime_resumed) {
1345         ret = pm_runtime_get_sync(gpu->dev);
1346         if (ret < 0) {
1347             pm_runtime_put_noidle(gpu->dev);
1348             return NULL;
1349         }
1350         submit->runtime_resumed = true;
1351     }
1352 
1353     /*
1354      * if there are performance monitor requests we need to have
1355      * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1356      *   requests.
1357      * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1358      *   and update the sequence number for userspace.
1359      */
1360     if (submit->nr_pmrs)
1361         nr_events = 3;
1362 
1363     ret = event_alloc(gpu, nr_events, event);
1364     if (ret) {
1365         DRM_ERROR("no free events\n");
1366         pm_runtime_put_noidle(gpu->dev);
1367         return NULL;
1368     }
1369 
1370     mutex_lock(&gpu->lock);
1371 
1372     gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1373     if (!gpu_fence) {
1374         for (i = 0; i < nr_events; i++)
1375             event_free(gpu, event[i]);
1376 
1377         goto out_unlock;
1378     }
1379 
1380     if (!gpu->fe_running)
1381         etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1382 
1383     if (submit->prev_mmu_context)
1384         etnaviv_iommu_context_put(submit->prev_mmu_context);
1385     submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1386 
1387     if (submit->nr_pmrs) {
1388         gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1389         kref_get(&submit->refcount);
1390         gpu->event[event[1]].submit = submit;
1391         etnaviv_sync_point_queue(gpu, event[1]);
1392     }
1393 
1394     gpu->event[event[0]].fence = gpu_fence;
1395     submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1396     etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1397                  event[0], &submit->cmdbuf);
1398 
1399     if (submit->nr_pmrs) {
1400         gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1401         kref_get(&submit->refcount);
1402         gpu->event[event[2]].submit = submit;
1403         etnaviv_sync_point_queue(gpu, event[2]);
1404     }
1405 
1406 out_unlock:
1407     mutex_unlock(&gpu->lock);
1408 
1409     return gpu_fence;
1410 }
1411 
1412 static void sync_point_worker(struct work_struct *work)
1413 {
1414     struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1415                            sync_point_work);
1416     struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1417     u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1418 
1419     event->sync_point(gpu, event);
1420     etnaviv_submit_put(event->submit);
1421     event_free(gpu, gpu->sync_point_event);
1422 
1423     /* restart FE last to avoid GPU and IRQ racing against this worker */
1424     etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1425 }
1426 
1427 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1428 {
1429     u32 status_reg, status;
1430     int i;
1431 
1432     if (gpu->sec_mode == ETNA_SEC_NONE)
1433         status_reg = VIVS_MMUv2_STATUS;
1434     else
1435         status_reg = VIVS_MMUv2_SEC_STATUS;
1436 
1437     status = gpu_read(gpu, status_reg);
1438     dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1439 
1440     for (i = 0; i < 4; i++) {
1441         u32 address_reg;
1442 
1443         if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1444             continue;
1445 
1446         if (gpu->sec_mode == ETNA_SEC_NONE)
1447             address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1448         else
1449             address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1450 
1451         dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1452                     gpu_read(gpu, address_reg));
1453     }
1454 }
1455 
1456 static irqreturn_t irq_handler(int irq, void *data)
1457 {
1458     struct etnaviv_gpu *gpu = data;
1459     irqreturn_t ret = IRQ_NONE;
1460 
1461     u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1462 
1463     if (intr != 0) {
1464         int event;
1465 
1466         pm_runtime_mark_last_busy(gpu->dev);
1467 
1468         dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1469 
1470         if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1471             dev_err(gpu->dev, "AXI bus error\n");
1472             intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1473         }
1474 
1475         if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1476             dump_mmu_fault(gpu);
1477             intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1478         }
1479 
1480         while ((event = ffs(intr)) != 0) {
1481             struct dma_fence *fence;
1482 
1483             event -= 1;
1484 
1485             intr &= ~(1 << event);
1486 
1487             dev_dbg(gpu->dev, "event %u\n", event);
1488 
1489             if (gpu->event[event].sync_point) {
1490                 gpu->sync_point_event = event;
1491                 queue_work(gpu->wq, &gpu->sync_point_work);
1492             }
1493 
1494             fence = gpu->event[event].fence;
1495             if (!fence)
1496                 continue;
1497 
1498             gpu->event[event].fence = NULL;
1499 
1500             /*
1501              * Events can be processed out of order.  Eg,
1502              * - allocate and queue event 0
1503              * - allocate event 1
1504              * - event 0 completes, we process it
1505              * - allocate and queue event 0
1506              * - event 1 and event 0 complete
1507              * we can end up processing event 0 first, then 1.
1508              */
1509             if (fence_after(fence->seqno, gpu->completed_fence))
1510                 gpu->completed_fence = fence->seqno;
1511             dma_fence_signal(fence);
1512 
1513             event_free(gpu, event);
1514         }
1515 
1516         ret = IRQ_HANDLED;
1517     }
1518 
1519     return ret;
1520 }
1521 
1522 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1523 {
1524     int ret;
1525 
1526     ret = clk_prepare_enable(gpu->clk_reg);
1527     if (ret)
1528         return ret;
1529 
1530     ret = clk_prepare_enable(gpu->clk_bus);
1531     if (ret)
1532         goto disable_clk_reg;
1533 
1534     ret = clk_prepare_enable(gpu->clk_core);
1535     if (ret)
1536         goto disable_clk_bus;
1537 
1538     ret = clk_prepare_enable(gpu->clk_shader);
1539     if (ret)
1540         goto disable_clk_core;
1541 
1542     return 0;
1543 
1544 disable_clk_core:
1545     clk_disable_unprepare(gpu->clk_core);
1546 disable_clk_bus:
1547     clk_disable_unprepare(gpu->clk_bus);
1548 disable_clk_reg:
1549     clk_disable_unprepare(gpu->clk_reg);
1550 
1551     return ret;
1552 }
1553 
1554 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1555 {
1556     clk_disable_unprepare(gpu->clk_shader);
1557     clk_disable_unprepare(gpu->clk_core);
1558     clk_disable_unprepare(gpu->clk_bus);
1559     clk_disable_unprepare(gpu->clk_reg);
1560 
1561     return 0;
1562 }
1563 
1564 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1565 {
1566     unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1567 
1568     do {
1569         u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1570 
1571         if ((idle & gpu->idle_mask) == gpu->idle_mask)
1572             return 0;
1573 
1574         if (time_is_before_jiffies(timeout)) {
1575             dev_warn(gpu->dev,
1576                  "timed out waiting for idle: idle=0x%x\n",
1577                  idle);
1578             return -ETIMEDOUT;
1579         }
1580 
1581         udelay(5);
1582     } while (1);
1583 }
1584 
1585 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1586 {
1587     if (gpu->initialized && gpu->fe_running) {
1588         /* Replace the last WAIT with END */
1589         mutex_lock(&gpu->lock);
1590         etnaviv_buffer_end(gpu);
1591         mutex_unlock(&gpu->lock);
1592 
1593         /*
1594          * We know that only the FE is busy here, this should
1595          * happen quickly (as the WAIT is only 200 cycles).  If
1596          * we fail, just warn and continue.
1597          */
1598         etnaviv_gpu_wait_idle(gpu, 100);
1599 
1600         gpu->fe_running = false;
1601     }
1602 
1603     gpu->exec_state = -1;
1604 
1605     return etnaviv_gpu_clk_disable(gpu);
1606 }
1607 
1608 #ifdef CONFIG_PM
1609 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1610 {
1611     int ret;
1612 
1613     ret = mutex_lock_killable(&gpu->lock);
1614     if (ret)
1615         return ret;
1616 
1617     etnaviv_gpu_update_clock(gpu);
1618     etnaviv_gpu_hw_init(gpu);
1619 
1620     mutex_unlock(&gpu->lock);
1621 
1622     return 0;
1623 }
1624 #endif
1625 
1626 static int
1627 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1628                   unsigned long *state)
1629 {
1630     *state = 6;
1631 
1632     return 0;
1633 }
1634 
1635 static int
1636 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1637                   unsigned long *state)
1638 {
1639     struct etnaviv_gpu *gpu = cdev->devdata;
1640 
1641     *state = gpu->freq_scale;
1642 
1643     return 0;
1644 }
1645 
1646 static int
1647 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1648                   unsigned long state)
1649 {
1650     struct etnaviv_gpu *gpu = cdev->devdata;
1651 
1652     mutex_lock(&gpu->lock);
1653     gpu->freq_scale = state;
1654     if (!pm_runtime_suspended(gpu->dev))
1655         etnaviv_gpu_update_clock(gpu);
1656     mutex_unlock(&gpu->lock);
1657 
1658     return 0;
1659 }
1660 
1661 static const struct thermal_cooling_device_ops cooling_ops = {
1662     .get_max_state = etnaviv_gpu_cooling_get_max_state,
1663     .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1664     .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1665 };
1666 
1667 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1668     void *data)
1669 {
1670     struct drm_device *drm = data;
1671     struct etnaviv_drm_private *priv = drm->dev_private;
1672     struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1673     int ret;
1674 
1675     if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1676         gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1677                 (char *)dev_name(dev), gpu, &cooling_ops);
1678         if (IS_ERR(gpu->cooling))
1679             return PTR_ERR(gpu->cooling);
1680     }
1681 
1682     gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1683     if (!gpu->wq) {
1684         ret = -ENOMEM;
1685         goto out_thermal;
1686     }
1687 
1688     ret = etnaviv_sched_init(gpu);
1689     if (ret)
1690         goto out_workqueue;
1691 
1692 #ifdef CONFIG_PM
1693     ret = pm_runtime_get_sync(gpu->dev);
1694 #else
1695     ret = etnaviv_gpu_clk_enable(gpu);
1696 #endif
1697     if (ret < 0)
1698         goto out_sched;
1699 
1700 
1701     gpu->drm = drm;
1702     gpu->fence_context = dma_fence_context_alloc(1);
1703     idr_init(&gpu->fence_idr);
1704     spin_lock_init(&gpu->fence_spinlock);
1705 
1706     INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1707     init_waitqueue_head(&gpu->fence_event);
1708 
1709     priv->gpu[priv->num_gpus++] = gpu;
1710 
1711     pm_runtime_mark_last_busy(gpu->dev);
1712     pm_runtime_put_autosuspend(gpu->dev);
1713 
1714     return 0;
1715 
1716 out_sched:
1717     etnaviv_sched_fini(gpu);
1718 
1719 out_workqueue:
1720     destroy_workqueue(gpu->wq);
1721 
1722 out_thermal:
1723     if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1724         thermal_cooling_device_unregister(gpu->cooling);
1725 
1726     return ret;
1727 }
1728 
1729 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1730     void *data)
1731 {
1732     struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1733 
1734     DBG("%s", dev_name(gpu->dev));
1735 
1736     destroy_workqueue(gpu->wq);
1737 
1738     etnaviv_sched_fini(gpu);
1739 
1740 #ifdef CONFIG_PM
1741     pm_runtime_get_sync(gpu->dev);
1742     pm_runtime_put_sync_suspend(gpu->dev);
1743 #else
1744     etnaviv_gpu_hw_suspend(gpu);
1745 #endif
1746 
1747     if (gpu->mmu_context)
1748         etnaviv_iommu_context_put(gpu->mmu_context);
1749 
1750     if (gpu->initialized) {
1751         etnaviv_cmdbuf_free(&gpu->buffer);
1752         etnaviv_iommu_global_fini(gpu);
1753         gpu->initialized = false;
1754     }
1755 
1756     gpu->drm = NULL;
1757     idr_destroy(&gpu->fence_idr);
1758 
1759     if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1760         thermal_cooling_device_unregister(gpu->cooling);
1761     gpu->cooling = NULL;
1762 }
1763 
1764 static const struct component_ops gpu_ops = {
1765     .bind = etnaviv_gpu_bind,
1766     .unbind = etnaviv_gpu_unbind,
1767 };
1768 
1769 static const struct of_device_id etnaviv_gpu_match[] = {
1770     {
1771         .compatible = "vivante,gc"
1772     },
1773     { /* sentinel */ }
1774 };
1775 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1776 
1777 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1778 {
1779     struct device *dev = &pdev->dev;
1780     struct etnaviv_gpu *gpu;
1781     int err;
1782 
1783     gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1784     if (!gpu)
1785         return -ENOMEM;
1786 
1787     gpu->dev = &pdev->dev;
1788     mutex_init(&gpu->lock);
1789     mutex_init(&gpu->fence_lock);
1790 
1791     /* Map registers: */
1792     gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1793     if (IS_ERR(gpu->mmio))
1794         return PTR_ERR(gpu->mmio);
1795 
1796     /* Get Interrupt: */
1797     gpu->irq = platform_get_irq(pdev, 0);
1798     if (gpu->irq < 0)
1799         return gpu->irq;
1800 
1801     err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1802                    dev_name(gpu->dev), gpu);
1803     if (err) {
1804         dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1805         return err;
1806     }
1807 
1808     /* Get Clocks: */
1809     gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1810     DBG("clk_reg: %p", gpu->clk_reg);
1811     if (IS_ERR(gpu->clk_reg))
1812         return PTR_ERR(gpu->clk_reg);
1813 
1814     gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1815     DBG("clk_bus: %p", gpu->clk_bus);
1816     if (IS_ERR(gpu->clk_bus))
1817         return PTR_ERR(gpu->clk_bus);
1818 
1819     gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1820     DBG("clk_core: %p", gpu->clk_core);
1821     if (IS_ERR(gpu->clk_core))
1822         return PTR_ERR(gpu->clk_core);
1823     gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1824 
1825     gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1826     DBG("clk_shader: %p", gpu->clk_shader);
1827     if (IS_ERR(gpu->clk_shader))
1828         return PTR_ERR(gpu->clk_shader);
1829     gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1830 
1831     /* TODO: figure out max mapped size */
1832     dev_set_drvdata(dev, gpu);
1833 
1834     /*
1835      * We treat the device as initially suspended.  The runtime PM
1836      * autosuspend delay is rather arbitary: no measurements have
1837      * yet been performed to determine an appropriate value.
1838      */
1839     pm_runtime_use_autosuspend(gpu->dev);
1840     pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1841     pm_runtime_enable(gpu->dev);
1842 
1843     err = component_add(&pdev->dev, &gpu_ops);
1844     if (err < 0) {
1845         dev_err(&pdev->dev, "failed to register component: %d\n", err);
1846         return err;
1847     }
1848 
1849     return 0;
1850 }
1851 
1852 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1853 {
1854     component_del(&pdev->dev, &gpu_ops);
1855     pm_runtime_disable(&pdev->dev);
1856     return 0;
1857 }
1858 
1859 #ifdef CONFIG_PM
1860 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1861 {
1862     struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1863     u32 idle, mask;
1864 
1865     /* If there are any jobs in the HW queue, we're not idle */
1866     if (atomic_read(&gpu->sched.hw_rq_count))
1867         return -EBUSY;
1868 
1869     /* Check whether the hardware (except FE and MC) is idle */
1870     mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1871                   VIVS_HI_IDLE_STATE_MC);
1872     idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1873     if (idle != mask) {
1874         dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1875                      idle);
1876         return -EBUSY;
1877     }
1878 
1879     return etnaviv_gpu_hw_suspend(gpu);
1880 }
1881 
1882 static int etnaviv_gpu_rpm_resume(struct device *dev)
1883 {
1884     struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1885     int ret;
1886 
1887     ret = etnaviv_gpu_clk_enable(gpu);
1888     if (ret)
1889         return ret;
1890 
1891     /* Re-initialise the basic hardware state */
1892     if (gpu->drm && gpu->initialized) {
1893         ret = etnaviv_gpu_hw_resume(gpu);
1894         if (ret) {
1895             etnaviv_gpu_clk_disable(gpu);
1896             return ret;
1897         }
1898     }
1899 
1900     return 0;
1901 }
1902 #endif
1903 
1904 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1905     SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1906                NULL)
1907 };
1908 
1909 struct platform_driver etnaviv_gpu_driver = {
1910     .driver = {
1911         .name = "etnaviv-gpu",
1912         .owner = THIS_MODULE,
1913         .pm = &etnaviv_gpu_pm_ops,
1914         .of_match_table = etnaviv_gpu_match,
1915     },
1916     .probe = etnaviv_gpu_platform_probe,
1917     .remove = etnaviv_gpu_platform_remove,
1918     .id_table = gpu_ids,
1919 };
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