drm/display/drm_dsc_helper.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright © 2018 Intel Corp
0004  *
0005  * Author:
0006  * Manasi Navare <manasi.d.navare@intel.com>
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/init.h>
0012 #include <linux/errno.h>
0013 #include <linux/byteorder/generic.h>
0014
0015 #include <drm/display/drm_dp_helper.h>
0016 #include <drm/display/drm_dsc_helper.h>
0017 #include <drm/drm_print.h>
0018
0019 /**
0020  * DOC: dsc helpers
0021  *
0022  * VESA specification for DP 1.4 adds a new feature called Display Stream
0023  * Compression (DSC) used to compress the pixel bits before sending it on
0024  * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
0025  * display interfaces can support high resolutions at higher frames rates uisng
0026  * the maximum available link capacity of these interfaces.
0027  *
0028  * These functions contain some common logic and helpers to deal with VESA
0029  * Display Stream Compression standard required for DSC on Display Port/eDP or
0030  * MIPI display interfaces.
0031  */
0032
0033 /**
0034  * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
0035  * for DisplayPort as per the DP 1.4 spec.
0036  * @pps_header: Secondary data packet header for DSC Picture
0037  *              Parameter Set as defined in &struct dp_sdp_header
0038  *
0039  * DP 1.4 spec defines the secondary data packet for sending the
0040  * picture parameter infoframes from the source to the sink.
0041  * This function populates the SDP header defined in
0042  * &struct dp_sdp_header.
0043  */
0044 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
0045 {
0046     memset(pps_header, 0, sizeof(*pps_header));
0047
0048     pps_header->HB1 = DP_SDP_PPS;
0049     pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
0050 }
0051 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
0052
0053 /**
0054  * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
0055  * @rc_buffer_block_size: block size code, according to DPCD offset 62h
0056  * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
0057  *
0058  * return:
0059  * buffer size in bytes, or 0 on invalid input
0060  */
0061 int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)
0062 {
0063     int size = 1024 * (rc_buffer_size + 1);
0064
0065     switch (rc_buffer_block_size) {
0066     case DP_DSC_RC_BUF_BLK_SIZE_1:
0067         return 1 * size;
0068     case DP_DSC_RC_BUF_BLK_SIZE_4:
0069         return 4 * size;
0070     case DP_DSC_RC_BUF_BLK_SIZE_16:
0071         return 16 * size;
0072     case DP_DSC_RC_BUF_BLK_SIZE_64:
0073         return 64 * size;
0074     default:
0075         return 0;
0076     }
0077 }
0078 EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size);
0079
0080 /**
0081  * drm_dsc_pps_payload_pack() - Populates the DSC PPS
0082  *
0083  * @pps_payload:
0084  * Bitwise struct for DSC Picture Parameter Set. This is defined
0085  * by &struct drm_dsc_picture_parameter_set
0086  * @dsc_cfg:
0087  * DSC Configuration data filled by driver as defined by
0088  * &struct drm_dsc_config
0089  *
0090  * DSC source device sends a picture parameter set (PPS) containing the
0091  * information required by the sink to decode the compressed frame. Driver
0092  * populates the DSC PPS struct using the DSC configuration parameters in
0093  * the order expected by the DSC Display Sink device. For the DSC, the sink
0094  * device expects the PPS payload in big endian format for fields
0095  * that span more than 1 byte.
0096  */
0097 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
0098                 const struct drm_dsc_config *dsc_cfg)
0099 {
0100     int i;
0101
0102     /* Protect against someone accidentally changing struct size */
0103     BUILD_BUG_ON(sizeof(*pps_payload) !=
0104              DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
0105
0106     memset(pps_payload, 0, sizeof(*pps_payload));
0107
0108     /* PPS 0 */
0109     pps_payload->dsc_version =
0110         dsc_cfg->dsc_version_minor |
0111         dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
0112
0113     /* PPS 1, 2 is 0 */
0114
0115     /* PPS 3 */
0116     pps_payload->pps_3 =
0117         dsc_cfg->line_buf_depth |
0118         dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
0119
0120     /* PPS 4 */
0121     pps_payload->pps_4 =
0122         ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
0123          DSC_PPS_MSB_SHIFT) |
0124         dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
0125         dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
0126         dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
0127         dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
0128
0129     /* PPS 5 */
0130     pps_payload->bits_per_pixel_low =
0131         (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
0132
0133     /*
0134      * The DSC panel expects the PPS packet to have big endian format
0135      * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
0136      * to big endian format. If format is little endian, it will swap
0137      * bytes to convert to Big endian else keep it unchanged.
0138      */
0139
0140     /* PPS 6, 7 */
0141     pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
0142
0143     /* PPS 8, 9 */
0144     pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
0145
0146     /* PPS 10, 11 */
0147     pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
0148
0149     /* PPS 12, 13 */
0150     pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
0151
0152     /* PPS 14, 15 */
0153     pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
0154
0155     /* PPS 16 */
0156     pps_payload->initial_xmit_delay_high =
0157         ((dsc_cfg->initial_xmit_delay &
0158           DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
0159          DSC_PPS_MSB_SHIFT);
0160
0161     /* PPS 17 */
0162     pps_payload->initial_xmit_delay_low =
0163         (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
0164
0165     /* PPS 18, 19 */
0166     pps_payload->initial_dec_delay =
0167         cpu_to_be16(dsc_cfg->initial_dec_delay);
0168
0169     /* PPS 20 is 0 */
0170
0171     /* PPS 21 */
0172     pps_payload->initial_scale_value =
0173         dsc_cfg->initial_scale_value;
0174
0175     /* PPS 22, 23 */
0176     pps_payload->scale_increment_interval =
0177         cpu_to_be16(dsc_cfg->scale_increment_interval);
0178
0179     /* PPS 24 */
0180     pps_payload->scale_decrement_interval_high =
0181         ((dsc_cfg->scale_decrement_interval &
0182           DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
0183          DSC_PPS_MSB_SHIFT);
0184
0185     /* PPS 25 */
0186     pps_payload->scale_decrement_interval_low =
0187         (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
0188
0189     /* PPS 26[7:0], PPS 27[7:5] RESERVED */
0190
0191     /* PPS 27 */
0192     pps_payload->first_line_bpg_offset =
0193         dsc_cfg->first_line_bpg_offset;
0194
0195     /* PPS 28, 29 */
0196     pps_payload->nfl_bpg_offset =
0197         cpu_to_be16(dsc_cfg->nfl_bpg_offset);
0198
0199     /* PPS 30, 31 */
0200     pps_payload->slice_bpg_offset =
0201         cpu_to_be16(dsc_cfg->slice_bpg_offset);
0202
0203     /* PPS 32, 33 */
0204     pps_payload->initial_offset =
0205         cpu_to_be16(dsc_cfg->initial_offset);
0206
0207     /* PPS 34, 35 */
0208     pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
0209
0210     /* PPS 36 */
0211     pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
0212
0213     /* PPS 37 */
0214     pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
0215
0216     /* PPS 38, 39 */
0217     pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
0218
0219     /* PPS 40 */
0220     pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
0221
0222     /* PPS 41 */
0223     pps_payload->rc_quant_incr_limit0 =
0224         dsc_cfg->rc_quant_incr_limit0;
0225
0226     /* PPS 42 */
0227     pps_payload->rc_quant_incr_limit1 =
0228         dsc_cfg->rc_quant_incr_limit1;
0229
0230     /* PPS 43 */
0231     pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
0232         DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
0233
0234     /* PPS 44 - 57 */
0235     for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
0236         pps_payload->rc_buf_thresh[i] =
0237             dsc_cfg->rc_buf_thresh[i];
0238
0239     /* PPS 58 - 87 */
0240     /*
0241      * For DSC sink programming the RC Range parameter fields
0242      * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
0243      */
0244     for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
0245         pps_payload->rc_range_parameters[i] =
0246             cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
0247                      DSC_PPS_RC_RANGE_MINQP_SHIFT) |
0248                     (dsc_cfg->rc_range_params[i].range_max_qp <<
0249                      DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
0250                     (dsc_cfg->rc_range_params[i].range_bpg_offset));
0251     }
0252
0253     /* PPS 88 */
0254     pps_payload->native_422_420 = dsc_cfg->native_422 |
0255         dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
0256
0257     /* PPS 89 */
0258     pps_payload->second_line_bpg_offset =
0259         dsc_cfg->second_line_bpg_offset;
0260
0261     /* PPS 90, 91 */
0262     pps_payload->nsl_bpg_offset =
0263         cpu_to_be16(dsc_cfg->nsl_bpg_offset);
0264
0265     /* PPS 92, 93 */
0266     pps_payload->second_line_offset_adj =
0267         cpu_to_be16(dsc_cfg->second_line_offset_adj);
0268
0269     /* PPS 94 - 127 are O */
0270 }
0271 EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
0272
0273 /**
0274  * drm_dsc_compute_rc_parameters() - Write rate control
0275  * parameters to the dsc configuration defined in
0276  * &struct drm_dsc_config in accordance with the DSC 1.2
0277  * specification. Some configuration fields must be present
0278  * beforehand.
0279  *
0280  * @vdsc_cfg:
0281  * DSC Configuration data partially filled by driver
0282  */
0283 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
0284 {
0285     unsigned long groups_per_line = 0;
0286     unsigned long groups_total = 0;
0287     unsigned long num_extra_mux_bits = 0;
0288     unsigned long slice_bits = 0;
0289     unsigned long hrd_delay = 0;
0290     unsigned long final_scale = 0;
0291     unsigned long rbs_min = 0;
0292
0293     if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
0294         /* Number of groups used to code each line of a slice */
0295         groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
0296                            DSC_RC_PIXELS_PER_GROUP);
0297
0298         /* chunksize in Bytes */
0299         vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
0300                               vdsc_cfg->bits_per_pixel,
0301                               (8 * 16));
0302     } else {
0303         /* Number of groups used to code each line of a slice */
0304         groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
0305                            DSC_RC_PIXELS_PER_GROUP);
0306
0307         /* chunksize in Bytes */
0308         vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
0309                               vdsc_cfg->bits_per_pixel,
0310                               (8 * 16));
0311     }
0312
0313     if (vdsc_cfg->convert_rgb)
0314         num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
0315                       (4 * vdsc_cfg->bits_per_component + 4)
0316                       - 2);
0317     else if (vdsc_cfg->native_422)
0318         num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
0319             (4 * vdsc_cfg->bits_per_component + 4) +
0320             3 * (4 * vdsc_cfg->bits_per_component) - 2;
0321     else
0322         num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
0323             (4 * vdsc_cfg->bits_per_component + 4) +
0324             2 * (4 * vdsc_cfg->bits_per_component) - 2;
0325     /* Number of bits in one Slice */
0326     slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
0327
0328     while ((num_extra_mux_bits > 0) &&
0329            ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
0330         num_extra_mux_bits--;
0331
0332     if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
0333         vdsc_cfg->initial_scale_value = groups_per_line + 8;
0334
0335     /* scale_decrement_interval calculation according to DSC spec 1.11 */
0336     if (vdsc_cfg->initial_scale_value > 8)
0337         vdsc_cfg->scale_decrement_interval = groups_per_line /
0338             (vdsc_cfg->initial_scale_value - 8);
0339     else
0340         vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
0341
0342     vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
0343         (vdsc_cfg->initial_xmit_delay *
0344          vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
0345
0346     if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
0347         DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
0348         return -ERANGE;
0349     }
0350
0351     final_scale = (vdsc_cfg->rc_model_size * 8) /
0352         (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
0353     if (vdsc_cfg->slice_height > 1)
0354         /*
0355          * NflBpgOffset is 16 bit value with 11 fractional bits
0356          * hence we multiply by 2^11 for preserving the
0357          * fractional part
0358          */
0359         vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
0360                             (vdsc_cfg->slice_height - 1));
0361     else
0362         vdsc_cfg->nfl_bpg_offset = 0;
0363
0364     /* Number of groups used to code the entire slice */
0365     groups_total = groups_per_line * vdsc_cfg->slice_height;
0366
0367     /* slice_bpg_offset is 16 bit value with 11 fractional bits */
0368     vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
0369                             vdsc_cfg->initial_offset +
0370                             num_extra_mux_bits) << 11),
0371                           groups_total);
0372
0373     if (final_scale > 9) {
0374         /*
0375          * ScaleIncrementInterval =
0376          * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
0377          * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
0378          * we need divide by 2^11 from pstDscCfg values
0379          */
0380         vdsc_cfg->scale_increment_interval =
0381                 (vdsc_cfg->final_offset * (1 << 11)) /
0382                 ((vdsc_cfg->nfl_bpg_offset +
0383                 vdsc_cfg->slice_bpg_offset) *
0384                 (final_scale - 9));
0385     } else {
0386         /*
0387          * If finalScaleValue is less than or equal to 9, a value of 0 should
0388          * be used to disable the scale increment at the end of the slice
0389          */
0390         vdsc_cfg->scale_increment_interval = 0;
0391     }
0392
0393     /*
0394      * DSC spec mentions that bits_per_pixel specifies the target
0395      * bits/pixel (bpp) rate that is used by the encoder,
0396      * in steps of 1/16 of a bit per pixel
0397      */
0398     rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
0399         DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
0400                  vdsc_cfg->bits_per_pixel, 16) +
0401         groups_per_line * vdsc_cfg->first_line_bpg_offset;
0402
0403     hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
0404     vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
0405     vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
0406
0407     return 0;
0408 }
0409 EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);