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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * TI SN65DSI83,84,85 driver
0004  *
0005  * Currently supported:
0006  * - SN65DSI83
0007  *   = 1x Single-link DSI ~ 1x Single-link LVDS
0008  *   - Supported
0009  *   - Single-link LVDS mode tested
0010  * - SN65DSI84
0011  *   = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
0012  *   - Supported
0013  *   - Dual-link LVDS mode tested
0014  *   - 2x Single-link LVDS mode unsupported
0015  *     (should be easy to add by someone who has the HW)
0016  * - SN65DSI85
0017  *   = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
0018  *   - Unsupported
0019  *     (should be easy to add by someone who has the HW)
0020  *
0021  * Copyright (C) 2021 Marek Vasut <marex@denx.de>
0022  *
0023  * Based on previous work of:
0024  * Valentin Raevsky <valentin@compulab.co.il>
0025  * Philippe Schenker <philippe.schenker@toradex.com>
0026  */
0027 
0028 #include <linux/bits.h>
0029 #include <linux/clk.h>
0030 #include <linux/gpio/consumer.h>
0031 #include <linux/i2c.h>
0032 #include <linux/media-bus-format.h>
0033 #include <linux/module.h>
0034 #include <linux/of_device.h>
0035 #include <linux/of_graph.h>
0036 #include <linux/regmap.h>
0037 #include <linux/regulator/consumer.h>
0038 
0039 #include <drm/drm_atomic_helper.h>
0040 #include <drm/drm_bridge.h>
0041 #include <drm/drm_mipi_dsi.h>
0042 #include <drm/drm_of.h>
0043 #include <drm/drm_panel.h>
0044 #include <drm/drm_print.h>
0045 #include <drm/drm_probe_helper.h>
0046 
0047 /* ID registers */
0048 #define REG_ID(n)               (0x00 + (n))
0049 /* Reset and clock registers */
0050 #define REG_RC_RESET                0x09
0051 #define  REG_RC_RESET_SOFT_RESET        BIT(0)
0052 #define REG_RC_LVDS_PLL             0x0a
0053 #define  REG_RC_LVDS_PLL_PLL_EN_STAT        BIT(7)
0054 #define  REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n)  (((n) & 0x7) << 1)
0055 #define  REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY    BIT(0)
0056 #define REG_RC_DSI_CLK              0x0b
0057 #define  REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n)  (((n) & 0x1f) << 3)
0058 #define  REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n)    ((n) & 0x3)
0059 #define REG_RC_PLL_EN               0x0d
0060 #define  REG_RC_PLL_EN_PLL_EN           BIT(0)
0061 /* DSI registers */
0062 #define REG_DSI_LANE                0x10
0063 #define  REG_DSI_LANE_LEFT_RIGHT_PIXELS     BIT(7)  /* DSI85-only */
0064 #define  REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0   /* DSI85-only */
0065 #define  REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE  BIT(6)  /* DSI85-only */
0066 #define  REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE   BIT(5)
0067 #define  REG_DSI_LANE_CHA_DSI_LANES(n)      (((n) & 0x3) << 3)
0068 #define  REG_DSI_LANE_CHB_DSI_LANES(n)      (((n) & 0x3) << 1)
0069 #define  REG_DSI_LANE_SOT_ERR_TOL_DIS       BIT(0)
0070 #define REG_DSI_EQ              0x11
0071 #define  REG_DSI_EQ_CHA_DSI_DATA_EQ(n)      (((n) & 0x3) << 6)
0072 #define  REG_DSI_EQ_CHA_DSI_CLK_EQ(n)       (((n) & 0x3) << 2)
0073 #define REG_DSI_CLK             0x12
0074 #define  REG_DSI_CLK_CHA_DSI_CLK_RANGE(n)   ((n) & 0xff)
0075 /* LVDS registers */
0076 #define REG_LVDS_FMT                0x18
0077 #define  REG_LVDS_FMT_DE_NEG_POLARITY       BIT(7)
0078 #define  REG_LVDS_FMT_HS_NEG_POLARITY       BIT(6)
0079 #define  REG_LVDS_FMT_VS_NEG_POLARITY       BIT(5)
0080 #define  REG_LVDS_FMT_LVDS_LINK_CFG     BIT(4)  /* 0:AB 1:A-only */
0081 #define  REG_LVDS_FMT_CHA_24BPP_MODE        BIT(3)
0082 #define  REG_LVDS_FMT_CHB_24BPP_MODE        BIT(2)
0083 #define  REG_LVDS_FMT_CHA_24BPP_FORMAT1     BIT(1)
0084 #define  REG_LVDS_FMT_CHB_24BPP_FORMAT1     BIT(0)
0085 #define REG_LVDS_VCOM               0x19
0086 #define  REG_LVDS_VCOM_CHA_LVDS_VOCM        BIT(6)
0087 #define  REG_LVDS_VCOM_CHB_LVDS_VOCM        BIT(4)
0088 #define  REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n)    (((n) & 0x3) << 2)
0089 #define  REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n)    ((n) & 0x3)
0090 #define REG_LVDS_LANE               0x1a
0091 #define  REG_LVDS_LANE_EVEN_ODD_SWAP        BIT(6)
0092 #define  REG_LVDS_LANE_CHA_REVERSE_LVDS     BIT(5)
0093 #define  REG_LVDS_LANE_CHB_REVERSE_LVDS     BIT(4)
0094 #define  REG_LVDS_LANE_CHA_LVDS_TERM        BIT(1)
0095 #define  REG_LVDS_LANE_CHB_LVDS_TERM        BIT(0)
0096 #define REG_LVDS_CM             0x1b
0097 #define  REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n)  (((n) & 0x3) << 4)
0098 #define  REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n)  ((n) & 0x3)
0099 /* Video registers */
0100 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW  0x20
0101 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21
0102 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW   0x24
0103 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH  0x25
0104 #define REG_VID_CHA_SYNC_DELAY_LOW      0x28
0105 #define REG_VID_CHA_SYNC_DELAY_HIGH     0x29
0106 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW   0x2c
0107 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH  0x2d
0108 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW   0x30
0109 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH  0x31
0110 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH   0x34
0111 #define REG_VID_CHA_VERTICAL_BACK_PORCH     0x36
0112 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH  0x38
0113 #define REG_VID_CHA_VERTICAL_FRONT_PORCH    0x3a
0114 #define REG_VID_CHA_TEST_PATTERN        0x3c
0115 /* IRQ registers */
0116 #define REG_IRQ_GLOBAL              0xe0
0117 #define  REG_IRQ_GLOBAL_IRQ_EN          BIT(0)
0118 #define REG_IRQ_EN              0xe1
0119 #define  REG_IRQ_EN_CHA_SYNCH_ERR_EN        BIT(7)
0120 #define  REG_IRQ_EN_CHA_CRC_ERR_EN      BIT(6)
0121 #define  REG_IRQ_EN_CHA_UNC_ECC_ERR_EN      BIT(5)
0122 #define  REG_IRQ_EN_CHA_COR_ECC_ERR_EN      BIT(4)
0123 #define  REG_IRQ_EN_CHA_LLP_ERR_EN      BIT(3)
0124 #define  REG_IRQ_EN_CHA_SOT_BIT_ERR_EN      BIT(2)
0125 #define  REG_IRQ_EN_CHA_PLL_UNLOCK_EN       BIT(0)
0126 #define REG_IRQ_STAT                0xe5
0127 #define  REG_IRQ_STAT_CHA_SYNCH_ERR     BIT(7)
0128 #define  REG_IRQ_STAT_CHA_CRC_ERR       BIT(6)
0129 #define  REG_IRQ_STAT_CHA_UNC_ECC_ERR       BIT(5)
0130 #define  REG_IRQ_STAT_CHA_COR_ECC_ERR       BIT(4)
0131 #define  REG_IRQ_STAT_CHA_LLP_ERR       BIT(3)
0132 #define  REG_IRQ_STAT_CHA_SOT_BIT_ERR       BIT(2)
0133 #define  REG_IRQ_STAT_CHA_PLL_UNLOCK        BIT(0)
0134 
0135 enum sn65dsi83_model {
0136     MODEL_SN65DSI83,
0137     MODEL_SN65DSI84,
0138 };
0139 
0140 struct sn65dsi83 {
0141     struct drm_bridge       bridge;
0142     struct device           *dev;
0143     struct regmap           *regmap;
0144     struct mipi_dsi_device      *dsi;
0145     struct drm_bridge       *panel_bridge;
0146     struct gpio_desc        *enable_gpio;
0147     struct regulator        *vcc;
0148     bool                lvds_dual_link;
0149     bool                lvds_dual_link_even_odd_swap;
0150 };
0151 
0152 static const struct regmap_range sn65dsi83_readable_ranges[] = {
0153     regmap_reg_range(REG_ID(0), REG_ID(8)),
0154     regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
0155     regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
0156     regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
0157     regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
0158     regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
0159              REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
0160     regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
0161              REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
0162     regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
0163              REG_VID_CHA_SYNC_DELAY_HIGH),
0164     regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
0165              REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
0166     regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
0167              REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
0168     regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
0169              REG_VID_CHA_HORIZONTAL_BACK_PORCH),
0170     regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
0171              REG_VID_CHA_VERTICAL_BACK_PORCH),
0172     regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
0173              REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
0174     regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
0175              REG_VID_CHA_VERTICAL_FRONT_PORCH),
0176     regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
0177     regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
0178     regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
0179 };
0180 
0181 static const struct regmap_access_table sn65dsi83_readable_table = {
0182     .yes_ranges = sn65dsi83_readable_ranges,
0183     .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
0184 };
0185 
0186 static const struct regmap_range sn65dsi83_writeable_ranges[] = {
0187     regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
0188     regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
0189     regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
0190     regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
0191     regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
0192              REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
0193     regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
0194              REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
0195     regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
0196              REG_VID_CHA_SYNC_DELAY_HIGH),
0197     regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
0198              REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
0199     regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
0200              REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
0201     regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
0202              REG_VID_CHA_HORIZONTAL_BACK_PORCH),
0203     regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
0204              REG_VID_CHA_VERTICAL_BACK_PORCH),
0205     regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
0206              REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
0207     regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
0208              REG_VID_CHA_VERTICAL_FRONT_PORCH),
0209     regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
0210     regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
0211     regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
0212 };
0213 
0214 static const struct regmap_access_table sn65dsi83_writeable_table = {
0215     .yes_ranges = sn65dsi83_writeable_ranges,
0216     .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
0217 };
0218 
0219 static const struct regmap_range sn65dsi83_volatile_ranges[] = {
0220     regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
0221     regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
0222     regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
0223 };
0224 
0225 static const struct regmap_access_table sn65dsi83_volatile_table = {
0226     .yes_ranges = sn65dsi83_volatile_ranges,
0227     .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
0228 };
0229 
0230 static const struct regmap_config sn65dsi83_regmap_config = {
0231     .reg_bits = 8,
0232     .val_bits = 8,
0233     .rd_table = &sn65dsi83_readable_table,
0234     .wr_table = &sn65dsi83_writeable_table,
0235     .volatile_table = &sn65dsi83_volatile_table,
0236     .cache_type = REGCACHE_RBTREE,
0237     .max_register = REG_IRQ_STAT,
0238 };
0239 
0240 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
0241 {
0242     return container_of(bridge, struct sn65dsi83, bridge);
0243 }
0244 
0245 static int sn65dsi83_attach(struct drm_bridge *bridge,
0246                 enum drm_bridge_attach_flags flags)
0247 {
0248     struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
0249 
0250     return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
0251                  &ctx->bridge, flags);
0252 }
0253 
0254 static void sn65dsi83_detach(struct drm_bridge *bridge)
0255 {
0256     struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
0257 
0258     if (!ctx->dsi)
0259         return;
0260 
0261     ctx->dsi = NULL;
0262 }
0263 
0264 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
0265                    const struct drm_display_mode *mode)
0266 {
0267     /*
0268      * The encoding of the LVDS_CLK_RANGE is as follows:
0269      * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
0270      * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
0271      * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
0272      * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
0273      * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
0274      * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
0275      * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
0276      * the ends of the ranges are clamped to the supported range. Since
0277      * sn65dsi83_mode_valid() already filters the valid modes and limits
0278      * the clock to 25..154 MHz, the range calculation can be simplified
0279      * as follows:
0280      */
0281     int mode_clock = mode->clock;
0282 
0283     if (ctx->lvds_dual_link)
0284         mode_clock /= 2;
0285 
0286     return (mode_clock - 12500) / 25000;
0287 }
0288 
0289 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
0290                   const struct drm_display_mode *mode)
0291 {
0292     /*
0293      * The encoding of the CHA_DSI_CLK_RANGE is as follows:
0294      * 0x00 through 0x07 - Reserved
0295      * 0x08 - 40 <= DSI_CLK < 45 MHz
0296      * 0x09 - 45 <= DSI_CLK < 50 MHz
0297      * ...
0298      * 0x63 - 495 <= DSI_CLK < 500 MHz
0299      * 0x64 - 500 MHz
0300      * 0x65 through 0xFF - Reserved
0301      * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
0302      * The DSI clock are calculated as:
0303      *  DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
0304      * the 2 is there because the bus is DDR.
0305      */
0306     return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
0307                 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
0308                 ctx->dsi->lanes / 2, 40000U, 500000U), 5000U);
0309 }
0310 
0311 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
0312 {
0313     /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
0314     unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
0315 
0316     dsi_div /= ctx->dsi->lanes;
0317 
0318     if (!ctx->lvds_dual_link)
0319         dsi_div /= 2;
0320 
0321     return dsi_div - 1;
0322 }
0323 
0324 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
0325                     struct drm_bridge_state *old_bridge_state)
0326 {
0327     struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
0328     struct drm_atomic_state *state = old_bridge_state->base.state;
0329     const struct drm_bridge_state *bridge_state;
0330     const struct drm_crtc_state *crtc_state;
0331     const struct drm_display_mode *mode;
0332     struct drm_connector *connector;
0333     struct drm_crtc *crtc;
0334     bool lvds_format_24bpp;
0335     bool lvds_format_jeida;
0336     unsigned int pval;
0337     __le16 le16val;
0338     u16 val;
0339     int ret;
0340 
0341     ret = regulator_enable(ctx->vcc);
0342     if (ret) {
0343         dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret);
0344         return;
0345     }
0346 
0347     /* Deassert reset */
0348     gpiod_set_value_cansleep(ctx->enable_gpio, 1);
0349     usleep_range(1000, 1100);
0350 
0351     /* Get the LVDS format from the bridge state. */
0352     bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
0353 
0354     switch (bridge_state->output_bus_cfg.format) {
0355     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0356         lvds_format_24bpp = false;
0357         lvds_format_jeida = true;
0358         break;
0359     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0360         lvds_format_24bpp = true;
0361         lvds_format_jeida = true;
0362         break;
0363     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0364         lvds_format_24bpp = true;
0365         lvds_format_jeida = false;
0366         break;
0367     default:
0368         /*
0369          * Some bridges still don't set the correct
0370          * LVDS bus pixel format, use SPWG24 default
0371          * format until those are fixed.
0372          */
0373         lvds_format_24bpp = true;
0374         lvds_format_jeida = false;
0375         dev_warn(ctx->dev,
0376              "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
0377              bridge_state->output_bus_cfg.format);
0378         break;
0379     }
0380 
0381     /*
0382      * Retrieve the CRTC adjusted mode. This requires a little dance to go
0383      * from the bridge to the encoder, to the connector and to the CRTC.
0384      */
0385     connector = drm_atomic_get_new_connector_for_encoder(state,
0386                                  bridge->encoder);
0387     crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
0388     crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
0389     mode = &crtc_state->adjusted_mode;
0390 
0391     /* Clear reset, disable PLL */
0392     regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
0393     regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
0394 
0395     /* Reference clock derived from DSI link clock. */
0396     regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
0397              REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
0398              REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
0399     regmap_write(ctx->regmap, REG_DSI_CLK,
0400              REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
0401     regmap_write(ctx->regmap, REG_RC_DSI_CLK,
0402              REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
0403 
0404     /* Set number of DSI lanes and LVDS link config. */
0405     regmap_write(ctx->regmap, REG_DSI_LANE,
0406              REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
0407              REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) |
0408              /* CHB is DSI85-only, set to default on DSI83/DSI84 */
0409              REG_DSI_LANE_CHB_DSI_LANES(3));
0410     /* No equalization. */
0411     regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
0412 
0413     /* Set up sync signal polarity. */
0414     val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
0415            REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
0416           (mode->flags & DRM_MODE_FLAG_NVSYNC ?
0417            REG_LVDS_FMT_VS_NEG_POLARITY : 0);
0418 
0419     /* Set up bits-per-pixel, 18bpp or 24bpp. */
0420     if (lvds_format_24bpp) {
0421         val |= REG_LVDS_FMT_CHA_24BPP_MODE;
0422         if (ctx->lvds_dual_link)
0423             val |= REG_LVDS_FMT_CHB_24BPP_MODE;
0424     }
0425 
0426     /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
0427     if (lvds_format_jeida) {
0428         val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
0429         if (ctx->lvds_dual_link)
0430             val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
0431     }
0432 
0433     /* Set up LVDS output config (DSI84,DSI85) */
0434     if (!ctx->lvds_dual_link)
0435         val |= REG_LVDS_FMT_LVDS_LINK_CFG;
0436 
0437     regmap_write(ctx->regmap, REG_LVDS_FMT, val);
0438     regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05);
0439     regmap_write(ctx->regmap, REG_LVDS_LANE,
0440              (ctx->lvds_dual_link_even_odd_swap ?
0441               REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
0442              REG_LVDS_LANE_CHA_LVDS_TERM |
0443              REG_LVDS_LANE_CHB_LVDS_TERM);
0444     regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
0445 
0446     le16val = cpu_to_le16(mode->hdisplay);
0447     regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
0448               &le16val, 2);
0449     le16val = cpu_to_le16(mode->vdisplay);
0450     regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
0451               &le16val, 2);
0452     /* 32 + 1 pixel clock to ensure proper operation */
0453     le16val = cpu_to_le16(32 + 1);
0454     regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
0455     le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
0456     regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
0457               &le16val, 2);
0458     le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
0459     regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
0460               &le16val, 2);
0461     regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
0462              mode->htotal - mode->hsync_end);
0463     regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
0464              mode->vtotal - mode->vsync_end);
0465     regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
0466              mode->hsync_start - mode->hdisplay);
0467     regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
0468              mode->vsync_start - mode->vdisplay);
0469     regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
0470 
0471     /* Enable PLL */
0472     regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
0473     usleep_range(3000, 4000);
0474     ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
0475                        pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
0476                        1000, 100000);
0477     if (ret) {
0478         dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
0479         /* On failure, disable PLL again and exit. */
0480         regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
0481         return;
0482     }
0483 
0484     /* Trigger reset after CSR register update. */
0485     regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
0486 
0487     /* Clear all errors that got asserted during initialization. */
0488     regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
0489     regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
0490 
0491     usleep_range(10000, 12000);
0492     regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
0493     if (pval)
0494         dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval);
0495 }
0496 
0497 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
0498                      struct drm_bridge_state *old_bridge_state)
0499 {
0500     struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
0501     int ret;
0502 
0503     /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
0504     gpiod_set_value_cansleep(ctx->enable_gpio, 0);
0505     usleep_range(10000, 11000);
0506 
0507     ret = regulator_disable(ctx->vcc);
0508     if (ret)
0509         dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
0510 
0511     regcache_mark_dirty(ctx->regmap);
0512 }
0513 
0514 static enum drm_mode_status
0515 sn65dsi83_mode_valid(struct drm_bridge *bridge,
0516              const struct drm_display_info *info,
0517              const struct drm_display_mode *mode)
0518 {
0519     /* LVDS output clock range 25..154 MHz */
0520     if (mode->clock < 25000)
0521         return MODE_CLOCK_LOW;
0522     if (mode->clock > 154000)
0523         return MODE_CLOCK_HIGH;
0524 
0525     return MODE_OK;
0526 }
0527 
0528 #define MAX_INPUT_SEL_FORMATS   1
0529 
0530 static u32 *
0531 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
0532                     struct drm_bridge_state *bridge_state,
0533                     struct drm_crtc_state *crtc_state,
0534                     struct drm_connector_state *conn_state,
0535                     u32 output_fmt,
0536                     unsigned int *num_input_fmts)
0537 {
0538     u32 *input_fmts;
0539 
0540     *num_input_fmts = 0;
0541 
0542     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
0543                  GFP_KERNEL);
0544     if (!input_fmts)
0545         return NULL;
0546 
0547     /* This is the DSI-end bus format */
0548     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
0549     *num_input_fmts = 1;
0550 
0551     return input_fmts;
0552 }
0553 
0554 static const struct drm_bridge_funcs sn65dsi83_funcs = {
0555     .attach         = sn65dsi83_attach,
0556     .detach         = sn65dsi83_detach,
0557     .atomic_enable      = sn65dsi83_atomic_enable,
0558     .atomic_disable     = sn65dsi83_atomic_disable,
0559     .mode_valid     = sn65dsi83_mode_valid,
0560 
0561     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0562     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
0563     .atomic_reset = drm_atomic_helper_bridge_reset,
0564     .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
0565 };
0566 
0567 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
0568 {
0569     struct drm_bridge *panel_bridge;
0570     struct device *dev = ctx->dev;
0571 
0572     ctx->lvds_dual_link = false;
0573     ctx->lvds_dual_link_even_odd_swap = false;
0574     if (model != MODEL_SN65DSI83) {
0575         struct device_node *port2, *port3;
0576         int dual_link;
0577 
0578         port2 = of_graph_get_port_by_id(dev->of_node, 2);
0579         port3 = of_graph_get_port_by_id(dev->of_node, 3);
0580         dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
0581         of_node_put(port2);
0582         of_node_put(port3);
0583 
0584         if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
0585             ctx->lvds_dual_link = true;
0586             /* Odd pixels to LVDS Channel A, even pixels to B */
0587             ctx->lvds_dual_link_even_odd_swap = false;
0588         } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
0589             ctx->lvds_dual_link = true;
0590             /* Even pixels to LVDS Channel A, odd pixels to B */
0591             ctx->lvds_dual_link_even_odd_swap = true;
0592         }
0593     }
0594 
0595     panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
0596     if (IS_ERR(panel_bridge))
0597         return PTR_ERR(panel_bridge);
0598 
0599     ctx->panel_bridge = panel_bridge;
0600 
0601     ctx->vcc = devm_regulator_get(dev, "vcc");
0602     if (IS_ERR(ctx->vcc))
0603         return dev_err_probe(dev, PTR_ERR(ctx->vcc),
0604                      "Failed to get supply 'vcc'\n");
0605 
0606     return 0;
0607 }
0608 
0609 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
0610 {
0611     struct device *dev = ctx->dev;
0612     struct device_node *host_node;
0613     struct device_node *endpoint;
0614     struct mipi_dsi_device *dsi;
0615     struct mipi_dsi_host *host;
0616     const struct mipi_dsi_device_info info = {
0617         .type = "sn65dsi83",
0618         .channel = 0,
0619         .node = NULL,
0620     };
0621     int dsi_lanes, ret;
0622 
0623     endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
0624     dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
0625     host_node = of_graph_get_remote_port_parent(endpoint);
0626     host = of_find_mipi_dsi_host_by_node(host_node);
0627     of_node_put(host_node);
0628     of_node_put(endpoint);
0629 
0630     if (!host)
0631         return -EPROBE_DEFER;
0632 
0633     if (dsi_lanes < 0)
0634         return dsi_lanes;
0635 
0636     dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
0637     if (IS_ERR(dsi))
0638         return dev_err_probe(dev, PTR_ERR(dsi),
0639                      "failed to create dsi device\n");
0640 
0641     ctx->dsi = dsi;
0642 
0643     dsi->lanes = dsi_lanes;
0644     dsi->format = MIPI_DSI_FMT_RGB888;
0645     dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
0646 
0647     ret = devm_mipi_dsi_attach(dev, dsi);
0648     if (ret < 0) {
0649         dev_err(dev, "failed to attach dsi to host: %d\n", ret);
0650         return ret;
0651     }
0652 
0653     return 0;
0654 }
0655 
0656 static int sn65dsi83_probe(struct i2c_client *client,
0657                const struct i2c_device_id *id)
0658 {
0659     struct device *dev = &client->dev;
0660     enum sn65dsi83_model model;
0661     struct sn65dsi83 *ctx;
0662     int ret;
0663 
0664     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
0665     if (!ctx)
0666         return -ENOMEM;
0667 
0668     ctx->dev = dev;
0669 
0670     if (dev->of_node) {
0671         model = (enum sn65dsi83_model)(uintptr_t)
0672             of_device_get_match_data(dev);
0673     } else {
0674         model = id->driver_data;
0675     }
0676 
0677     /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
0678     ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable",
0679                            GPIOD_OUT_LOW);
0680     if (IS_ERR(ctx->enable_gpio))
0681         return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n");
0682 
0683     usleep_range(10000, 11000);
0684 
0685     ret = sn65dsi83_parse_dt(ctx, model);
0686     if (ret)
0687         return ret;
0688 
0689     ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
0690     if (IS_ERR(ctx->regmap))
0691         return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n");
0692 
0693     dev_set_drvdata(dev, ctx);
0694     i2c_set_clientdata(client, ctx);
0695 
0696     ctx->bridge.funcs = &sn65dsi83_funcs;
0697     ctx->bridge.of_node = dev->of_node;
0698     drm_bridge_add(&ctx->bridge);
0699 
0700     ret = sn65dsi83_host_attach(ctx);
0701     if (ret)
0702         goto err_remove_bridge;
0703 
0704     return 0;
0705 
0706 err_remove_bridge:
0707     drm_bridge_remove(&ctx->bridge);
0708     return ret;
0709 }
0710 
0711 static int sn65dsi83_remove(struct i2c_client *client)
0712 {
0713     struct sn65dsi83 *ctx = i2c_get_clientdata(client);
0714 
0715     drm_bridge_remove(&ctx->bridge);
0716 
0717     return 0;
0718 }
0719 
0720 static struct i2c_device_id sn65dsi83_id[] = {
0721     { "ti,sn65dsi83", MODEL_SN65DSI83 },
0722     { "ti,sn65dsi84", MODEL_SN65DSI84 },
0723     {},
0724 };
0725 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
0726 
0727 static const struct of_device_id sn65dsi83_match_table[] = {
0728     { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
0729     { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
0730     {},
0731 };
0732 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
0733 
0734 static struct i2c_driver sn65dsi83_driver = {
0735     .probe = sn65dsi83_probe,
0736     .remove = sn65dsi83_remove,
0737     .id_table = sn65dsi83_id,
0738     .driver = {
0739         .name = "sn65dsi83",
0740         .of_match_table = sn65dsi83_match_table,
0741     },
0742 };
0743 module_i2c_driver(sn65dsi83_driver);
0744 
0745 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
0746 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
0747 MODULE_LICENSE("GPL v2");
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