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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * TC358775 DSI to LVDS bridge driver
0004  *
0005  * Copyright (C) 2020 SMART Wireless Computing
0006  * Author: Vinay Simha BN <simhavcs@gmail.com>
0007  *
0008  */
0009 /* #define DEBUG */
0010 #include <linux/bitfield.h>
0011 #include <linux/clk.h>
0012 #include <linux/device.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/i2c.h>
0015 #include <linux/kernel.h>
0016 #include <linux/media-bus-format.h>
0017 #include <linux/module.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/slab.h>
0020 
0021 #include <asm/unaligned.h>
0022 
0023 #include <drm/display/drm_dp_helper.h>
0024 #include <drm/drm_atomic_helper.h>
0025 #include <drm/drm_bridge.h>
0026 #include <drm/drm_crtc_helper.h>
0027 #include <drm/drm_mipi_dsi.h>
0028 #include <drm/drm_of.h>
0029 #include <drm/drm_panel.h>
0030 #include <drm/drm_probe_helper.h>
0031 
0032 #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
0033 
0034 /* Registers */
0035 
0036 /* DSI D-PHY Layer Registers */
0037 #define D0W_DPHYCONTTX  0x0004  /* Data Lane 0 DPHY Tx Control */
0038 #define CLW_DPHYCONTRX  0x0020  /* Clock Lane DPHY Rx Control */
0039 #define D0W_DPHYCONTRX  0x0024  /* Data Lane 0 DPHY Rx Control */
0040 #define D1W_DPHYCONTRX  0x0028  /* Data Lane 1 DPHY Rx Control */
0041 #define D2W_DPHYCONTRX  0x002C  /* Data Lane 2 DPHY Rx Control */
0042 #define D3W_DPHYCONTRX  0x0030  /* Data Lane 3 DPHY Rx Control */
0043 #define COM_DPHYCONTRX  0x0038  /* DPHY Rx Common Control */
0044 #define CLW_CNTRL       0x0040  /* Clock Lane Control */
0045 #define D0W_CNTRL       0x0044  /* Data Lane 0 Control */
0046 #define D1W_CNTRL       0x0048  /* Data Lane 1 Control */
0047 #define D2W_CNTRL       0x004C  /* Data Lane 2 Control */
0048 #define D3W_CNTRL       0x0050  /* Data Lane 3 Control */
0049 #define DFTMODE_CNTRL   0x0054  /* DFT Mode Control */
0050 
0051 /* DSI PPI Layer Registers */
0052 #define PPI_STARTPPI    0x0104  /* START control bit of PPI-TX function. */
0053 #define PPI_START_FUNCTION      1
0054 
0055 #define PPI_BUSYPPI     0x0108
0056 #define PPI_LINEINITCNT 0x0110  /* Line Initialization Wait Counter  */
0057 #define PPI_LPTXTIMECNT 0x0114
0058 #define PPI_LANEENABLE  0x0134  /* Enables each lane at the PPI layer. */
0059 #define PPI_TX_RX_TA    0x013C  /* DSI Bus Turn Around timing parameters */
0060 
0061 /* Analog timer function enable */
0062 #define PPI_CLS_ATMR    0x0140  /* Delay for Clock Lane in LPRX  */
0063 #define PPI_D0S_ATMR    0x0144  /* Delay for Data Lane 0 in LPRX */
0064 #define PPI_D1S_ATMR    0x0148  /* Delay for Data Lane 1 in LPRX */
0065 #define PPI_D2S_ATMR    0x014C  /* Delay for Data Lane 2 in LPRX */
0066 #define PPI_D3S_ATMR    0x0150  /* Delay for Data Lane 3 in LPRX */
0067 
0068 #define PPI_D0S_CLRSIPOCOUNT    0x0164  /* For lane 0 */
0069 #define PPI_D1S_CLRSIPOCOUNT    0x0168  /* For lane 1 */
0070 #define PPI_D2S_CLRSIPOCOUNT    0x016C  /* For lane 2 */
0071 #define PPI_D3S_CLRSIPOCOUNT    0x0170  /* For lane 3 */
0072 
0073 #define CLS_PRE         0x0180  /* Digital Counter inside of PHY IO */
0074 #define D0S_PRE         0x0184  /* Digital Counter inside of PHY IO */
0075 #define D1S_PRE         0x0188  /* Digital Counter inside of PHY IO */
0076 #define D2S_PRE         0x018C  /* Digital Counter inside of PHY IO */
0077 #define D3S_PRE         0x0190  /* Digital Counter inside of PHY IO */
0078 #define CLS_PREP        0x01A0  /* Digital Counter inside of PHY IO */
0079 #define D0S_PREP        0x01A4  /* Digital Counter inside of PHY IO */
0080 #define D1S_PREP        0x01A8  /* Digital Counter inside of PHY IO */
0081 #define D2S_PREP        0x01AC  /* Digital Counter inside of PHY IO */
0082 #define D3S_PREP        0x01B0  /* Digital Counter inside of PHY IO */
0083 #define CLS_ZERO        0x01C0  /* Digital Counter inside of PHY IO */
0084 #define D0S_ZERO        0x01C4  /* Digital Counter inside of PHY IO */
0085 #define D1S_ZERO        0x01C8  /* Digital Counter inside of PHY IO */
0086 #define D2S_ZERO        0x01CC  /* Digital Counter inside of PHY IO */
0087 #define D3S_ZERO        0x01D0  /* Digital Counter inside of PHY IO */
0088 
0089 #define PPI_CLRFLG      0x01E0  /* PRE Counters has reached set values */
0090 #define PPI_CLRSIPO     0x01E4  /* Clear SIPO values, Slave mode use only. */
0091 #define HSTIMEOUT       0x01F0  /* HS Rx Time Out Counter */
0092 #define HSTIMEOUTENABLE 0x01F4  /* Enable HS Rx Time Out Counter */
0093 #define DSI_STARTDSI    0x0204  /* START control bit of DSI-TX function */
0094 #define DSI_RX_START    1
0095 
0096 #define DSI_BUSYDSI     0x0208
0097 #define DSI_LANEENABLE  0x0210  /* Enables each lane at the Protocol layer. */
0098 #define DSI_LANESTATUS0 0x0214  /* Displays lane is in HS RX mode. */
0099 #define DSI_LANESTATUS1 0x0218  /* Displays lane is in ULPS or STOP state */
0100 
0101 #define DSI_INTSTATUS   0x0220  /* Interrupt Status */
0102 #define DSI_INTMASK     0x0224  /* Interrupt Mask */
0103 #define DSI_INTCLR      0x0228  /* Interrupt Clear */
0104 #define DSI_LPTXTO      0x0230  /* Low Power Tx Time Out Counter */
0105 
0106 #define DSIERRCNT       0x0300  /* DSI Error Count */
0107 #define APLCTRL         0x0400  /* Application Layer Control */
0108 #define RDPKTLN         0x0404  /* Command Read Packet Length */
0109 
0110 #define VPCTRL          0x0450  /* Video Path Control */
0111 #define HTIM1           0x0454  /* Horizontal Timing Control 1 */
0112 #define HTIM2           0x0458  /* Horizontal Timing Control 2 */
0113 #define VTIM1           0x045C  /* Vertical Timing Control 1 */
0114 #define VTIM2           0x0460  /* Vertical Timing Control 2 */
0115 #define VFUEN           0x0464  /* Video Frame Timing Update Enable */
0116 #define VFUEN_EN    BIT(0)  /* Upload Enable */
0117 
0118 /* Mux Input Select for LVDS LINK Input */
0119 #define LV_MX0003        0x0480  /* Bit 0 to 3 */
0120 #define LV_MX0407        0x0484  /* Bit 4 to 7 */
0121 #define LV_MX0811        0x0488  /* Bit 8 to 11 */
0122 #define LV_MX1215        0x048C  /* Bit 12 to 15 */
0123 #define LV_MX1619        0x0490  /* Bit 16 to 19 */
0124 #define LV_MX2023        0x0494  /* Bit 20 to 23 */
0125 #define LV_MX2427        0x0498  /* Bit 24 to 27 */
0126 #define LV_MX(b0, b1, b2, b3)   (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
0127                 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
0128 
0129 /* Input bit numbers used in mux registers */
0130 enum {
0131     LVI_R0,
0132     LVI_R1,
0133     LVI_R2,
0134     LVI_R3,
0135     LVI_R4,
0136     LVI_R5,
0137     LVI_R6,
0138     LVI_R7,
0139     LVI_G0,
0140     LVI_G1,
0141     LVI_G2,
0142     LVI_G3,
0143     LVI_G4,
0144     LVI_G5,
0145     LVI_G6,
0146     LVI_G7,
0147     LVI_B0,
0148     LVI_B1,
0149     LVI_B2,
0150     LVI_B3,
0151     LVI_B4,
0152     LVI_B5,
0153     LVI_B6,
0154     LVI_B7,
0155     LVI_HS,
0156     LVI_VS,
0157     LVI_DE,
0158     LVI_L0
0159 };
0160 
0161 #define LVCFG           0x049C  /* LVDS Configuration  */
0162 #define LVPHY0          0x04A0  /* LVDS PHY 0 */
0163 #define LV_PHY0_RST(v)          FLD_VAL(v, 22, 22) /* PHY reset */
0164 #define LV_PHY0_IS(v)           FLD_VAL(v, 15, 14)
0165 #define LV_PHY0_ND(v)           FLD_VAL(v, 4, 0) /* Frequency range select */
0166 #define LV_PHY0_PRBS_ON(v)      FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
0167 
0168 #define LVPHY1          0x04A4  /* LVDS PHY 1 */
0169 #define SYSSTAT         0x0500  /* System Status  */
0170 #define SYSRST          0x0504  /* System Reset  */
0171 
0172 #define SYS_RST_I2CS    BIT(0) /* Reset I2C-Slave controller */
0173 #define SYS_RST_I2CM    BIT(1) /* Reset I2C-Master controller */
0174 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
0175 #define SYS_RST_BM  BIT(3) /* Reset Bus Management controller */
0176 #define SYS_RST_DSIRX   BIT(4) /* Reset DSI-RX and App controller */
0177 #define SYS_RST_REG BIT(5) /* Reset Register module */
0178 
0179 /* GPIO Registers */
0180 #define GPIOC           0x0520  /* GPIO Control  */
0181 #define GPIOO           0x0524  /* GPIO Output  */
0182 #define GPIOI           0x0528  /* GPIO Input  */
0183 
0184 /* I2C Registers */
0185 #define I2CTIMCTRL      0x0540  /* I2C IF Timing and Enable Control */
0186 #define I2CMADDR        0x0544  /* I2C Master Addressing */
0187 #define WDATAQ          0x0548  /* Write Data Queue */
0188 #define RDATAQ          0x054C  /* Read Data Queue */
0189 
0190 /* Chip ID and Revision ID Register */
0191 #define IDREG           0x0580
0192 
0193 #define LPX_PERIOD      4
0194 #define TTA_GET         0x40000
0195 #define TTA_SURE        6
0196 #define SINGLE_LINK     1
0197 #define DUAL_LINK       2
0198 
0199 #define TC358775XBG_ID  0x00007500
0200 
0201 /* Debug Registers */
0202 #define DEBUG00         0x05A0  /* Debug */
0203 #define DEBUG01         0x05A4  /* LVDS Data */
0204 
0205 #define DSI_CLEN_BIT        BIT(0)
0206 #define DIVIDE_BY_3     3 /* PCLK=DCLK/3 */
0207 #define DIVIDE_BY_6     6 /* PCLK=DCLK/6 */
0208 #define LVCFG_LVEN_BIT      BIT(0)
0209 
0210 #define L0EN BIT(1)
0211 
0212 #define TC358775_VPCTRL_VSDELAY__MASK   0x3FF00000
0213 #define TC358775_VPCTRL_VSDELAY__SHIFT  20
0214 static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
0215 {
0216     return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
0217             TC358775_VPCTRL_VSDELAY__MASK;
0218 }
0219 
0220 #define TC358775_VPCTRL_OPXLFMT__MASK   0x00000100
0221 #define TC358775_VPCTRL_OPXLFMT__SHIFT  8
0222 static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
0223 {
0224     return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
0225             TC358775_VPCTRL_OPXLFMT__MASK;
0226 }
0227 
0228 #define TC358775_VPCTRL_MSF__MASK   0x00000001
0229 #define TC358775_VPCTRL_MSF__SHIFT  0
0230 static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
0231 {
0232     return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
0233             TC358775_VPCTRL_MSF__MASK;
0234 }
0235 
0236 #define TC358775_LVCFG_PCLKDIV__MASK    0x000000f0
0237 #define TC358775_LVCFG_PCLKDIV__SHIFT   4
0238 static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
0239 {
0240     return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
0241             TC358775_LVCFG_PCLKDIV__MASK;
0242 }
0243 
0244 #define TC358775_LVCFG_LVDLINK__MASK                         0x00000002
0245 #define TC358775_LVCFG_LVDLINK__SHIFT                        1
0246 static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
0247 {
0248     return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
0249             TC358775_LVCFG_LVDLINK__MASK;
0250 }
0251 
0252 enum tc358775_ports {
0253     TC358775_DSI_IN,
0254     TC358775_LVDS_OUT0,
0255     TC358775_LVDS_OUT1,
0256 };
0257 
0258 struct tc_data {
0259     struct i2c_client   *i2c;
0260     struct device       *dev;
0261 
0262     struct drm_bridge   bridge;
0263     struct drm_bridge   *panel_bridge;
0264 
0265     struct device_node *host_node;
0266     struct mipi_dsi_device *dsi;
0267     u8 num_dsi_lanes;
0268 
0269     struct regulator    *vdd;
0270     struct regulator    *vddio;
0271     struct gpio_desc    *reset_gpio;
0272     struct gpio_desc    *stby_gpio;
0273     u8          lvds_link; /* single-link or dual-link */
0274     u8          bpc;
0275 };
0276 
0277 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
0278 {
0279     return container_of(b, struct tc_data, bridge);
0280 }
0281 
0282 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
0283 {
0284     struct tc_data *tc = bridge_to_tc(bridge);
0285     struct device *dev = &tc->dsi->dev;
0286     int ret;
0287 
0288     ret = regulator_enable(tc->vddio);
0289     if (ret < 0)
0290         dev_err(dev, "regulator vddio enable failed, %d\n", ret);
0291     usleep_range(10000, 11000);
0292 
0293     ret = regulator_enable(tc->vdd);
0294     if (ret < 0)
0295         dev_err(dev, "regulator vdd enable failed, %d\n", ret);
0296     usleep_range(10000, 11000);
0297 
0298     gpiod_set_value(tc->stby_gpio, 0);
0299     usleep_range(10000, 11000);
0300 
0301     gpiod_set_value(tc->reset_gpio, 0);
0302     usleep_range(10, 20);
0303 }
0304 
0305 static void tc_bridge_post_disable(struct drm_bridge *bridge)
0306 {
0307     struct tc_data *tc = bridge_to_tc(bridge);
0308     struct device *dev = &tc->dsi->dev;
0309     int ret;
0310 
0311     gpiod_set_value(tc->reset_gpio, 1);
0312     usleep_range(10, 20);
0313 
0314     gpiod_set_value(tc->stby_gpio, 1);
0315     usleep_range(10000, 11000);
0316 
0317     ret = regulator_disable(tc->vdd);
0318     if (ret < 0)
0319         dev_err(dev, "regulator vdd disable failed, %d\n", ret);
0320     usleep_range(10000, 11000);
0321 
0322     ret = regulator_disable(tc->vddio);
0323     if (ret < 0)
0324         dev_err(dev, "regulator vddio disable failed, %d\n", ret);
0325     usleep_range(10000, 11000);
0326 }
0327 
0328 static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
0329 {
0330     int ret;
0331     u8 buf_addr[2];
0332 
0333     put_unaligned_be16(addr, buf_addr);
0334     ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
0335     if (ret < 0)
0336         goto fail;
0337 
0338     ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
0339     if (ret < 0)
0340         goto fail;
0341 
0342     pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
0343     return;
0344 
0345 fail:
0346     dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
0347         ret, addr);
0348 }
0349 
0350 static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
0351 {
0352     u8 data[6];
0353     int ret;
0354 
0355     put_unaligned_be16(addr, data);
0356     put_unaligned_le32(val, data + 2);
0357 
0358     ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
0359     if (ret < 0)
0360         dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
0361             ret, addr);
0362 }
0363 
0364 /* helper function to access bus_formats */
0365 static struct drm_connector *get_connector(struct drm_encoder *encoder)
0366 {
0367     struct drm_device *dev = encoder->dev;
0368     struct drm_connector *connector;
0369 
0370     list_for_each_entry(connector, &dev->mode_config.connector_list, head)
0371         if (connector->encoder == encoder)
0372             return connector;
0373 
0374     return NULL;
0375 }
0376 
0377 static void tc_bridge_enable(struct drm_bridge *bridge)
0378 {
0379     struct tc_data *tc = bridge_to_tc(bridge);
0380     u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
0381     u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
0382     u32 val = 0;
0383     u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
0384     struct drm_display_mode *mode;
0385     struct drm_connector *connector = get_connector(bridge->encoder);
0386 
0387     mode = &bridge->encoder->crtc->state->adjusted_mode;
0388 
0389     hback_porch = mode->htotal - mode->hsync_end;
0390     hsync_len  = mode->hsync_end - mode->hsync_start;
0391     vback_porch = mode->vtotal - mode->vsync_end;
0392     vsync_len  = mode->vsync_end - mode->vsync_start;
0393 
0394     htime1 = (hback_porch << 16) + hsync_len;
0395     vtime1 = (vback_porch << 16) + vsync_len;
0396 
0397     hfront_porch = mode->hsync_start - mode->hdisplay;
0398     hactive = mode->hdisplay;
0399     vfront_porch = mode->vsync_start - mode->vdisplay;
0400     vactive = mode->vdisplay;
0401 
0402     htime2 = (hfront_porch << 16) + hactive;
0403     vtime2 = (vfront_porch << 16) + vactive;
0404 
0405     d2l_read(tc->i2c, IDREG, &val);
0406 
0407     dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
0408          (val >> 8) & 0xFF, val & 0xFF);
0409 
0410     d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
0411           SYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS);
0412     usleep_range(30000, 40000);
0413 
0414     d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
0415     d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
0416     d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
0417     d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
0418     d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
0419     d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
0420 
0421     val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
0422     d2l_write(tc->i2c, PPI_LANEENABLE, val);
0423     d2l_write(tc->i2c, DSI_LANEENABLE, val);
0424 
0425     d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
0426     d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
0427 
0428     if (tc->bpc == 8)
0429         val = TC358775_VPCTRL_OPXLFMT(1);
0430     else /* bpc = 6; */
0431         val = TC358775_VPCTRL_MSF(1);
0432 
0433     dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
0434     clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);
0435     byteclk = dsiclk / 4;
0436     t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
0437     t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
0438     t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
0439         tc->num_dsi_lanes);
0440 
0441     vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
0442 
0443     val |= TC358775_VPCTRL_VSDELAY(vsdelay);
0444     d2l_write(tc->i2c, VPCTRL, val);
0445 
0446     d2l_write(tc->i2c, HTIM1, htime1);
0447     d2l_write(tc->i2c, VTIM1, vtime1);
0448     d2l_write(tc->i2c, HTIM2, htime2);
0449     d2l_write(tc->i2c, VTIM2, vtime2);
0450 
0451     d2l_write(tc->i2c, VFUEN, VFUEN_EN);
0452     d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
0453     d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
0454 
0455     dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
0456         connector->display_info.bus_formats[0],
0457         tc->bpc);
0458     /*
0459      * Default hardware register settings of tc358775 configured
0460      * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
0461      */
0462     if (connector->display_info.bus_formats[0] ==
0463         MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
0464         /* VESA-24 */
0465         d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
0466         d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
0467         d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
0468         d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
0469         d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
0470         d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
0471         d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
0472     } else { /*  MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
0473         d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
0474         d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0));
0475         d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0));
0476         d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
0477         d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2));
0478         d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
0479         d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0));
0480     }
0481 
0482     d2l_write(tc->i2c, VFUEN, VFUEN_EN);
0483 
0484     val = LVCFG_LVEN_BIT;
0485     if (tc->lvds_link == DUAL_LINK) {
0486         val |= TC358775_LVCFG_LVDLINK(1);
0487         val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
0488     } else {
0489         val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
0490     }
0491     d2l_write(tc->i2c, LVCFG, val);
0492 }
0493 
0494 static enum drm_mode_status
0495 tc_mode_valid(struct drm_bridge *bridge,
0496           const struct drm_display_info *info,
0497           const struct drm_display_mode *mode)
0498 {
0499     struct tc_data *tc = bridge_to_tc(bridge);
0500 
0501     /*
0502      * Maximum pixel clock speed 135MHz for single-link
0503      * 270MHz for dual-link
0504      */
0505     if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
0506         (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
0507         return MODE_CLOCK_HIGH;
0508 
0509     switch (info->bus_formats[0]) {
0510     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0511     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0512         /* RGB888 */
0513         tc->bpc = 8;
0514         break;
0515     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0516         /* RGB666 */
0517         tc->bpc = 6;
0518         break;
0519     default:
0520         dev_warn(tc->dev,
0521              "unsupported LVDS bus format 0x%04x\n",
0522              info->bus_formats[0]);
0523         return MODE_NOMODE;
0524     }
0525 
0526     return MODE_OK;
0527 }
0528 
0529 static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
0530 {
0531     struct device_node *endpoint;
0532     struct device_node *parent;
0533     struct device_node *remote;
0534     int dsi_lanes = -1;
0535 
0536     /*
0537      * To get the data-lanes of dsi, we need to access the dsi0_out of port1
0538      *  of dsi0 endpoint from bridge port0 of d2l_in
0539      */
0540     endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
0541                          TC358775_DSI_IN, -1);
0542     if (endpoint) {
0543         /* dsi0_out node */
0544         parent = of_graph_get_remote_port_parent(endpoint);
0545         of_node_put(endpoint);
0546         if (parent) {
0547             /* dsi0 port 1 */
0548             dsi_lanes = drm_of_get_data_lanes_count_ep(parent, 1, -1, 1, 4);
0549             of_node_put(parent);
0550         }
0551     }
0552 
0553     if (dsi_lanes < 0)
0554         return dsi_lanes;
0555 
0556     tc->num_dsi_lanes = dsi_lanes;
0557 
0558     tc->host_node = of_graph_get_remote_node(np, 0, 0);
0559     if (!tc->host_node)
0560         return -ENODEV;
0561 
0562     of_node_put(tc->host_node);
0563 
0564     tc->lvds_link = SINGLE_LINK;
0565     endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
0566                          TC358775_LVDS_OUT1, -1);
0567     if (endpoint) {
0568         remote = of_graph_get_remote_port_parent(endpoint);
0569         of_node_put(endpoint);
0570 
0571         if (remote) {
0572             if (of_device_is_available(remote))
0573                 tc->lvds_link = DUAL_LINK;
0574             of_node_put(remote);
0575         }
0576     }
0577 
0578     dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
0579     dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
0580 
0581     return 0;
0582 }
0583 
0584 static int tc_bridge_attach(struct drm_bridge *bridge,
0585                 enum drm_bridge_attach_flags flags)
0586 {
0587     struct tc_data *tc = bridge_to_tc(bridge);
0588 
0589     /* Attach the panel-bridge to the dsi bridge */
0590     return drm_bridge_attach(bridge->encoder, tc->panel_bridge,
0591                  &tc->bridge, flags);
0592 }
0593 
0594 static const struct drm_bridge_funcs tc_bridge_funcs = {
0595     .attach = tc_bridge_attach,
0596     .pre_enable = tc_bridge_pre_enable,
0597     .enable = tc_bridge_enable,
0598     .mode_valid = tc_mode_valid,
0599     .post_disable = tc_bridge_post_disable,
0600 };
0601 
0602 static int tc_attach_host(struct tc_data *tc)
0603 {
0604     struct device *dev = &tc->i2c->dev;
0605     struct mipi_dsi_host *host;
0606     struct mipi_dsi_device *dsi;
0607     int ret;
0608     const struct mipi_dsi_device_info info = { .type = "tc358775",
0609                             .channel = 0,
0610                             .node = NULL,
0611                         };
0612 
0613     host = of_find_mipi_dsi_host_by_node(tc->host_node);
0614     if (!host) {
0615         dev_err(dev, "failed to find dsi host\n");
0616         return -EPROBE_DEFER;
0617     }
0618 
0619     dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
0620     if (IS_ERR(dsi)) {
0621         dev_err(dev, "failed to create dsi device\n");
0622         return PTR_ERR(dsi);
0623     }
0624 
0625     tc->dsi = dsi;
0626 
0627     dsi->lanes = tc->num_dsi_lanes;
0628     dsi->format = MIPI_DSI_FMT_RGB888;
0629     dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
0630 
0631     ret = devm_mipi_dsi_attach(dev, dsi);
0632     if (ret < 0) {
0633         dev_err(dev, "failed to attach dsi to host\n");
0634         return ret;
0635     }
0636 
0637     return 0;
0638 }
0639 
0640 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
0641 {
0642     struct device *dev = &client->dev;
0643     struct tc_data *tc;
0644     int ret;
0645 
0646     tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
0647     if (!tc)
0648         return -ENOMEM;
0649 
0650     tc->dev = dev;
0651     tc->i2c = client;
0652 
0653     tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
0654                           TC358775_LVDS_OUT0, 0);
0655     if (IS_ERR(tc->panel_bridge))
0656         return PTR_ERR(tc->panel_bridge);
0657 
0658     ret = tc358775_parse_dt(dev->of_node, tc);
0659     if (ret)
0660         return ret;
0661 
0662     tc->vddio = devm_regulator_get(dev, "vddio-supply");
0663     if (IS_ERR(tc->vddio)) {
0664         ret = PTR_ERR(tc->vddio);
0665         dev_err(dev, "vddio-supply not found\n");
0666         return ret;
0667     }
0668 
0669     tc->vdd = devm_regulator_get(dev, "vdd-supply");
0670     if (IS_ERR(tc->vdd)) {
0671         ret = PTR_ERR(tc->vdd);
0672         dev_err(dev, "vdd-supply not found\n");
0673         return ret;
0674     }
0675 
0676     tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH);
0677     if (IS_ERR(tc->stby_gpio)) {
0678         ret = PTR_ERR(tc->stby_gpio);
0679         dev_err(dev, "cannot get stby-gpio %d\n", ret);
0680         return ret;
0681     }
0682 
0683     tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
0684     if (IS_ERR(tc->reset_gpio)) {
0685         ret = PTR_ERR(tc->reset_gpio);
0686         dev_err(dev, "cannot get reset-gpios %d\n", ret);
0687         return ret;
0688     }
0689 
0690     tc->bridge.funcs = &tc_bridge_funcs;
0691     tc->bridge.of_node = dev->of_node;
0692     drm_bridge_add(&tc->bridge);
0693 
0694     i2c_set_clientdata(client, tc);
0695 
0696     ret = tc_attach_host(tc);
0697     if (ret)
0698         goto err_bridge_remove;
0699 
0700     return 0;
0701 
0702 err_bridge_remove:
0703     drm_bridge_remove(&tc->bridge);
0704     return ret;
0705 }
0706 
0707 static int tc_remove(struct i2c_client *client)
0708 {
0709     struct tc_data *tc = i2c_get_clientdata(client);
0710 
0711     drm_bridge_remove(&tc->bridge);
0712 
0713     return 0;
0714 }
0715 
0716 static const struct i2c_device_id tc358775_i2c_ids[] = {
0717     { "tc358775", 0 },
0718     { }
0719 };
0720 MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
0721 
0722 static const struct of_device_id tc358775_of_ids[] = {
0723     { .compatible = "toshiba,tc358775", },
0724     { }
0725 };
0726 MODULE_DEVICE_TABLE(of, tc358775_of_ids);
0727 
0728 static struct i2c_driver tc358775_driver = {
0729     .driver = {
0730         .name = "tc358775",
0731         .of_match_table = tc358775_of_ids,
0732     },
0733     .id_table = tc358775_i2c_ids,
0734     .probe = tc_probe,
0735     .remove = tc_remove,
0736 };
0737 module_i2c_driver(tc358775_driver);
0738 
0739 MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
0740 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
0741 MODULE_LICENSE("GPL v2");
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