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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
0004  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/gpio/consumer.h>
0010 #include <linux/i2c.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/regmap.h>
0014 #include <linux/regulator/consumer.h>
0015 #include <linux/slab.h>
0016 
0017 #include <drm/drm_atomic_helper.h>
0018 #include <drm/drm_crtc_helper.h>
0019 #include <drm/drm_drv.h>
0020 #include <drm/drm_mipi_dsi.h>
0021 #include <drm/drm_of.h>
0022 #include <drm/drm_panel.h>
0023 #include <video/mipi_display.h>
0024 #include <video/videomode.h>
0025 
0026 /* Global (16-bit addressable) */
0027 #define TC358768_CHIPID         0x0000
0028 #define TC358768_SYSCTL         0x0002
0029 #define TC358768_CONFCTL        0x0004
0030 #define TC358768_VSDLY          0x0006
0031 #define TC358768_DATAFMT        0x0008
0032 #define TC358768_GPIOEN         0x000E
0033 #define TC358768_GPIODIR        0x0010
0034 #define TC358768_GPIOIN         0x0012
0035 #define TC358768_GPIOOUT        0x0014
0036 #define TC358768_PLLCTL0        0x0016
0037 #define TC358768_PLLCTL1        0x0018
0038 #define TC358768_CMDBYTE        0x0022
0039 #define TC358768_PP_MISC        0x0032
0040 #define TC358768_DSITX_DT       0x0050
0041 #define TC358768_FIFOSTATUS     0x00F8
0042 
0043 /* Debug (16-bit addressable) */
0044 #define TC358768_VBUFCTRL       0x00E0
0045 #define TC358768_DBG_WIDTH      0x00E2
0046 #define TC358768_DBG_VBLANK     0x00E4
0047 #define TC358768_DBG_DATA       0x00E8
0048 
0049 /* TX PHY (32-bit addressable) */
0050 #define TC358768_CLW_DPHYCONTTX     0x0100
0051 #define TC358768_D0W_DPHYCONTTX     0x0104
0052 #define TC358768_D1W_DPHYCONTTX     0x0108
0053 #define TC358768_D2W_DPHYCONTTX     0x010C
0054 #define TC358768_D3W_DPHYCONTTX     0x0110
0055 #define TC358768_CLW_CNTRL      0x0140
0056 #define TC358768_D0W_CNTRL      0x0144
0057 #define TC358768_D1W_CNTRL      0x0148
0058 #define TC358768_D2W_CNTRL      0x014C
0059 #define TC358768_D3W_CNTRL      0x0150
0060 
0061 /* TX PPI (32-bit addressable) */
0062 #define TC358768_STARTCNTRL     0x0204
0063 #define TC358768_DSITXSTATUS        0x0208
0064 #define TC358768_LINEINITCNT        0x0210
0065 #define TC358768_LPTXTIMECNT        0x0214
0066 #define TC358768_TCLK_HEADERCNT     0x0218
0067 #define TC358768_TCLK_TRAILCNT      0x021C
0068 #define TC358768_THS_HEADERCNT      0x0220
0069 #define TC358768_TWAKEUP        0x0224
0070 #define TC358768_TCLK_POSTCNT       0x0228
0071 #define TC358768_THS_TRAILCNT       0x022C
0072 #define TC358768_HSTXVREGCNT        0x0230
0073 #define TC358768_HSTXVREGEN     0x0234
0074 #define TC358768_TXOPTIONCNTRL      0x0238
0075 #define TC358768_BTACNTRL1      0x023C
0076 
0077 /* TX CTRL (32-bit addressable) */
0078 #define TC358768_DSI_CONTROL        0x040C
0079 #define TC358768_DSI_STATUS     0x0410
0080 #define TC358768_DSI_INT        0x0414
0081 #define TC358768_DSI_INT_ENA        0x0418
0082 #define TC358768_DSICMD_RDFIFO      0x0430
0083 #define TC358768_DSI_ACKERR     0x0434
0084 #define TC358768_DSI_ACKERR_INTENA  0x0438
0085 #define TC358768_DSI_ACKERR_HALT    0x043c
0086 #define TC358768_DSI_RXERR      0x0440
0087 #define TC358768_DSI_RXERR_INTENA   0x0444
0088 #define TC358768_DSI_RXERR_HALT     0x0448
0089 #define TC358768_DSI_ERR        0x044C
0090 #define TC358768_DSI_ERR_INTENA     0x0450
0091 #define TC358768_DSI_ERR_HALT       0x0454
0092 #define TC358768_DSI_CONFW      0x0500
0093 #define TC358768_DSI_LPCMD      0x0500
0094 #define TC358768_DSI_RESET      0x0504
0095 #define TC358768_DSI_INT_CLR        0x050C
0096 #define TC358768_DSI_START      0x0518
0097 
0098 /* DSITX CTRL (16-bit addressable) */
0099 #define TC358768_DSICMD_TX      0x0600
0100 #define TC358768_DSICMD_TYPE        0x0602
0101 #define TC358768_DSICMD_WC      0x0604
0102 #define TC358768_DSICMD_WD0     0x0610
0103 #define TC358768_DSICMD_WD1     0x0612
0104 #define TC358768_DSICMD_WD2     0x0614
0105 #define TC358768_DSICMD_WD3     0x0616
0106 #define TC358768_DSI_EVENT      0x0620
0107 #define TC358768_DSI_VSW        0x0622
0108 #define TC358768_DSI_VBPR       0x0624
0109 #define TC358768_DSI_VACT       0x0626
0110 #define TC358768_DSI_HSW        0x0628
0111 #define TC358768_DSI_HBPR       0x062A
0112 #define TC358768_DSI_HACT       0x062C
0113 
0114 /* TC358768_DSI_CONTROL (0x040C) register */
0115 #define TC358768_DSI_CONTROL_DIS_MODE   BIT(15)
0116 #define TC358768_DSI_CONTROL_TXMD   BIT(7)
0117 #define TC358768_DSI_CONTROL_HSCKMD BIT(5)
0118 #define TC358768_DSI_CONTROL_EOTDIS BIT(0)
0119 
0120 /* TC358768_DSI_CONFW (0x0500) register */
0121 #define TC358768_DSI_CONFW_MODE_SET (5 << 29)
0122 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
0123 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
0124 
0125 static const char * const tc358768_supplies[] = {
0126     "vddc", "vddmipi", "vddio"
0127 };
0128 
0129 struct tc358768_dsi_output {
0130     struct mipi_dsi_device *dev;
0131     struct drm_panel *panel;
0132     struct drm_bridge *bridge;
0133 };
0134 
0135 struct tc358768_priv {
0136     struct device *dev;
0137     struct regmap *regmap;
0138     struct gpio_desc *reset_gpio;
0139     struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
0140     struct clk *refclk;
0141     int enabled;
0142     int error;
0143 
0144     struct mipi_dsi_host dsi_host;
0145     struct drm_bridge bridge;
0146     struct tc358768_dsi_output output;
0147 
0148     u32 pd_lines; /* number of Parallel Port Input Data Lines */
0149     u32 dsi_lanes; /* number of DSI Lanes */
0150 
0151     /* Parameters for PLL programming */
0152     u32 fbd;    /* PLL feedback divider */
0153     u32 prd;    /* PLL input divider */
0154     u32 frs;    /* PLL Freqency range for HSCK (post divider) */
0155 
0156     u32 dsiclk; /* pll_clk / 2 */
0157 };
0158 
0159 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
0160                              *host)
0161 {
0162     return container_of(host, struct tc358768_priv, dsi_host);
0163 }
0164 
0165 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
0166                                *bridge)
0167 {
0168     return container_of(bridge, struct tc358768_priv, bridge);
0169 }
0170 
0171 static int tc358768_clear_error(struct tc358768_priv *priv)
0172 {
0173     int ret = priv->error;
0174 
0175     priv->error = 0;
0176     return ret;
0177 }
0178 
0179 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
0180 {
0181     /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
0182     int tmpval = val;
0183     size_t count = 2;
0184 
0185     if (priv->error)
0186         return;
0187 
0188     /* 16-bit register? */
0189     if (reg < 0x100 || reg >= 0x600)
0190         count = 1;
0191 
0192     priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
0193 }
0194 
0195 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
0196 {
0197     size_t count = 2;
0198 
0199     if (priv->error)
0200         return;
0201 
0202     /* 16-bit register? */
0203     if (reg < 0x100 || reg >= 0x600) {
0204         *val = 0;
0205         count = 1;
0206     }
0207 
0208     priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
0209 }
0210 
0211 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
0212                  u32 val)
0213 {
0214     u32 tmp, orig;
0215 
0216     tc358768_read(priv, reg, &orig);
0217     tmp = orig & ~mask;
0218     tmp |= val & mask;
0219     if (tmp != orig)
0220         tc358768_write(priv, reg, tmp);
0221 }
0222 
0223 static int tc358768_sw_reset(struct tc358768_priv *priv)
0224 {
0225     /* Assert Reset */
0226     tc358768_write(priv, TC358768_SYSCTL, 1);
0227     /* Release Reset, Exit Sleep */
0228     tc358768_write(priv, TC358768_SYSCTL, 0);
0229 
0230     return tc358768_clear_error(priv);
0231 }
0232 
0233 static void tc358768_hw_enable(struct tc358768_priv *priv)
0234 {
0235     int ret;
0236 
0237     if (priv->enabled)
0238         return;
0239 
0240     ret = clk_prepare_enable(priv->refclk);
0241     if (ret < 0)
0242         dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
0243 
0244     ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
0245     if (ret < 0)
0246         dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
0247 
0248     if (priv->reset_gpio)
0249         usleep_range(200, 300);
0250 
0251     /*
0252      * The RESX is active low (GPIO_ACTIVE_LOW).
0253      * DEASSERT (value = 0) the reset_gpio to enable the chip
0254      */
0255     gpiod_set_value_cansleep(priv->reset_gpio, 0);
0256 
0257     /* wait for encoder clocks to stabilize */
0258     usleep_range(1000, 2000);
0259 
0260     priv->enabled = true;
0261 }
0262 
0263 static void tc358768_hw_disable(struct tc358768_priv *priv)
0264 {
0265     int ret;
0266 
0267     if (!priv->enabled)
0268         return;
0269 
0270     /*
0271      * The RESX is active low (GPIO_ACTIVE_LOW).
0272      * ASSERT (value = 1) the reset_gpio to disable the chip
0273      */
0274     gpiod_set_value_cansleep(priv->reset_gpio, 1);
0275 
0276     ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
0277                      priv->supplies);
0278     if (ret < 0)
0279         dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
0280 
0281     clk_disable_unprepare(priv->refclk);
0282 
0283     priv->enabled = false;
0284 }
0285 
0286 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
0287 {
0288     return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
0289 }
0290 
0291 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
0292 {
0293     return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
0294 }
0295 
0296 static int tc358768_calc_pll(struct tc358768_priv *priv,
0297                  const struct drm_display_mode *mode,
0298                  bool verify_only)
0299 {
0300     static const u32 frs_limits[] = {
0301         1000000000,
0302         500000000,
0303         250000000,
0304         125000000,
0305         62500000
0306     };
0307     unsigned long refclk;
0308     u32 prd, target_pll, i, max_pll, min_pll;
0309     u32 frs, best_diff, best_pll, best_prd, best_fbd;
0310 
0311     target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
0312 
0313     /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
0314 
0315     for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
0316         if (target_pll >= frs_limits[i])
0317             break;
0318 
0319     if (i == ARRAY_SIZE(frs_limits) || i == 0)
0320         return -EINVAL;
0321 
0322     frs = i - 1;
0323     max_pll = frs_limits[i - 1];
0324     min_pll = frs_limits[i];
0325 
0326     refclk = clk_get_rate(priv->refclk);
0327 
0328     best_diff = UINT_MAX;
0329     best_pll = 0;
0330     best_prd = 0;
0331     best_fbd = 0;
0332 
0333     for (prd = 0; prd < 16; ++prd) {
0334         u32 divisor = (prd + 1) * (1 << frs);
0335         u32 fbd;
0336 
0337         for (fbd = 0; fbd < 512; ++fbd) {
0338             u32 pll, diff;
0339 
0340             pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
0341 
0342             if (pll >= max_pll || pll < min_pll)
0343                 continue;
0344 
0345             diff = max(pll, target_pll) - min(pll, target_pll);
0346 
0347             if (diff < best_diff) {
0348                 best_diff = diff;
0349                 best_pll = pll;
0350                 best_prd = prd;
0351                 best_fbd = fbd;
0352 
0353                 if (best_diff == 0)
0354                     goto found;
0355             }
0356         }
0357     }
0358 
0359     if (best_diff == UINT_MAX) {
0360         dev_err(priv->dev, "could not find suitable PLL setup\n");
0361         return -EINVAL;
0362     }
0363 
0364 found:
0365     if (verify_only)
0366         return 0;
0367 
0368     priv->fbd = best_fbd;
0369     priv->prd = best_prd;
0370     priv->frs = frs;
0371     priv->dsiclk = best_pll / 2;
0372 
0373     return 0;
0374 }
0375 
0376 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
0377                     struct mipi_dsi_device *dev)
0378 {
0379     struct tc358768_priv *priv = dsi_host_to_tc358768(host);
0380     struct drm_bridge *bridge;
0381     struct drm_panel *panel;
0382     struct device_node *ep;
0383     int ret;
0384 
0385     if (dev->lanes > 4) {
0386         dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
0387             dev->lanes);
0388         return -EINVAL;
0389     }
0390 
0391     /*
0392      * tc358768 supports both Video and Pulse mode, but the driver only
0393      * implements Video (event) mode currently
0394      */
0395     if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
0396         dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
0397         return -ENOTSUPP;
0398     }
0399 
0400     /*
0401      * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
0402      * RGB888 is verified.
0403      */
0404     if (dev->format != MIPI_DSI_FMT_RGB888) {
0405         dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
0406         return -ENOTSUPP;
0407     }
0408 
0409     ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
0410                       &bridge);
0411     if (ret)
0412         return ret;
0413 
0414     if (panel) {
0415         bridge = drm_panel_bridge_add_typed(panel,
0416                             DRM_MODE_CONNECTOR_DSI);
0417         if (IS_ERR(bridge))
0418             return PTR_ERR(bridge);
0419     }
0420 
0421     priv->output.dev = dev;
0422     priv->output.bridge = bridge;
0423     priv->output.panel = panel;
0424 
0425     priv->dsi_lanes = dev->lanes;
0426 
0427     /* get input ep (port0/endpoint0) */
0428     ret = -EINVAL;
0429     ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
0430     if (ep) {
0431         ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
0432 
0433         of_node_put(ep);
0434     }
0435 
0436     if (ret)
0437         priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
0438 
0439     drm_bridge_add(&priv->bridge);
0440 
0441     return 0;
0442 }
0443 
0444 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
0445                     struct mipi_dsi_device *dev)
0446 {
0447     struct tc358768_priv *priv = dsi_host_to_tc358768(host);
0448 
0449     drm_bridge_remove(&priv->bridge);
0450     if (priv->output.panel)
0451         drm_panel_bridge_remove(priv->output.bridge);
0452 
0453     return 0;
0454 }
0455 
0456 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
0457                       const struct mipi_dsi_msg *msg)
0458 {
0459     struct tc358768_priv *priv = dsi_host_to_tc358768(host);
0460     struct mipi_dsi_packet packet;
0461     int ret;
0462 
0463     if (!priv->enabled) {
0464         dev_err(priv->dev, "Bridge is not enabled\n");
0465         return -ENODEV;
0466     }
0467 
0468     if (msg->rx_len) {
0469         dev_warn(priv->dev, "MIPI rx is not supported\n");
0470         return -ENOTSUPP;
0471     }
0472 
0473     if (msg->tx_len > 8) {
0474         dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
0475         return -ENOTSUPP;
0476     }
0477 
0478     ret = mipi_dsi_create_packet(&packet, msg);
0479     if (ret)
0480         return ret;
0481 
0482     if (mipi_dsi_packet_format_is_short(msg->type)) {
0483         tc358768_write(priv, TC358768_DSICMD_TYPE,
0484                    (0x10 << 8) | (packet.header[0] & 0x3f));
0485         tc358768_write(priv, TC358768_DSICMD_WC, 0);
0486         tc358768_write(priv, TC358768_DSICMD_WD0,
0487                    (packet.header[2] << 8) | packet.header[1]);
0488     } else {
0489         int i;
0490 
0491         tc358768_write(priv, TC358768_DSICMD_TYPE,
0492                    (0x40 << 8) | (packet.header[0] & 0x3f));
0493         tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
0494         for (i = 0; i < packet.payload_length; i += 2) {
0495             u16 val = packet.payload[i];
0496 
0497             if (i + 1 < packet.payload_length)
0498                 val |= packet.payload[i + 1] << 8;
0499 
0500             tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
0501         }
0502     }
0503 
0504     /* start transfer */
0505     tc358768_write(priv, TC358768_DSICMD_TX, 1);
0506 
0507     ret = tc358768_clear_error(priv);
0508     if (ret)
0509         dev_warn(priv->dev, "Software disable failed: %d\n", ret);
0510     else
0511         ret = packet.size;
0512 
0513     return ret;
0514 }
0515 
0516 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
0517     .attach = tc358768_dsi_host_attach,
0518     .detach = tc358768_dsi_host_detach,
0519     .transfer = tc358768_dsi_host_transfer,
0520 };
0521 
0522 static int tc358768_bridge_attach(struct drm_bridge *bridge,
0523                   enum drm_bridge_attach_flags flags)
0524 {
0525     struct tc358768_priv *priv = bridge_to_tc358768(bridge);
0526 
0527     if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
0528         dev_err(priv->dev, "needs atomic updates support\n");
0529         return -ENOTSUPP;
0530     }
0531 
0532     return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
0533                  flags);
0534 }
0535 
0536 static enum drm_mode_status
0537 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
0538                const struct drm_display_info *info,
0539                const struct drm_display_mode *mode)
0540 {
0541     struct tc358768_priv *priv = bridge_to_tc358768(bridge);
0542 
0543     if (tc358768_calc_pll(priv, mode, true))
0544         return MODE_CLOCK_RANGE;
0545 
0546     return MODE_OK;
0547 }
0548 
0549 static void tc358768_bridge_disable(struct drm_bridge *bridge)
0550 {
0551     struct tc358768_priv *priv = bridge_to_tc358768(bridge);
0552     int ret;
0553 
0554     /* set FrmStop */
0555     tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
0556 
0557     /* wait at least for one frame */
0558     msleep(50);
0559 
0560     /* clear PP_en */
0561     tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
0562 
0563     /* set RstPtr */
0564     tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
0565 
0566     ret = tc358768_clear_error(priv);
0567     if (ret)
0568         dev_warn(priv->dev, "Software disable failed: %d\n", ret);
0569 }
0570 
0571 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
0572 {
0573     struct tc358768_priv *priv = bridge_to_tc358768(bridge);
0574 
0575     tc358768_hw_disable(priv);
0576 }
0577 
0578 static int tc358768_setup_pll(struct tc358768_priv *priv,
0579                   const struct drm_display_mode *mode)
0580 {
0581     u32 fbd, prd, frs;
0582     int ret;
0583 
0584     ret = tc358768_calc_pll(priv, mode, false);
0585     if (ret) {
0586         dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
0587         return ret;
0588     }
0589 
0590     fbd = priv->fbd;
0591     prd = priv->prd;
0592     frs = priv->frs;
0593 
0594     dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
0595         clk_get_rate(priv->refclk), fbd, prd, frs);
0596     dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n",
0597         priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
0598     dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
0599         tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
0600         mode->clock * 1000);
0601 
0602     /* PRD[15:12] FBD[8:0] */
0603     tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
0604 
0605     /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
0606     tc358768_write(priv, TC358768_PLLCTL1,
0607                (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
0608 
0609     /* wait for lock */
0610     usleep_range(1000, 2000);
0611 
0612     /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
0613     tc358768_write(priv, TC358768_PLLCTL1,
0614                (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
0615 
0616     return tc358768_clear_error(priv);
0617 }
0618 
0619 #define TC358768_PRECISION  1000
0620 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk)
0621 {
0622     return (ns * TC358768_PRECISION + period_nsk) / period_nsk;
0623 }
0624 
0625 static u32 tc358768_to_ns(u32 nsk)
0626 {
0627     return (nsk / TC358768_PRECISION);
0628 }
0629 
0630 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
0631 {
0632     struct tc358768_priv *priv = bridge_to_tc358768(bridge);
0633     struct mipi_dsi_device *dsi_dev = priv->output.dev;
0634     unsigned long mode_flags = dsi_dev->mode_flags;
0635     u32 val, val2, lptxcnt, hact, data_type;
0636     const struct drm_display_mode *mode;
0637     u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
0638     u32 dsiclk, dsibclk, video_start;
0639     const u32 internal_delay = 40;
0640     int ret, i;
0641 
0642     if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
0643         dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n");
0644         mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
0645     }
0646 
0647     tc358768_hw_enable(priv);
0648 
0649     ret = tc358768_sw_reset(priv);
0650     if (ret) {
0651         dev_err(priv->dev, "Software reset failed: %d\n", ret);
0652         tc358768_hw_disable(priv);
0653         return;
0654     }
0655 
0656     mode = &bridge->encoder->crtc->state->adjusted_mode;
0657     ret = tc358768_setup_pll(priv, mode);
0658     if (ret) {
0659         dev_err(priv->dev, "PLL setup failed: %d\n", ret);
0660         tc358768_hw_disable(priv);
0661         return;
0662     }
0663 
0664     dsiclk = priv->dsiclk;
0665     dsibclk = dsiclk / 4;
0666 
0667     /* Data Format Control Register */
0668     val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
0669     switch (dsi_dev->format) {
0670     case MIPI_DSI_FMT_RGB888:
0671         val |= (0x3 << 4);
0672         hact = mode->hdisplay * 3;
0673         video_start = (mode->htotal - mode->hsync_start) * 3;
0674         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
0675         break;
0676     case MIPI_DSI_FMT_RGB666:
0677         val |= (0x4 << 4);
0678         hact = mode->hdisplay * 3;
0679         video_start = (mode->htotal - mode->hsync_start) * 3;
0680         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
0681         break;
0682 
0683     case MIPI_DSI_FMT_RGB666_PACKED:
0684         val |= (0x4 << 4) | BIT(3);
0685         hact = mode->hdisplay * 18 / 8;
0686         video_start = (mode->htotal - mode->hsync_start) * 18 / 8;
0687         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
0688         break;
0689 
0690     case MIPI_DSI_FMT_RGB565:
0691         val |= (0x5 << 4);
0692         hact = mode->hdisplay * 2;
0693         video_start = (mode->htotal - mode->hsync_start) * 2;
0694         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
0695         break;
0696     default:
0697         dev_err(priv->dev, "Invalid data format (%u)\n",
0698             dsi_dev->format);
0699         tc358768_hw_disable(priv);
0700         return;
0701     }
0702 
0703     /* VSDly[9:0] */
0704     video_start = max(video_start, internal_delay + 1) - internal_delay;
0705     tc358768_write(priv, TC358768_VSDLY, video_start);
0706 
0707     tc358768_write(priv, TC358768_DATAFMT, val);
0708     tc358768_write(priv, TC358768_DSITX_DT, data_type);
0709 
0710     /* Enable D-PHY (HiZ->LP11) */
0711     tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
0712     /* Enable lanes */
0713     for (i = 0; i < dsi_dev->lanes; i++)
0714         tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
0715 
0716     /* DSI Timings */
0717     dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION,
0718                   dsibclk);
0719     dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
0720     ui_nsk = dsiclk_nsk / 2;
0721     phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
0722     dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
0723     dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
0724     dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
0725     dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
0726 
0727     /* LP11 > 100us for D-PHY Rx Init */
0728     val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
0729     dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
0730     tc358768_write(priv, TC358768_LINEINITCNT, val);
0731 
0732     /* LPTimeCnt > 50ns */
0733     val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
0734     lptxcnt = val;
0735     dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
0736     tc358768_write(priv, TC358768_LPTXTIMECNT, val);
0737 
0738     /* 38ns < TCLK_PREPARE < 95ns */
0739     val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
0740     /* TCLK_PREPARE > 300ns */
0741     val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
0742                   dsibclk_nsk);
0743     val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
0744     dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
0745     tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
0746 
0747     /* TCLK_TRAIL > 60ns + 3*UI */
0748     val = 60 + tc358768_to_ns(3 * ui_nsk);
0749     val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
0750     dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
0751     tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
0752 
0753     /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
0754     val = 50 + tc358768_to_ns(4 * ui_nsk);
0755     val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
0756     /* THS_ZERO > 145ns + 10*UI */
0757     val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
0758     val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
0759     dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
0760     tc358768_write(priv, TC358768_THS_HEADERCNT, val);
0761 
0762     /* TWAKEUP > 1ms in lptxcnt steps */
0763     val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
0764     val = val / (lptxcnt + 1) - 1;
0765     dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
0766     tc358768_write(priv, TC358768_TWAKEUP, val);
0767 
0768     /* TCLK_POSTCNT > 60ns + 52*UI */
0769     val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
0770                  dsibclk_nsk) - 3;
0771     dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
0772     tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
0773 
0774     /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
0775     val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
0776                  dsibclk_nsk) - 5;
0777     dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
0778     tc358768_write(priv, TC358768_THS_TRAILCNT, val);
0779 
0780     val = BIT(0);
0781     for (i = 0; i < dsi_dev->lanes; i++)
0782         val |= BIT(i + 1);
0783     tc358768_write(priv, TC358768_HSTXVREGEN, val);
0784 
0785     if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
0786         tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
0787 
0788     /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
0789     val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
0790     val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
0791     val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
0792                   dsibclk_nsk) - 2;
0793     val = val << 16 | val2;
0794     dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
0795     tc358768_write(priv, TC358768_BTACNTRL1, val);
0796 
0797     /* START[0] */
0798     tc358768_write(priv, TC358768_STARTCNTRL, 1);
0799 
0800     if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
0801         /* Set pulse mode */
0802         tc358768_write(priv, TC358768_DSI_EVENT, 0);
0803 
0804         /* vact */
0805         tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
0806 
0807         /* vsw */
0808         tc358768_write(priv, TC358768_DSI_VSW,
0809                    mode->vsync_end - mode->vsync_start);
0810         /* vbp */
0811         tc358768_write(priv, TC358768_DSI_VBPR,
0812                    mode->vtotal - mode->vsync_end);
0813 
0814         /* hsw * byteclk * ndl / pclk */
0815         val = (u32)div_u64((mode->hsync_end - mode->hsync_start) *
0816                    ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
0817                    mode->clock * 1000);
0818         tc358768_write(priv, TC358768_DSI_HSW, val);
0819 
0820         /* hbp * byteclk * ndl / pclk */
0821         val = (u32)div_u64((mode->htotal - mode->hsync_end) *
0822                    ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
0823                    mode->clock * 1000);
0824         tc358768_write(priv, TC358768_DSI_HBPR, val);
0825     } else {
0826         /* Set event mode */
0827         tc358768_write(priv, TC358768_DSI_EVENT, 1);
0828 
0829         /* vact */
0830         tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
0831 
0832         /* vsw (+ vbp) */
0833         tc358768_write(priv, TC358768_DSI_VSW,
0834                    mode->vtotal - mode->vsync_start);
0835         /* vbp (not used in event mode) */
0836         tc358768_write(priv, TC358768_DSI_VBPR, 0);
0837 
0838         /* (hsw + hbp) * byteclk * ndl / pclk */
0839         val = (u32)div_u64((mode->htotal - mode->hsync_start) *
0840                    ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
0841                    mode->clock * 1000);
0842         tc358768_write(priv, TC358768_DSI_HSW, val);
0843 
0844         /* hbp (not used in event mode) */
0845         tc358768_write(priv, TC358768_DSI_HBPR, 0);
0846     }
0847 
0848     /* hact (bytes) */
0849     tc358768_write(priv, TC358768_DSI_HACT, hact);
0850 
0851     /* VSYNC polarity */
0852     if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
0853         tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
0854     /* HSYNC polarity */
0855     if (mode->flags & DRM_MODE_FLAG_PHSYNC)
0856         tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
0857 
0858     /* Start DSI Tx */
0859     tc358768_write(priv, TC358768_DSI_START, 0x1);
0860 
0861     /* Configure DSI_Control register */
0862     val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
0863     val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
0864            0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
0865     tc358768_write(priv, TC358768_DSI_CONFW, val);
0866 
0867     val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
0868     val |= (dsi_dev->lanes - 1) << 1;
0869 
0870     if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
0871         val |= TC358768_DSI_CONTROL_TXMD;
0872 
0873     if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
0874         val |= TC358768_DSI_CONTROL_HSCKMD;
0875 
0876     if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
0877         val |= TC358768_DSI_CONTROL_EOTDIS;
0878 
0879     tc358768_write(priv, TC358768_DSI_CONFW, val);
0880 
0881     val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
0882     val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
0883     tc358768_write(priv, TC358768_DSI_CONFW, val);
0884 
0885     ret = tc358768_clear_error(priv);
0886     if (ret) {
0887         dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret);
0888         tc358768_bridge_disable(bridge);
0889         tc358768_bridge_post_disable(bridge);
0890     }
0891 }
0892 
0893 static void tc358768_bridge_enable(struct drm_bridge *bridge)
0894 {
0895     struct tc358768_priv *priv = bridge_to_tc358768(bridge);
0896     int ret;
0897 
0898     if (!priv->enabled) {
0899         dev_err(priv->dev, "Bridge is not enabled\n");
0900         return;
0901     }
0902 
0903     /* clear FrmStop and RstPtr */
0904     tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
0905 
0906     /* set PP_en */
0907     tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
0908 
0909     ret = tc358768_clear_error(priv);
0910     if (ret) {
0911         dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
0912         tc358768_bridge_disable(bridge);
0913         tc358768_bridge_post_disable(bridge);
0914     }
0915 }
0916 
0917 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
0918     .attach = tc358768_bridge_attach,
0919     .mode_valid = tc358768_bridge_mode_valid,
0920     .pre_enable = tc358768_bridge_pre_enable,
0921     .enable = tc358768_bridge_enable,
0922     .disable = tc358768_bridge_disable,
0923     .post_disable = tc358768_bridge_post_disable,
0924 };
0925 
0926 static const struct drm_bridge_timings default_tc358768_timings = {
0927     .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
0928          | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
0929          | DRM_BUS_FLAG_DE_HIGH,
0930 };
0931 
0932 static bool tc358768_is_reserved_reg(unsigned int reg)
0933 {
0934     switch (reg) {
0935     case 0x114 ... 0x13f:
0936     case 0x200:
0937     case 0x20c:
0938     case 0x400 ... 0x408:
0939     case 0x41c ... 0x42f:
0940         return true;
0941     default:
0942         return false;
0943     }
0944 }
0945 
0946 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
0947 {
0948     if (tc358768_is_reserved_reg(reg))
0949         return false;
0950 
0951     switch (reg) {
0952     case TC358768_CHIPID:
0953     case TC358768_FIFOSTATUS:
0954     case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
0955     case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
0956     case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
0957         return false;
0958     default:
0959         return true;
0960     }
0961 }
0962 
0963 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
0964 {
0965     if (tc358768_is_reserved_reg(reg))
0966         return false;
0967 
0968     switch (reg) {
0969     case TC358768_STARTCNTRL:
0970     case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
0971     case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
0972     case TC358768_DSI_START ... (TC358768_DSI_START + 2):
0973     case TC358768_DBG_DATA:
0974         return false;
0975     default:
0976         return true;
0977     }
0978 }
0979 
0980 static const struct regmap_config tc358768_regmap_config = {
0981     .name = "tc358768",
0982     .reg_bits = 16,
0983     .val_bits = 16,
0984     .max_register = TC358768_DSI_HACT,
0985     .cache_type = REGCACHE_NONE,
0986     .writeable_reg = tc358768_writeable_reg,
0987     .readable_reg = tc358768_readable_reg,
0988     .reg_format_endian = REGMAP_ENDIAN_BIG,
0989     .val_format_endian = REGMAP_ENDIAN_BIG,
0990 };
0991 
0992 static const struct i2c_device_id tc358768_i2c_ids[] = {
0993     { "tc358768", 0 },
0994     { "tc358778", 0 },
0995     { }
0996 };
0997 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
0998 
0999 static const struct of_device_id tc358768_of_ids[] = {
1000     { .compatible = "toshiba,tc358768", },
1001     { .compatible = "toshiba,tc358778", },
1002     { }
1003 };
1004 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1005 
1006 static int tc358768_get_regulators(struct tc358768_priv *priv)
1007 {
1008     int i, ret;
1009 
1010     for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1011         priv->supplies[i].supply = tc358768_supplies[i];
1012 
1013     ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1014                       priv->supplies);
1015     if (ret < 0)
1016         dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1017 
1018     return ret;
1019 }
1020 
1021 static int tc358768_i2c_probe(struct i2c_client *client,
1022                   const struct i2c_device_id *id)
1023 {
1024     struct tc358768_priv *priv;
1025     struct device *dev = &client->dev;
1026     struct device_node *np = dev->of_node;
1027     int ret;
1028 
1029     if (!np)
1030         return -ENODEV;
1031 
1032     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1033     if (!priv)
1034         return -ENOMEM;
1035 
1036     dev_set_drvdata(dev, priv);
1037     priv->dev = dev;
1038 
1039     ret = tc358768_get_regulators(priv);
1040     if (ret)
1041         return ret;
1042 
1043     priv->refclk = devm_clk_get(dev, "refclk");
1044     if (IS_ERR(priv->refclk))
1045         return PTR_ERR(priv->refclk);
1046 
1047     /*
1048      * RESX is low active, to disable tc358768 initially (keep in reset)
1049      * the gpio line must be LOW. This is the ASSERTED state of
1050      * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1051      */
1052     priv->reset_gpio  = devm_gpiod_get_optional(dev, "reset",
1053                             GPIOD_OUT_HIGH);
1054     if (IS_ERR(priv->reset_gpio))
1055         return PTR_ERR(priv->reset_gpio);
1056 
1057     priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1058     if (IS_ERR(priv->regmap)) {
1059         dev_err(dev, "Failed to init regmap\n");
1060         return PTR_ERR(priv->regmap);
1061     }
1062 
1063     priv->dsi_host.dev = dev;
1064     priv->dsi_host.ops = &tc358768_dsi_host_ops;
1065 
1066     priv->bridge.funcs = &tc358768_bridge_funcs;
1067     priv->bridge.timings = &default_tc358768_timings;
1068     priv->bridge.of_node = np;
1069 
1070     i2c_set_clientdata(client, priv);
1071 
1072     return mipi_dsi_host_register(&priv->dsi_host);
1073 }
1074 
1075 static int tc358768_i2c_remove(struct i2c_client *client)
1076 {
1077     struct tc358768_priv *priv = i2c_get_clientdata(client);
1078 
1079     mipi_dsi_host_unregister(&priv->dsi_host);
1080 
1081     return 0;
1082 }
1083 
1084 static struct i2c_driver tc358768_driver = {
1085     .driver = {
1086         .name = "tc358768",
1087         .of_match_table = tc358768_of_ids,
1088     },
1089     .id_table = tc358768_i2c_ids,
1090     .probe = tc358768_i2c_probe,
1091     .remove = tc358768_i2c_remove,
1092 };
1093 module_i2c_driver(tc358768_driver);
1094 
1095 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1096 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1097 MODULE_LICENSE("GPL v2");
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