drm/bridge/tc358764.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 Samsung Electronics Co., Ltd
0004  *
0005  * Authors:
0006  *  Andrzej Hajda <a.hajda@samsung.com>
0007  *  Maciej Purski <m.purski@samsung.com>
0008  */
0009
0010 #include <linux/delay.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/mod_devicetable.h>
0013 #include <linux/module.h>
0014 #include <linux/of_graph.h>
0015 #include <linux/regulator/consumer.h>
0016
0017 #include <video/mipi_display.h>
0018
0019 #include <drm/drm_atomic_helper.h>
0020 #include <drm/drm_mipi_dsi.h>
0021 #include <drm/drm_of.h>
0022 #include <drm/drm_print.h>
0023
0024 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
0025 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
0026
0027 /* PPI layer registers */
0028 #define PPI_STARTPPI        0x0104 /* START control bit */
0029 #define PPI_LPTXTIMECNT     0x0114 /* LPTX timing signal */
0030 #define PPI_LANEENABLE      0x0134 /* Enables each lane */
0031 #define PPI_TX_RX_TA        0x013C /* BTA timing parameters */
0032 #define PPI_D0S_CLRSIPOCOUNT    0x0164 /* Assertion timer for Lane 0 */
0033 #define PPI_D1S_CLRSIPOCOUNT    0x0168 /* Assertion timer for Lane 1 */
0034 #define PPI_D2S_CLRSIPOCOUNT    0x016C /* Assertion timer for Lane 2 */
0035 #define PPI_D3S_CLRSIPOCOUNT    0x0170 /* Assertion timer for Lane 3 */
0036 #define PPI_START_FUNCTION  1
0037
0038 /* DSI layer registers */
0039 #define DSI_STARTDSI        0x0204 /* START control bit of DSI-TX */
0040 #define DSI_LANEENABLE      0x0210 /* Enables each lane */
0041 #define DSI_RX_START        1
0042
0043 /* Video path registers */
0044 #define VP_CTRL         0x0450 /* Video Path Control */
0045 #define VP_CTRL_MSF(v)      FLD_VAL(v, 0, 0) /* Magic square in RGB666 */
0046 #define VP_CTRL_VTGEN(v)    FLD_VAL(v, 4, 4) /* Use chip clock for timing */
0047 #define VP_CTRL_EVTMODE(v)  FLD_VAL(v, 5, 5) /* Event mode */
0048 #define VP_CTRL_RGB888(v)   FLD_VAL(v, 8, 8) /* RGB888 mode */
0049 #define VP_CTRL_VSDELAY(v)  FLD_VAL(v, 31, 20) /* VSYNC delay */
0050 #define VP_CTRL_HSPOL       BIT(17) /* Polarity of HSYNC signal */
0051 #define VP_CTRL_DEPOL       BIT(18) /* Polarity of DE signal */
0052 #define VP_CTRL_VSPOL       BIT(19) /* Polarity of VSYNC signal */
0053 #define VP_HTIM1        0x0454 /* Horizontal Timing Control 1 */
0054 #define VP_HTIM1_HBP(v)     FLD_VAL(v, 24, 16)
0055 #define VP_HTIM1_HSYNC(v)   FLD_VAL(v, 8, 0)
0056 #define VP_HTIM2        0x0458 /* Horizontal Timing Control 2 */
0057 #define VP_HTIM2_HFP(v)     FLD_VAL(v, 24, 16)
0058 #define VP_HTIM2_HACT(v)    FLD_VAL(v, 10, 0)
0059 #define VP_VTIM1        0x045C /* Vertical Timing Control 1 */
0060 #define VP_VTIM1_VBP(v)     FLD_VAL(v, 23, 16)
0061 #define VP_VTIM1_VSYNC(v)   FLD_VAL(v, 7, 0)
0062 #define VP_VTIM2        0x0460 /* Vertical Timing Control 2 */
0063 #define VP_VTIM2_VFP(v)     FLD_VAL(v, 23, 16)
0064 #define VP_VTIM2_VACT(v)    FLD_VAL(v, 10, 0)
0065 #define VP_VFUEN        0x0464 /* Video Frame Timing Update Enable */
0066
0067 /* LVDS registers */
0068 #define LV_MX0003       0x0480 /* Mux input bit 0 to 3 */
0069 #define LV_MX0407       0x0484 /* Mux input bit 4 to 7 */
0070 #define LV_MX0811       0x0488 /* Mux input bit 8 to 11 */
0071 #define LV_MX1215       0x048C /* Mux input bit 12 to 15 */
0072 #define LV_MX1619       0x0490 /* Mux input bit 16 to 19 */
0073 #define LV_MX2023       0x0494 /* Mux input bit 20 to 23 */
0074 #define LV_MX2427       0x0498 /* Mux input bit 24 to 27 */
0075 #define LV_MX(b0, b1, b2, b3)   (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
0076                 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
0077
0078 /* Input bit numbers used in mux registers */
0079 enum {
0080     LVI_R0,
0081     LVI_R1,
0082     LVI_R2,
0083     LVI_R3,
0084     LVI_R4,
0085     LVI_R5,
0086     LVI_R6,
0087     LVI_R7,
0088     LVI_G0,
0089     LVI_G1,
0090     LVI_G2,
0091     LVI_G3,
0092     LVI_G4,
0093     LVI_G5,
0094     LVI_G6,
0095     LVI_G7,
0096     LVI_B0,
0097     LVI_B1,
0098     LVI_B2,
0099     LVI_B3,
0100     LVI_B4,
0101     LVI_B5,
0102     LVI_B6,
0103     LVI_B7,
0104     LVI_HS,
0105     LVI_VS,
0106     LVI_DE,
0107     LVI_L0
0108 };
0109
0110 #define LV_CFG          0x049C /* LVDS Configuration */
0111 #define LV_PHY0         0x04A0 /* LVDS PHY 0 */
0112 #define LV_PHY0_RST(v)      FLD_VAL(v, 22, 22) /* PHY reset */
0113 #define LV_PHY0_IS(v)       FLD_VAL(v, 15, 14)
0114 #define LV_PHY0_ND(v)       FLD_VAL(v, 4, 0) /* Frequency range select */
0115 #define LV_PHY0_PRBS_ON(v)  FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
0116
0117 /* System registers */
0118 #define SYS_RST         0x0504 /* System Reset */
0119 #define SYS_ID          0x0580 /* System ID */
0120
0121 #define SYS_RST_I2CS        BIT(0) /* Reset I2C-Slave controller */
0122 #define SYS_RST_I2CM        BIT(1) /* Reset I2C-Master controller */
0123 #define SYS_RST_LCD     BIT(2) /* Reset LCD controller */
0124 #define SYS_RST_BM      BIT(3) /* Reset Bus Management controller */
0125 #define SYS_RST_DSIRX       BIT(4) /* Reset DSI-RX and App controller */
0126 #define SYS_RST_REG     BIT(5) /* Reset Register module */
0127
0128 #define LPX_PERIOD      2
0129 #define TTA_SURE        3
0130 #define TTA_GET         0x20000
0131
0132 /* Lane enable PPI and DSI register bits */
0133 #define LANEENABLE_CLEN     BIT(0)
0134 #define LANEENABLE_L0EN     BIT(1)
0135 #define LANEENABLE_L1EN     BIT(2)
0136 #define LANEENABLE_L2EN     BIT(3)
0137 #define LANEENABLE_L3EN     BIT(4)
0138
0139 /* LVCFG fields */
0140 #define LV_CFG_LVEN     BIT(0)
0141 #define LV_CFG_LVDLINK      BIT(1)
0142 #define LV_CFG_CLKPOL1      BIT(2)
0143 #define LV_CFG_CLKPOL2      BIT(3)
0144
0145 static const char * const tc358764_supplies[] = {
0146     "vddc", "vddio", "vddlvds"
0147 };
0148
0149 struct tc358764 {
0150     struct device *dev;
0151     struct drm_bridge bridge;
0152     struct drm_bridge *next_bridge;
0153     struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)];
0154     struct gpio_desc *gpio_reset;
0155     int error;
0156 };
0157
0158 static int tc358764_clear_error(struct tc358764 *ctx)
0159 {
0160     int ret = ctx->error;
0161
0162     ctx->error = 0;
0163     return ret;
0164 }
0165
0166 static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
0167 {
0168     struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
0169     ssize_t ret;
0170
0171     if (ctx->error)
0172         return;
0173
0174     cpu_to_le16s(&addr);
0175     ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val));
0176     if (ret >= 0)
0177         le32_to_cpus(val);
0178
0179     dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val);
0180 }
0181
0182 static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
0183 {
0184     struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
0185     ssize_t ret;
0186     u8 data[6];
0187
0188     if (ctx->error)
0189         return;
0190
0191     data[0] = addr;
0192     data[1] = addr >> 8;
0193     data[2] = val;
0194     data[3] = val >> 8;
0195     data[4] = val >> 16;
0196     data[5] = val >> 24;
0197
0198     ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
0199     if (ret < 0)
0200         ctx->error = ret;
0201 }
0202
0203 static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge)
0204 {
0205     return container_of(bridge, struct tc358764, bridge);
0206 }
0207
0208 static int tc358764_init(struct tc358764 *ctx)
0209 {
0210     u32 v = 0;
0211
0212     tc358764_read(ctx, SYS_ID, &v);
0213     if (ctx->error)
0214         return tc358764_clear_error(ctx);
0215     dev_info(ctx->dev, "ID: %#x\n", v);
0216
0217     /* configure PPI counters */
0218     tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
0219     tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
0220     tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
0221     tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
0222     tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5);
0223     tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5);
0224
0225     /* enable four data lanes and clock lane */
0226     tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
0227                LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
0228     tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
0229                LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
0230
0231     /* start */
0232     tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
0233     tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START);
0234
0235     /* configure video path */
0236     tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) |
0237                VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL);
0238
0239     /* reset PHY */
0240     tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) |
0241                LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6));
0242     tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) |
0243                LV_PHY0_ND(6));
0244
0245     /* reset bridge */
0246     tc358764_write(ctx, SYS_RST, SYS_RST_LCD);
0247
0248     /* set bit order */
0249     tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
0250     tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
0251     tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
0252     tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
0253     tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
0254     tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
0255     tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
0256     tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 |
0257                LV_CFG_LVEN);
0258
0259     return tc358764_clear_error(ctx);
0260 }
0261
0262 static void tc358764_reset(struct tc358764 *ctx)
0263 {
0264     gpiod_set_value(ctx->gpio_reset, 1);
0265     usleep_range(1000, 2000);
0266     gpiod_set_value(ctx->gpio_reset, 0);
0267     usleep_range(1000, 2000);
0268 }
0269
0270 static void tc358764_post_disable(struct drm_bridge *bridge)
0271 {
0272     struct tc358764 *ctx = bridge_to_tc358764(bridge);
0273     int ret;
0274
0275     tc358764_reset(ctx);
0276     usleep_range(10000, 15000);
0277     ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
0278     if (ret < 0)
0279         dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
0280 }
0281
0282 static void tc358764_pre_enable(struct drm_bridge *bridge)
0283 {
0284     struct tc358764 *ctx = bridge_to_tc358764(bridge);
0285     int ret;
0286
0287     ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
0288     if (ret < 0)
0289         dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
0290     usleep_range(10000, 15000);
0291     tc358764_reset(ctx);
0292     ret = tc358764_init(ctx);
0293     if (ret < 0)
0294         dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
0295 }
0296
0297 static int tc358764_attach(struct drm_bridge *bridge,
0298                enum drm_bridge_attach_flags flags)
0299 {
0300     struct tc358764 *ctx = bridge_to_tc358764(bridge);
0301
0302     return drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags);
0303 }
0304
0305 static const struct drm_bridge_funcs tc358764_bridge_funcs = {
0306     .post_disable = tc358764_post_disable,
0307     .pre_enable = tc358764_pre_enable,
0308     .attach = tc358764_attach,
0309 };
0310
0311 static int tc358764_parse_dt(struct tc358764 *ctx)
0312 {
0313     struct device *dev = ctx->dev;
0314
0315     ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
0316     if (IS_ERR(ctx->gpio_reset)) {
0317         dev_err(dev, "no reset GPIO pin provided\n");
0318         return PTR_ERR(ctx->gpio_reset);
0319     }
0320
0321     ctx->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
0322     if (IS_ERR(ctx->next_bridge))
0323         return PTR_ERR(ctx->next_bridge);
0324
0325     return 0;
0326 }
0327
0328 static int tc358764_configure_regulators(struct tc358764 *ctx)
0329 {
0330     int i, ret;
0331
0332     for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i)
0333         ctx->supplies[i].supply = tc358764_supplies[i];
0334
0335     ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies),
0336                       ctx->supplies);
0337     if (ret < 0)
0338         dev_err(ctx->dev, "failed to get regulators: %d\n", ret);
0339
0340     return ret;
0341 }
0342
0343 static int tc358764_probe(struct mipi_dsi_device *dsi)
0344 {
0345     struct device *dev = &dsi->dev;
0346     struct tc358764 *ctx;
0347     int ret;
0348
0349     ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
0350     if (!ctx)
0351         return -ENOMEM;
0352
0353     mipi_dsi_set_drvdata(dsi, ctx);
0354
0355     ctx->dev = dev;
0356
0357     dsi->lanes = 4;
0358     dsi->format = MIPI_DSI_FMT_RGB888;
0359     dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST
0360         | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM;
0361
0362     ret = tc358764_parse_dt(ctx);
0363     if (ret < 0)
0364         return ret;
0365
0366     ret = tc358764_configure_regulators(ctx);
0367     if (ret < 0)
0368         return ret;
0369
0370     ctx->bridge.funcs = &tc358764_bridge_funcs;
0371     ctx->bridge.of_node = dev->of_node;
0372
0373     drm_bridge_add(&ctx->bridge);
0374
0375     ret = mipi_dsi_attach(dsi);
0376     if (ret < 0) {
0377         drm_bridge_remove(&ctx->bridge);
0378         dev_err(dev, "failed to attach dsi\n");
0379     }
0380
0381     return ret;
0382 }
0383
0384 static int tc358764_remove(struct mipi_dsi_device *dsi)
0385 {
0386     struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi);
0387
0388     mipi_dsi_detach(dsi);
0389     drm_bridge_remove(&ctx->bridge);
0390
0391     return 0;
0392 }
0393
0394 static const struct of_device_id tc358764_of_match[] = {
0395     { .compatible = "toshiba,tc358764" },
0396     { }
0397 };
0398 MODULE_DEVICE_TABLE(of, tc358764_of_match);
0399
0400 static struct mipi_dsi_driver tc358764_driver = {
0401     .probe = tc358764_probe,
0402     .remove = tc358764_remove,
0403     .driver = {
0404         .name = "tc358764",
0405         .owner = THIS_MODULE,
0406         .of_match_table = tc358764_of_match,
0407     },
0408 };
0409 module_mipi_dsi_driver(tc358764_driver);
0410
0411 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
0412 MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>");
0413 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge");
0414 MODULE_LICENSE("GPL v2");