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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Silicon Image SiI8620 HDMI/MHL bridge driver
0004  *
0005  * Copyright (C) 2015, Samsung Electronics Co., Ltd.
0006  * Andrzej Hajda <a.hajda@samsung.com>
0007  */
0008 
0009 #include <asm/unaligned.h>
0010 
0011 #include <drm/bridge/mhl.h>
0012 #include <drm/drm_bridge.h>
0013 #include <drm/drm_crtc.h>
0014 #include <drm/drm_edid.h>
0015 #include <drm/drm_encoder.h>
0016 
0017 #include <linux/clk.h>
0018 #include <linux/delay.h>
0019 #include <linux/extcon.h>
0020 #include <linux/gpio/consumer.h>
0021 #include <linux/i2c.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/irq.h>
0024 #include <linux/kernel.h>
0025 #include <linux/list.h>
0026 #include <linux/module.h>
0027 #include <linux/mutex.h>
0028 #include <linux/of_graph.h>
0029 #include <linux/regulator/consumer.h>
0030 #include <linux/slab.h>
0031 
0032 #include <media/rc-core.h>
0033 
0034 #include "sil-sii8620.h"
0035 
0036 #define SII8620_BURST_BUF_LEN 288
0037 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
0038 
0039 #define MHL1_MAX_PCLK 75000
0040 #define MHL1_MAX_PCLK_PP_MODE 150000
0041 #define MHL3_MAX_PCLK 200000
0042 #define MHL3_MAX_PCLK_PP_MODE 300000
0043 
0044 enum sii8620_mode {
0045     CM_DISCONNECTED,
0046     CM_DISCOVERY,
0047     CM_MHL1,
0048     CM_MHL3,
0049     CM_ECBUS_S
0050 };
0051 
0052 enum sii8620_sink_type {
0053     SINK_NONE,
0054     SINK_HDMI,
0055     SINK_DVI
0056 };
0057 
0058 enum sii8620_mt_state {
0059     MT_STATE_READY,
0060     MT_STATE_BUSY,
0061     MT_STATE_DONE
0062 };
0063 
0064 struct sii8620 {
0065     struct drm_bridge bridge;
0066     struct device *dev;
0067     struct rc_dev *rc_dev;
0068     struct clk *clk_xtal;
0069     struct gpio_desc *gpio_reset;
0070     struct gpio_desc *gpio_int;
0071     struct regulator_bulk_data supplies[2];
0072     struct mutex lock; /* context lock, protects fields below */
0073     int error;
0074     unsigned int use_packed_pixel:1;
0075     enum sii8620_mode mode;
0076     enum sii8620_sink_type sink_type;
0077     u8 cbus_status;
0078     u8 stat[MHL_DST_SIZE];
0079     u8 xstat[MHL_XDS_SIZE];
0080     u8 devcap[MHL_DCAP_SIZE];
0081     u8 xdevcap[MHL_XDC_SIZE];
0082     bool feature_complete;
0083     bool devcap_read;
0084     bool sink_detected;
0085     struct edid *edid;
0086     unsigned int gen2_write_burst:1;
0087     enum sii8620_mt_state mt_state;
0088     struct extcon_dev *extcon;
0089     struct notifier_block extcon_nb;
0090     struct work_struct extcon_wq;
0091     int cable_state;
0092     struct list_head mt_queue;
0093     struct {
0094         int r_size;
0095         int r_count;
0096         int rx_ack;
0097         int rx_count;
0098         u8 rx_buf[32];
0099         int tx_count;
0100         u8 tx_buf[32];
0101     } burst;
0102 };
0103 
0104 struct sii8620_mt_msg;
0105 
0106 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx,
0107                   struct sii8620_mt_msg *msg);
0108 
0109 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret);
0110 
0111 struct sii8620_mt_msg {
0112     struct list_head node;
0113     u8 reg[4];
0114     u8 ret;
0115     sii8620_mt_msg_cb send;
0116     sii8620_mt_msg_cb recv;
0117     sii8620_cb continuation;
0118 };
0119 
0120 static const u8 sii8620_i2c_page[] = {
0121     0x39, /* Main System */
0122     0x3d, /* TDM and HSIC */
0123     0x49, /* TMDS Receiver, MHL EDID */
0124     0x4d, /* eMSC, HDCP, HSIC */
0125     0x5d, /* MHL Spec */
0126     0x64, /* MHL CBUS */
0127     0x59, /* Hardware TPI (Transmitter Programming Interface) */
0128     0x61, /* eCBUS-S, eCBUS-D */
0129 };
0130 
0131 static void sii8620_fetch_edid(struct sii8620 *ctx);
0132 static void sii8620_set_upstream_edid(struct sii8620 *ctx);
0133 static void sii8620_enable_hpd(struct sii8620 *ctx);
0134 static void sii8620_mhl_disconnected(struct sii8620 *ctx);
0135 static void sii8620_disconnect(struct sii8620 *ctx);
0136 
0137 static int sii8620_clear_error(struct sii8620 *ctx)
0138 {
0139     int ret = ctx->error;
0140 
0141     ctx->error = 0;
0142     return ret;
0143 }
0144 
0145 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len)
0146 {
0147     struct device *dev = ctx->dev;
0148     struct i2c_client *client = to_i2c_client(dev);
0149     u8 data = addr;
0150     struct i2c_msg msg[] = {
0151         {
0152             .addr = sii8620_i2c_page[addr >> 8],
0153             .flags = client->flags,
0154             .len = 1,
0155             .buf = &data
0156         },
0157         {
0158             .addr = sii8620_i2c_page[addr >> 8],
0159             .flags = client->flags | I2C_M_RD,
0160             .len = len,
0161             .buf = buf
0162         },
0163     };
0164     int ret;
0165 
0166     if (ctx->error)
0167         return;
0168 
0169     ret = i2c_transfer(client->adapter, msg, 2);
0170     dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret);
0171 
0172     if (ret != 2) {
0173         dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n",
0174             addr, len, ret);
0175         ctx->error = ret < 0 ? ret : -EIO;
0176     }
0177 }
0178 
0179 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr)
0180 {
0181     u8 ret = 0;
0182 
0183     sii8620_read_buf(ctx, addr, &ret, 1);
0184     return ret;
0185 }
0186 
0187 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf,
0188                   int len)
0189 {
0190     struct device *dev = ctx->dev;
0191     struct i2c_client *client = to_i2c_client(dev);
0192     u8 data[2];
0193     struct i2c_msg msg = {
0194         .addr = sii8620_i2c_page[addr >> 8],
0195         .flags = client->flags,
0196         .len = len + 1,
0197     };
0198     int ret;
0199 
0200     if (ctx->error)
0201         return;
0202 
0203     if (len > 1) {
0204         msg.buf = kmalloc(len + 1, GFP_KERNEL);
0205         if (!msg.buf) {
0206             ctx->error = -ENOMEM;
0207             return;
0208         }
0209         memcpy(msg.buf + 1, buf, len);
0210     } else {
0211         msg.buf = data;
0212         msg.buf[1] = *buf;
0213     }
0214 
0215     msg.buf[0] = addr;
0216 
0217     ret = i2c_transfer(client->adapter, &msg, 1);
0218     dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret);
0219 
0220     if (ret != 1) {
0221         dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n",
0222             addr, len, buf, ret);
0223         ctx->error = ret ?: -EIO;
0224     }
0225 
0226     if (len > 1)
0227         kfree(msg.buf);
0228 }
0229 
0230 #define sii8620_write(ctx, addr, arr...) \
0231 ({\
0232     u8 d[] = { arr }; \
0233     sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \
0234 })
0235 
0236 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len)
0237 {
0238     int i;
0239 
0240     for (i = 0; i < len; i += 2)
0241         sii8620_write(ctx, seq[i], seq[i + 1]);
0242 }
0243 
0244 #define sii8620_write_seq(ctx, seq...) \
0245 ({\
0246     const u16 d[] = { seq }; \
0247     __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
0248 })
0249 
0250 #define sii8620_write_seq_static(ctx, seq...) \
0251 ({\
0252     static const u16 d[] = { seq }; \
0253     __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
0254 })
0255 
0256 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
0257 {
0258     val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask);
0259     sii8620_write(ctx, addr, val);
0260 }
0261 
0262 static inline bool sii8620_is_mhl3(struct sii8620 *ctx)
0263 {
0264     return ctx->mode >= CM_MHL3;
0265 }
0266 
0267 static void sii8620_mt_cleanup(struct sii8620 *ctx)
0268 {
0269     struct sii8620_mt_msg *msg, *n;
0270 
0271     list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) {
0272         list_del(&msg->node);
0273         kfree(msg);
0274     }
0275     ctx->mt_state = MT_STATE_READY;
0276 }
0277 
0278 static void sii8620_mt_work(struct sii8620 *ctx)
0279 {
0280     struct sii8620_mt_msg *msg;
0281 
0282     if (ctx->error)
0283         return;
0284     if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue))
0285         return;
0286 
0287     if (ctx->mt_state == MT_STATE_DONE) {
0288         ctx->mt_state = MT_STATE_READY;
0289         msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg,
0290                        node);
0291         list_del(&msg->node);
0292         if (msg->recv)
0293             msg->recv(ctx, msg);
0294         if (msg->continuation)
0295             msg->continuation(ctx, msg->ret);
0296         kfree(msg);
0297     }
0298 
0299     if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue))
0300         return;
0301 
0302     ctx->mt_state = MT_STATE_BUSY;
0303     msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
0304     if (msg->send)
0305         msg->send(ctx, msg);
0306 }
0307 
0308 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
0309 {
0310     u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN;
0311 
0312     if (ctx->gen2_write_burst)
0313         return;
0314 
0315     if (ctx->mode >= CM_MHL1)
0316         ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN;
0317 
0318     sii8620_write_seq(ctx,
0319         REG_MDT_RCV_TIMEOUT, 100,
0320         REG_MDT_RCV_CTRL, ctrl
0321     );
0322     ctx->gen2_write_burst = 1;
0323 }
0324 
0325 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
0326 {
0327     if (!ctx->gen2_write_burst)
0328         return;
0329 
0330     sii8620_write_seq_static(ctx,
0331         REG_MDT_XMIT_CTRL, 0,
0332         REG_MDT_RCV_CTRL, 0
0333     );
0334     ctx->gen2_write_burst = 0;
0335 }
0336 
0337 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx)
0338 {
0339     sii8620_write_seq_static(ctx,
0340         REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT
0341             | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR
0342             | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
0343             | BIT_MDT_XMIT_SM_ERROR,
0344         REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY
0345             | BIT_MDT_IDLE_AFTER_HAWB_DISABLE
0346             | BIT_MDT_RFIFO_DATA_RDY
0347     );
0348     sii8620_enable_gen2_write_burst(ctx);
0349 }
0350 
0351 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
0352                     struct sii8620_mt_msg *msg)
0353 {
0354     if (msg->reg[0] == MHL_SET_INT &&
0355         msg->reg[1] == MHL_INT_REG(RCHANGE) &&
0356         msg->reg[2] == MHL_INT_RC_FEAT_REQ)
0357         sii8620_enable_gen2_write_burst(ctx);
0358     else
0359         sii8620_disable_gen2_write_burst(ctx);
0360 
0361     switch (msg->reg[0]) {
0362     case MHL_WRITE_STAT:
0363     case MHL_SET_INT:
0364         sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2);
0365         sii8620_write(ctx, REG_MSC_COMMAND_START,
0366                   BIT_MSC_COMMAND_START_WRITE_STAT);
0367         break;
0368     case MHL_MSC_MSG:
0369         sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3);
0370         sii8620_write(ctx, REG_MSC_COMMAND_START,
0371                   BIT_MSC_COMMAND_START_MSC_MSG);
0372         break;
0373     case MHL_READ_DEVCAP_REG:
0374     case MHL_READ_XDEVCAP_REG:
0375         sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]);
0376         sii8620_write(ctx, REG_MSC_COMMAND_START,
0377                   BIT_MSC_COMMAND_START_READ_DEVCAP);
0378         break;
0379     default:
0380         dev_err(ctx->dev, "%s: command %#x not supported\n", __func__,
0381             msg->reg[0]);
0382     }
0383 }
0384 
0385 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
0386 {
0387     struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
0388 
0389     if (!msg)
0390         ctx->error = -ENOMEM;
0391     else
0392         list_add_tail(&msg->node, &ctx->mt_queue);
0393 
0394     return msg;
0395 }
0396 
0397 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont)
0398 {
0399     struct sii8620_mt_msg *msg;
0400 
0401     if (ctx->error)
0402         return;
0403 
0404     if (list_empty(&ctx->mt_queue)) {
0405         ctx->error = -EINVAL;
0406         return;
0407     }
0408     msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
0409     msg->continuation = cont;
0410 }
0411 
0412 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2)
0413 {
0414     struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
0415 
0416     if (!msg)
0417         return;
0418 
0419     msg->reg[0] = cmd;
0420     msg->reg[1] = arg1;
0421     msg->reg[2] = arg2;
0422     msg->send = sii8620_mt_msc_cmd_send;
0423 }
0424 
0425 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
0426 {
0427     sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val);
0428 }
0429 
0430 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
0431 {
0432     sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask);
0433 }
0434 
0435 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
0436 {
0437     sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data);
0438 }
0439 
0440 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
0441 {
0442     sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
0443 }
0444 
0445 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code)
0446 {
0447     sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code);
0448 }
0449 
0450 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code)
0451 {
0452     sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code);
0453 }
0454 
0455 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
0456                     struct sii8620_mt_msg *msg)
0457 {
0458     u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
0459             | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
0460             | BIT_EDID_CTRL_EDID_MODE_EN;
0461 
0462     if (msg->reg[0] == MHL_READ_XDEVCAP)
0463         ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
0464 
0465     sii8620_write_seq(ctx,
0466         REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE,
0467         REG_EDID_CTRL, ctrl,
0468         REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START
0469     );
0470 }
0471 
0472 /* copy src to dst and set changed bits in src */
0473 static void sii8620_update_array(u8 *dst, u8 *src, int count)
0474 {
0475     while (--count >= 0) {
0476         *src ^= *dst;
0477         *dst++ ^= *src++;
0478     }
0479 }
0480 
0481 static void sii8620_identify_sink(struct sii8620 *ctx)
0482 {
0483     static const char * const sink_str[] = {
0484         [SINK_NONE] = "NONE",
0485         [SINK_HDMI] = "HDMI",
0486         [SINK_DVI] = "DVI"
0487     };
0488 
0489     char sink_name[20];
0490     struct device *dev = ctx->dev;
0491 
0492     if (!ctx->sink_detected || !ctx->devcap_read)
0493         return;
0494 
0495     sii8620_fetch_edid(ctx);
0496     if (!ctx->edid) {
0497         dev_err(ctx->dev, "Cannot fetch EDID\n");
0498         sii8620_mhl_disconnected(ctx);
0499         return;
0500     }
0501     sii8620_set_upstream_edid(ctx);
0502 
0503     if (drm_detect_hdmi_monitor(ctx->edid))
0504         ctx->sink_type = SINK_HDMI;
0505     else
0506         ctx->sink_type = SINK_DVI;
0507 
0508     drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name));
0509 
0510     dev_info(dev, "detected sink(type: %s): %s\n",
0511          sink_str[ctx->sink_type], sink_name);
0512 }
0513 
0514 static void sii8620_mr_devcap(struct sii8620 *ctx)
0515 {
0516     u8 dcap[MHL_DCAP_SIZE];
0517     struct device *dev = ctx->dev;
0518 
0519     sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
0520     if (ctx->error < 0)
0521         return;
0522 
0523     dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
0524          dcap[MHL_DCAP_MHL_VERSION] / 16,
0525          dcap[MHL_DCAP_MHL_VERSION] % 16,
0526          dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
0527          dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
0528     sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
0529     ctx->devcap_read = true;
0530     sii8620_identify_sink(ctx);
0531 }
0532 
0533 static void sii8620_mr_xdevcap(struct sii8620 *ctx)
0534 {
0535     sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
0536              MHL_XDC_SIZE);
0537 }
0538 
0539 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
0540                     struct sii8620_mt_msg *msg)
0541 {
0542     u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
0543         | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
0544         | BIT_EDID_CTRL_EDID_MODE_EN;
0545 
0546     if (msg->reg[0] == MHL_READ_XDEVCAP)
0547         ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
0548 
0549     sii8620_write_seq(ctx,
0550         REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE
0551             | BIT_INTR9_EDID_ERROR,
0552         REG_EDID_CTRL, ctrl,
0553         REG_EDID_FIFO_ADDR, 0
0554     );
0555 
0556     if (msg->reg[0] == MHL_READ_XDEVCAP)
0557         sii8620_mr_xdevcap(ctx);
0558     else
0559         sii8620_mr_devcap(ctx);
0560 }
0561 
0562 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap)
0563 {
0564     struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
0565 
0566     if (!msg)
0567         return;
0568 
0569     msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP;
0570     msg->send = sii8620_mt_read_devcap_send;
0571     msg->recv = sii8620_mt_read_devcap_recv;
0572 }
0573 
0574 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx,
0575         struct sii8620_mt_msg *msg)
0576 {
0577     u8 reg = msg->reg[1] & 0x7f;
0578 
0579     if (msg->reg[1] & 0x80)
0580         ctx->xdevcap[reg] = msg->ret;
0581     else
0582         ctx->devcap[reg] = msg->ret;
0583 }
0584 
0585 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg)
0586 {
0587     struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
0588 
0589     if (!msg)
0590         return;
0591 
0592     msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG;
0593     msg->reg[1] = reg;
0594     msg->send = sii8620_mt_msc_cmd_send;
0595     msg->recv = sii8620_mt_read_devcap_reg_recv;
0596 }
0597 
0598 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg)
0599 {
0600     sii8620_mt_read_devcap_reg(ctx, reg | 0x80);
0601 }
0602 
0603 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len)
0604 {
0605     u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count];
0606     int size = len + 2;
0607 
0608     if (ctx->burst.tx_count + size >= ARRAY_SIZE(ctx->burst.tx_buf)) {
0609         dev_err(ctx->dev, "TX-BLK buffer exhausted\n");
0610         ctx->error = -EINVAL;
0611         return NULL;
0612     }
0613 
0614     ctx->burst.tx_count += size;
0615     buf[1] = len;
0616 
0617     return buf + 2;
0618 }
0619 
0620 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len)
0621 {
0622     u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count];
0623     int size = len + 1;
0624 
0625     if (ctx->burst.rx_count + size >= ARRAY_SIZE(ctx->burst.rx_buf)) {
0626         dev_err(ctx->dev, "RX-BLK buffer exhausted\n");
0627         ctx->error = -EINVAL;
0628         return NULL;
0629     }
0630 
0631     ctx->burst.rx_count += size;
0632     buf[0] = len;
0633 
0634     return buf + 1;
0635 }
0636 
0637 static void sii8620_burst_send(struct sii8620 *ctx)
0638 {
0639     int tx_left = ctx->burst.tx_count;
0640     u8 *d = ctx->burst.tx_buf;
0641 
0642     while (tx_left > 0) {
0643         int len = d[1] + 2;
0644 
0645         if (ctx->burst.r_count + len > ctx->burst.r_size)
0646             break;
0647         d[0] = min(ctx->burst.rx_ack, 255);
0648         ctx->burst.rx_ack -= d[0];
0649         sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len);
0650         ctx->burst.r_count += len;
0651         tx_left -= len;
0652         d += len;
0653     }
0654 
0655     ctx->burst.tx_count = tx_left;
0656 
0657     while (ctx->burst.rx_ack > 0) {
0658         u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 };
0659 
0660         if (ctx->burst.r_count + 2 > ctx->burst.r_size)
0661             break;
0662         ctx->burst.rx_ack -= b[0];
0663         sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2);
0664         ctx->burst.r_count += 2;
0665     }
0666 }
0667 
0668 static void sii8620_burst_receive(struct sii8620 *ctx)
0669 {
0670     u8 buf[3], *d;
0671     int count;
0672 
0673     sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2);
0674     count = get_unaligned_le16(buf);
0675     while (count > 0) {
0676         int len = min(count, 3);
0677 
0678         sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len);
0679         count -= len;
0680         ctx->burst.rx_ack += len - 1;
0681         ctx->burst.r_count -= buf[1];
0682         if (ctx->burst.r_count < 0)
0683             ctx->burst.r_count = 0;
0684 
0685         if (len < 3 || !buf[2])
0686             continue;
0687 
0688         len = buf[2];
0689         d = sii8620_burst_get_rx_buf(ctx, len);
0690         if (!d)
0691             continue;
0692         sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len);
0693         count -= len;
0694         ctx->burst.rx_ack += len;
0695     }
0696 }
0697 
0698 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size)
0699 {
0700     struct mhl_burst_blk_rcv_buffer_info *d =
0701         sii8620_burst_get_tx_buf(ctx, sizeof(*d));
0702     if (!d)
0703         return;
0704 
0705     d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO);
0706     d->size = cpu_to_le16(size);
0707 }
0708 
0709 static u8 sii8620_checksum(void *ptr, int size)
0710 {
0711     u8 *d = ptr, sum = 0;
0712 
0713     while (size--)
0714         sum += *d++;
0715 
0716     return sum;
0717 }
0718 
0719 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h,
0720     enum mhl_burst_id id)
0721 {
0722     h->id = cpu_to_be16(id);
0723     h->total_entries = 1;
0724     h->sequence_index = 1;
0725 }
0726 
0727 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt)
0728 {
0729     struct mhl_burst_bits_per_pixel_fmt *d;
0730     const int size = sizeof(*d) + sizeof(d->desc[0]);
0731 
0732     d = sii8620_burst_get_tx_buf(ctx, size);
0733     if (!d)
0734         return;
0735 
0736     sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT);
0737     d->num_entries = 1;
0738     d->desc[0].stream_id = 0;
0739     d->desc[0].pixel_format = fmt;
0740     d->hdr.checksum -= sii8620_checksum(d, size);
0741 }
0742 
0743 static void sii8620_burst_rx_all(struct sii8620 *ctx)
0744 {
0745     u8 *d = ctx->burst.rx_buf;
0746     int count = ctx->burst.rx_count;
0747 
0748     while (count-- > 0) {
0749         int len = *d++;
0750         int id = get_unaligned_be16(&d[0]);
0751 
0752         switch (id) {
0753         case MHL_BURST_ID_BLK_RCV_BUFFER_INFO:
0754             ctx->burst.r_size = get_unaligned_le16(&d[2]);
0755             break;
0756         default:
0757             break;
0758         }
0759         count -= len;
0760         d += len;
0761     }
0762     ctx->burst.rx_count = 0;
0763 }
0764 
0765 static void sii8620_fetch_edid(struct sii8620 *ctx)
0766 {
0767     u8 lm_ddc, ddc_cmd, int3, cbus;
0768     unsigned long timeout;
0769     int fetched, i;
0770     int edid_len = EDID_LENGTH;
0771     u8 *edid;
0772 
0773     sii8620_readb(ctx, REG_CBUS_STATUS);
0774     lm_ddc = sii8620_readb(ctx, REG_LM_DDC);
0775     ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD);
0776 
0777     sii8620_write_seq(ctx,
0778         REG_INTR9_MASK, 0,
0779         REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
0780         REG_HDCP2X_POLL_CS, 0x71,
0781         REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX,
0782         REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED,
0783     );
0784 
0785     for (i = 0; i < 256; ++i) {
0786         u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS);
0787 
0788         if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG))
0789             break;
0790         sii8620_write(ctx, REG_DDC_STATUS,
0791                   BIT_DDC_STATUS_DDC_FIFO_EMPTY);
0792     }
0793 
0794     sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1);
0795 
0796     edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
0797     if (!edid) {
0798         ctx->error = -ENOMEM;
0799         return;
0800     }
0801 
0802 #define FETCH_SIZE 16
0803     for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) {
0804         sii8620_readb(ctx, REG_DDC_STATUS);
0805         sii8620_write_seq(ctx,
0806             REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT,
0807             REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO,
0808             REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY
0809         );
0810         sii8620_write_seq(ctx,
0811             REG_DDC_SEGM, fetched >> 8,
0812             REG_DDC_OFFSET, fetched & 0xff,
0813             REG_DDC_DIN_CNT1, FETCH_SIZE,
0814             REG_DDC_DIN_CNT2, 0,
0815             REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
0816         );
0817 
0818         int3 = 0;
0819         timeout = jiffies + msecs_to_jiffies(200);
0820         for (;;) {
0821             cbus = sii8620_readb(ctx, REG_CBUS_STATUS);
0822             if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) {
0823                 kfree(edid);
0824                 edid = NULL;
0825                 goto end;
0826             }
0827             if (int3 & BIT_DDC_CMD_DONE) {
0828                 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT)
0829                     >= FETCH_SIZE)
0830                     break;
0831             } else {
0832                 int3 = sii8620_readb(ctx, REG_INTR3);
0833             }
0834             if (time_is_before_jiffies(timeout)) {
0835                 ctx->error = -ETIMEDOUT;
0836                 dev_err(ctx->dev, "timeout during EDID read\n");
0837                 kfree(edid);
0838                 edid = NULL;
0839                 goto end;
0840             }
0841             usleep_range(10, 20);
0842         }
0843 
0844         sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE);
0845         if (fetched + FETCH_SIZE == EDID_LENGTH) {
0846             u8 ext = ((struct edid *)edid)->extensions;
0847 
0848             if (ext) {
0849                 u8 *new_edid;
0850 
0851                 edid_len += ext * EDID_LENGTH;
0852                 new_edid = krealloc(edid, edid_len, GFP_KERNEL);
0853                 if (!new_edid) {
0854                     kfree(edid);
0855                     ctx->error = -ENOMEM;
0856                     return;
0857                 }
0858                 edid = new_edid;
0859             }
0860         }
0861     }
0862 
0863     sii8620_write_seq(ctx,
0864         REG_INTR3_MASK, BIT_DDC_CMD_DONE,
0865         REG_LM_DDC, lm_ddc
0866     );
0867 
0868 end:
0869     kfree(ctx->edid);
0870     ctx->edid = (struct edid *)edid;
0871 }
0872 
0873 static void sii8620_set_upstream_edid(struct sii8620 *ctx)
0874 {
0875     sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N
0876             | BIT_DPD_PD_MHL_CLK_N, 0xff);
0877 
0878     sii8620_write_seq_static(ctx,
0879         REG_RX_HDMI_CTRL3, 0x00,
0880         REG_PKT_FILTER_0, 0xFF,
0881         REG_PKT_FILTER_1, 0xFF,
0882         REG_ALICE0_BW_I2C, 0x06
0883     );
0884 
0885     sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER,
0886             BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff);
0887 
0888     sii8620_write_seq_static(ctx,
0889         REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
0890             | BIT_EDID_CTRL_EDID_MODE_EN,
0891         REG_EDID_FIFO_ADDR, 0,
0892     );
0893 
0894     sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid,
0895               (ctx->edid->extensions + 1) * EDID_LENGTH);
0896 
0897     sii8620_write_seq_static(ctx,
0898         REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID
0899             | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
0900             | BIT_EDID_CTRL_EDID_MODE_EN,
0901         REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE,
0902         REG_INTR9_MASK, 0
0903     );
0904 }
0905 
0906 static void sii8620_xtal_set_rate(struct sii8620 *ctx)
0907 {
0908     static const struct {
0909         unsigned int rate;
0910         u8 div;
0911         u8 tp1;
0912     } rates[] = {
0913         { 19200, 0x04, 0x53 },
0914         { 20000, 0x04, 0x62 },
0915         { 24000, 0x05, 0x75 },
0916         { 30000, 0x06, 0x92 },
0917         { 38400, 0x0c, 0xbc },
0918     };
0919     unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000;
0920     int i;
0921 
0922     for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i)
0923         if (rate <= rates[i].rate)
0924             break;
0925 
0926     if (rate != rates[i].rate)
0927         dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n",
0928             rate, rates[i].rate);
0929 
0930     sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div);
0931     sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1);
0932 }
0933 
0934 static int sii8620_hw_on(struct sii8620 *ctx)
0935 {
0936     int ret;
0937 
0938     ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
0939     if (ret)
0940         return ret;
0941 
0942     usleep_range(10000, 20000);
0943     ret = clk_prepare_enable(ctx->clk_xtal);
0944     if (ret)
0945         return ret;
0946 
0947     msleep(100);
0948     gpiod_set_value(ctx->gpio_reset, 0);
0949     msleep(100);
0950 
0951     return 0;
0952 }
0953 
0954 static int sii8620_hw_off(struct sii8620 *ctx)
0955 {
0956     clk_disable_unprepare(ctx->clk_xtal);
0957     gpiod_set_value(ctx->gpio_reset, 1);
0958     return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
0959 }
0960 
0961 static void sii8620_cbus_reset(struct sii8620 *ctx)
0962 {
0963     sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST
0964               | BIT_PWD_SRST_CBUS_RST_SW_EN);
0965     usleep_range(10000, 20000);
0966     sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN);
0967 }
0968 
0969 static void sii8620_set_auto_zone(struct sii8620 *ctx)
0970 {
0971     if (ctx->mode != CM_MHL1) {
0972         sii8620_write_seq_static(ctx,
0973             REG_TX_ZONE_CTL1, 0x0,
0974             REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
0975                 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
0976                 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
0977         );
0978     } else {
0979         sii8620_write_seq_static(ctx,
0980             REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE,
0981             REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
0982                 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
0983         );
0984     }
0985 }
0986 
0987 static void sii8620_stop_video(struct sii8620 *ctx)
0988 {
0989     u8 val;
0990 
0991     sii8620_write_seq_static(ctx,
0992         REG_TPI_INTR_EN, 0,
0993         REG_HDCP2X_INTR0_MASK, 0,
0994         REG_TPI_COPP_DATA2, 0,
0995         REG_TPI_INTR_ST0, ~0,
0996     );
0997 
0998     switch (ctx->sink_type) {
0999     case SINK_DVI:
1000         val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1001             | BIT_TPI_SC_TPI_AV_MUTE;
1002         break;
1003     case SINK_HDMI:
1004     default:
1005         val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1006             | BIT_TPI_SC_TPI_AV_MUTE
1007             | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI;
1008         break;
1009     }
1010 
1011     sii8620_write(ctx, REG_TPI_SC, val);
1012 }
1013 
1014 static void sii8620_set_format(struct sii8620 *ctx)
1015 {
1016     u8 out_fmt;
1017 
1018     if (sii8620_is_mhl3(ctx)) {
1019         sii8620_setbits(ctx, REG_M3_P0CTRL,
1020                 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED,
1021                 ctx->use_packed_pixel ? ~0 : 0);
1022     } else {
1023         if (ctx->use_packed_pixel) {
1024             sii8620_write_seq_static(ctx,
1025                 REG_VID_MODE, BIT_VID_MODE_M1080P,
1026                 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1,
1027                 REG_MHLTX_CTL6, 0x60
1028             );
1029         } else {
1030             sii8620_write_seq_static(ctx,
1031                 REG_VID_MODE, 0,
1032                 REG_MHL_TOP_CTL, 1,
1033                 REG_MHLTX_CTL6, 0xa0
1034             );
1035         }
1036     }
1037 
1038     if (ctx->use_packed_pixel)
1039         out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL);
1040     else
1041         out_fmt = VAL_TPI_FORMAT(RGB, FULL);
1042 
1043     sii8620_write_seq(ctx,
1044         REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL),
1045         REG_TPI_OUTPUT, out_fmt,
1046     );
1047 }
1048 
1049 static int mhl3_infoframe_init(struct mhl3_infoframe *frame)
1050 {
1051     memset(frame, 0, sizeof(*frame));
1052 
1053     frame->version = 3;
1054     frame->hev_format = -1;
1055     return 0;
1056 }
1057 
1058 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame,
1059          void *buffer, size_t size)
1060 {
1061     const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE;
1062     u8 *ptr = buffer;
1063 
1064     if (size < frm_len)
1065         return -ENOSPC;
1066 
1067     memset(buffer, 0, size);
1068     ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR;
1069     ptr[1] = frame->version;
1070     ptr[2] = MHL3_INFOFRAME_SIZE;
1071     ptr[4] = MHL3_IEEE_OUI & 0xff;
1072     ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff;
1073     ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff;
1074     ptr[7] = frame->video_format & 0x3;
1075     ptr[7] |= (frame->format_type & 0x7) << 2;
1076     ptr[7] |= frame->sep_audio ? BIT(5) : 0;
1077     if (frame->hev_format >= 0) {
1078         ptr[9] = 1;
1079         ptr[10] = (frame->hev_format >> 8) & 0xff;
1080         ptr[11] = frame->hev_format & 0xff;
1081     }
1082     if (frame->av_delay) {
1083         bool sign = frame->av_delay < 0;
1084         int delay = sign ? -frame->av_delay : frame->av_delay;
1085 
1086         ptr[12] = (delay >> 16) & 0xf;
1087         if (sign)
1088             ptr[12] |= BIT(4);
1089         ptr[13] = (delay >> 8) & 0xff;
1090         ptr[14] = delay & 0xff;
1091     }
1092     ptr[3] -= sii8620_checksum(buffer, frm_len);
1093     return frm_len;
1094 }
1095 
1096 static void sii8620_set_infoframes(struct sii8620 *ctx,
1097                    struct drm_display_mode *mode)
1098 {
1099     struct mhl3_infoframe mhl_frm;
1100     union hdmi_infoframe frm;
1101     u8 buf[31];
1102     int ret;
1103 
1104     ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi,
1105                                NULL, mode);
1106     if (ctx->use_packed_pixel)
1107         frm.avi.colorspace = HDMI_COLORSPACE_YUV422;
1108 
1109     if (!ret)
1110         ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf));
1111     if (ret > 0)
1112         sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3);
1113 
1114     if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) {
1115         sii8620_write(ctx, REG_TPI_SC,
1116             BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI);
1117         sii8620_write(ctx, REG_PKT_FILTER_0,
1118             BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1119             BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1120             BIT_PKT_FILTER_0_DROP_GCP_PKT,
1121             BIT_PKT_FILTER_1_DROP_GEN_PKT);
1122         return;
1123     }
1124 
1125     sii8620_write(ctx, REG_PKT_FILTER_0,
1126         BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1127         BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1128         BIT_PKT_FILTER_0_DROP_AVI_PKT |
1129         BIT_PKT_FILTER_0_DROP_GCP_PKT,
1130         BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS |
1131         BIT_PKT_FILTER_1_DROP_GEN_PKT |
1132         BIT_PKT_FILTER_1_DROP_VSIF_PKT);
1133 
1134     sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN
1135         | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI);
1136     ret = mhl3_infoframe_init(&mhl_frm);
1137     if (!ret)
1138         ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf));
1139     sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret);
1140 }
1141 
1142 static void sii8620_start_video(struct sii8620 *ctx)
1143 {
1144     struct drm_display_mode *mode =
1145         &ctx->bridge.encoder->crtc->state->adjusted_mode;
1146 
1147     if (!sii8620_is_mhl3(ctx))
1148         sii8620_stop_video(ctx);
1149 
1150     if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) {
1151         sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1152                   VAL_RX_HDMI_CTRL2_DEFVAL);
1153         sii8620_write(ctx, REG_TPI_SC, 0);
1154         return;
1155     }
1156 
1157     sii8620_write_seq_static(ctx,
1158         REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
1159             | BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
1160         REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE
1161             | BIT_VID_OVRRD_M1080P_OVRRD);
1162     sii8620_set_format(ctx);
1163 
1164     if (!sii8620_is_mhl3(ctx)) {
1165         u8 link_mode = MHL_DST_LM_PATH_ENABLED;
1166 
1167         if (ctx->use_packed_pixel)
1168             link_mode |= MHL_DST_LM_CLK_MODE_PACKED_PIXEL;
1169         else
1170             link_mode |= MHL_DST_LM_CLK_MODE_NORMAL;
1171 
1172         sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), link_mode);
1173         sii8620_set_auto_zone(ctx);
1174     } else {
1175         static const struct {
1176             int max_clk;
1177             u8 zone;
1178             u8 link_rate;
1179             u8 rrp_decode;
1180         } clk_spec[] = {
1181             { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS,
1182               MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 },
1183             { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS,
1184               MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 },
1185             { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS,
1186               MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 },
1187         };
1188         u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN;
1189         int clk = mode->clock * (ctx->use_packed_pixel ? 2 : 3);
1190         int i;
1191 
1192         for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i)
1193             if (clk < clk_spec[i].max_clk)
1194                 break;
1195 
1196         if (100 * clk >= 98 * clk_spec[i].max_clk)
1197             p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN;
1198 
1199         sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel);
1200         sii8620_burst_send(ctx);
1201         sii8620_write_seq(ctx,
1202             REG_MHL_DP_CTL0, 0xf0,
1203             REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone);
1204         sii8620_setbits(ctx, REG_M3_P0CTRL,
1205             BIT_M3_P0CTRL_MHL3_P0_PORT_EN
1206             | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl);
1207         sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE,
1208             clk_spec[i].rrp_decode);
1209         sii8620_write_seq_static(ctx,
1210             REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1211                 | BIT_M3_CTRL_H2M_SWRST,
1212             REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1213         );
1214         sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL),
1215             clk_spec[i].link_rate);
1216     }
1217 
1218     sii8620_set_infoframes(ctx, mode);
1219 }
1220 
1221 static void sii8620_disable_hpd(struct sii8620 *ctx)
1222 {
1223     sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
1224     sii8620_write_seq_static(ctx,
1225         REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN,
1226         REG_INTR8_MASK, 0
1227     );
1228 }
1229 
1230 static void sii8620_enable_hpd(struct sii8620 *ctx)
1231 {
1232     sii8620_setbits(ctx, REG_TMDS_CSTAT_P3,
1233             BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
1234             | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0);
1235     sii8620_write_seq_static(ctx,
1236         REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN
1237             | BIT_HPD_CTRL_HPD_HIGH,
1238     );
1239 }
1240 
1241 static void sii8620_mhl_discover(struct sii8620 *ctx)
1242 {
1243     sii8620_write_seq_static(ctx,
1244         REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1245             | BIT_DISC_CTRL9_DISC_PULSE_PROCEED,
1246         REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K),
1247         REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT
1248             | BIT_MHL_EST_INT
1249             | BIT_NOT_MHL_EST_INT
1250             | BIT_CBUS_MHL3_DISCON_INT
1251             | BIT_CBUS_MHL12_DISCON_INT
1252             | BIT_RGND_READY_INT,
1253         REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1254             | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1255             | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1256         REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1257             | BIT_MHL_DP_CTL0_TX_OE_OVR,
1258         REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1259         REG_MHL_DP_CTL1, 0xA2,
1260         REG_MHL_DP_CTL2, 0x03,
1261         REG_MHL_DP_CTL3, 0x35,
1262         REG_MHL_DP_CTL5, 0x02,
1263         REG_MHL_DP_CTL6, 0x02,
1264         REG_MHL_DP_CTL7, 0x03,
1265         REG_COC_CTLC, 0xFF,
1266         REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1267             | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC,
1268         REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE
1269             | BIT_COC_CALIBRATION_DONE,
1270         REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD
1271             | BIT_CBUS_CMD_ABORT,
1272         REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE
1273             | BIT_CBUS_HPD_CHG
1274             | BIT_CBUS_MSC_MR_WRITE_STAT
1275             | BIT_CBUS_MSC_MR_MSC_MSG
1276             | BIT_CBUS_MSC_MR_WRITE_BURST
1277             | BIT_CBUS_MSC_MR_SET_INT
1278             | BIT_CBUS_MSC_MT_DONE_NACK
1279     );
1280 }
1281 
1282 static void sii8620_peer_specific_init(struct sii8620 *ctx)
1283 {
1284     if (sii8620_is_mhl3(ctx))
1285         sii8620_write_seq_static(ctx,
1286             REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD,
1287             REG_EMSCINTRMASK1,
1288                 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
1289         );
1290     else
1291         sii8620_write_seq_static(ctx,
1292             REG_HDCP2X_INTR0_MASK, 0x00,
1293             REG_EMSCINTRMASK1, 0x00,
1294             REG_HDCP2X_INTR0, 0xFF,
1295             REG_INTR1, 0xFF,
1296             REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
1297                 | BIT_SYS_CTRL1_TX_CTRL_HDMI
1298         );
1299 }
1300 
1301 #define SII8620_MHL_VERSION         0x32
1302 #define SII8620_SCRATCHPAD_SIZE         16
1303 #define SII8620_INT_STAT_SIZE           0x33
1304 
1305 static void sii8620_set_dev_cap(struct sii8620 *ctx)
1306 {
1307     static const u8 devcap[MHL_DCAP_SIZE] = {
1308         [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
1309         [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
1310         [MHL_DCAP_ADOPTER_ID_H] = 0x01,
1311         [MHL_DCAP_ADOPTER_ID_L] = 0x41,
1312         [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
1313             | MHL_DCAP_VID_LINK_PPIXEL
1314             | MHL_DCAP_VID_LINK_16BPP,
1315         [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH,
1316         [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS,
1317         [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI,
1318         [MHL_DCAP_BANDWIDTH] = 0x0f,
1319         [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT
1320             | MHL_DCAP_FEATURE_RAP_SUPPORT
1321             | MHL_DCAP_FEATURE_SP_SUPPORT,
1322         [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
1323         [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
1324     };
1325     static const u8 xdcap[MHL_XDC_SIZE] = {
1326         [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
1327             | MHL_XDC_ECBUS_S_8BIT,
1328         [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
1329             | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600,
1330         [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST,
1331         [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
1332     };
1333 
1334     sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
1335     sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
1336 }
1337 
1338 static void sii8620_mhl_init(struct sii8620 *ctx)
1339 {
1340     sii8620_write_seq_static(ctx,
1341         REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1342         REG_CBUS_MSC_COMPAT_CTRL,
1343             BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
1344     );
1345 
1346     sii8620_peer_specific_init(ctx);
1347 
1348     sii8620_disable_hpd(ctx);
1349 
1350     sii8620_write_seq_static(ctx,
1351         REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
1352         REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1353             | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1354         REG_TMDS0_CCTRL1, 0x90,
1355         REG_TMDS_CLK_EN, 0x01,
1356         REG_TMDS_CH_EN, 0x11,
1357         REG_BGR_BIAS, 0x87,
1358         REG_ALICE0_ZONE_CTRL, 0xE8,
1359         REG_ALICE0_MODE_CTRL, 0x04,
1360     );
1361     sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0);
1362     sii8620_write_seq_static(ctx,
1363         REG_TPI_HW_OPT3, 0x76,
1364         REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE,
1365         REG_TPI_DTD_B2, 79,
1366     );
1367     sii8620_set_dev_cap(ctx);
1368     sii8620_write_seq_static(ctx,
1369         REG_MDT_XMIT_TIMEOUT, 100,
1370         REG_MDT_XMIT_CTRL, 0x03,
1371         REG_MDT_XFIFO_STAT, 0x00,
1372         REG_MDT_RCV_TIMEOUT, 100,
1373         REG_CBUS_LINK_CTRL_8, 0x1D,
1374     );
1375 
1376     sii8620_start_gen2_write_burst(ctx);
1377     sii8620_write_seq_static(ctx,
1378         REG_BIST_CTRL, 0x00,
1379         REG_COC_CTL1, 0x10,
1380         REG_COC_CTL2, 0x18,
1381         REG_COC_CTLF, 0x07,
1382         REG_COC_CTL11, 0xF8,
1383         REG_COC_CTL17, 0x61,
1384         REG_COC_CTL18, 0x46,
1385         REG_COC_CTL19, 0x15,
1386         REG_COC_CTL1A, 0x01,
1387         REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
1388         REG_MHL_COC_CTL4, 0x2D,
1389         REG_MHL_COC_CTL5, 0xF9,
1390         REG_MSC_HEARTBEAT_CTRL, 0x27,
1391     );
1392     sii8620_disable_gen2_write_burst(ctx);
1393 
1394     sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION);
1395     sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
1396                   MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
1397                   | MHL_DST_CONN_POW_STAT);
1398     sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
1399 }
1400 
1401 static void sii8620_emsc_enable(struct sii8620 *ctx)
1402 {
1403     u8 reg;
1404 
1405     sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN
1406                      | BIT_GENCTL_CLR_EMSC_RFIFO
1407                      | BIT_GENCTL_CLR_EMSC_XFIFO, ~0);
1408     sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO
1409                      | BIT_GENCTL_CLR_EMSC_XFIFO, 0);
1410     sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0);
1411     reg = sii8620_readb(ctx, REG_EMSCINTR);
1412     sii8620_write(ctx, REG_EMSCINTR, reg);
1413     sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD);
1414 }
1415 
1416 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
1417 {
1418     int i;
1419 
1420     for (i = 0; i < 10; ++i) {
1421         u8 s = sii8620_readb(ctx, REG_COC_STAT_0);
1422 
1423         if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
1424             return 0;
1425         if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
1426             return -EBUSY;
1427         usleep_range(4000, 6000);
1428     }
1429     return -ETIMEDOUT;
1430 }
1431 
1432 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
1433 {
1434     int ret;
1435 
1436     if (ctx->mode == mode)
1437         return;
1438 
1439     switch (mode) {
1440     case CM_MHL1:
1441         sii8620_write_seq_static(ctx,
1442             REG_CBUS_MSC_COMPAT_CTRL, 0x02,
1443             REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
1444             REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1445                 | BIT_DPD_OSC_EN,
1446             REG_COC_INTR_MASK, 0
1447         );
1448         ctx->mode = mode;
1449         break;
1450     case CM_MHL3:
1451         sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
1452         ctx->mode = mode;
1453         return;
1454     case CM_ECBUS_S:
1455         sii8620_emsc_enable(ctx);
1456         sii8620_write_seq_static(ctx,
1457             REG_TTXSPINUMS, 4,
1458             REG_TRXSPINUMS, 4,
1459             REG_TTXHSICNUMS, 0x14,
1460             REG_TRXHSICNUMS, 0x14,
1461             REG_TTXTOTNUMS, 0x18,
1462             REG_TRXTOTNUMS, 0x18,
1463             REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST
1464                       | BIT_PWD_SRST_CBUS_RST_SW_EN,
1465             REG_MHL_COC_CTL1, 0xbd,
1466             REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN,
1467             REG_COC_CTLB, 0x01,
1468             REG_COC_CTL0, 0x5c,
1469             REG_COC_CTL14, 0x03,
1470             REG_COC_CTL15, 0x80,
1471             REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN
1472                      | BIT_MHL_DP_CTL6_DP_TAP1_EN
1473                      | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN,
1474             REG_MHL_DP_CTL8, 0x03
1475         );
1476         ret = sii8620_wait_for_fsm_state(ctx, 0x03);
1477         sii8620_write_seq_static(ctx,
1478             REG_COC_CTL14, 0x00,
1479             REG_COC_CTL15, 0x80
1480         );
1481         if (!ret)
1482             sii8620_write(ctx, REG_CBUS3_CNVT, 0x85);
1483         else
1484             sii8620_disconnect(ctx);
1485         return;
1486     case CM_DISCONNECTED:
1487         ctx->mode = mode;
1488         break;
1489     default:
1490         dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
1491         break;
1492     }
1493 
1494     sii8620_set_auto_zone(ctx);
1495 
1496     if (mode != CM_MHL1)
1497         return;
1498 
1499     sii8620_write_seq_static(ctx,
1500         REG_MHL_DP_CTL0, 0xBC,
1501         REG_MHL_DP_CTL1, 0xBB,
1502         REG_MHL_DP_CTL3, 0x48,
1503         REG_MHL_DP_CTL5, 0x39,
1504         REG_MHL_DP_CTL2, 0x2A,
1505         REG_MHL_DP_CTL6, 0x2A,
1506         REG_MHL_DP_CTL7, 0x08
1507     );
1508 }
1509 
1510 static void sii8620_hpd_unplugged(struct sii8620 *ctx)
1511 {
1512     sii8620_disable_hpd(ctx);
1513     ctx->sink_type = SINK_NONE;
1514     ctx->sink_detected = false;
1515     ctx->feature_complete = false;
1516     kfree(ctx->edid);
1517     ctx->edid = NULL;
1518 }
1519 
1520 static void sii8620_disconnect(struct sii8620 *ctx)
1521 {
1522     sii8620_disable_gen2_write_burst(ctx);
1523     sii8620_stop_video(ctx);
1524     msleep(100);
1525     sii8620_cbus_reset(ctx);
1526     sii8620_set_mode(ctx, CM_DISCONNECTED);
1527     sii8620_write_seq_static(ctx,
1528         REG_TX_ZONE_CTL1, 0,
1529         REG_MHL_PLL_CTL0, 0x07,
1530         REG_COC_CTL0, 0x40,
1531         REG_CBUS3_CNVT, 0x84,
1532         REG_COC_CTL14, 0x00,
1533         REG_COC_CTL0, 0x40,
1534         REG_HRXCTRL3, 0x07,
1535         REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1536             | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1537             | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1538         REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1539             | BIT_MHL_DP_CTL0_TX_OE_OVR,
1540         REG_MHL_DP_CTL1, 0xBB,
1541         REG_MHL_DP_CTL3, 0x48,
1542         REG_MHL_DP_CTL5, 0x3F,
1543         REG_MHL_DP_CTL2, 0x2F,
1544         REG_MHL_DP_CTL6, 0x2A,
1545         REG_MHL_DP_CTL7, 0x03
1546     );
1547     sii8620_hpd_unplugged(ctx);
1548     sii8620_write_seq_static(ctx,
1549         REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1550         REG_MHL_COC_CTL1, 0x07,
1551         REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1552         REG_DISC_CTRL8, 0x00,
1553         REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1554             | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1555         REG_INT_CTRL, 0x00,
1556         REG_MSC_HEARTBEAT_CTRL, 0x27,
1557         REG_DISC_CTRL1, 0x25,
1558         REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
1559         REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
1560         REG_MDT_INT_1, 0xff,
1561         REG_MDT_INT_1_MASK, 0x00,
1562         REG_MDT_INT_0, 0xff,
1563         REG_MDT_INT_0_MASK, 0x00,
1564         REG_COC_INTR, 0xff,
1565         REG_COC_INTR_MASK, 0x00,
1566         REG_TRXINTH, 0xff,
1567         REG_TRXINTMH, 0x00,
1568         REG_CBUS_INT_0, 0xff,
1569         REG_CBUS_INT_0_MASK, 0x00,
1570         REG_CBUS_INT_1, 0xff,
1571         REG_CBUS_INT_1_MASK, 0x00,
1572         REG_EMSCINTR, 0xff,
1573         REG_EMSCINTRMASK, 0x00,
1574         REG_EMSCINTR1, 0xff,
1575         REG_EMSCINTRMASK1, 0x00,
1576         REG_INTR8, 0xff,
1577         REG_INTR8_MASK, 0x00,
1578         REG_TPI_INTR_ST0, 0xff,
1579         REG_TPI_INTR_EN, 0x00,
1580         REG_HDCP2X_INTR0, 0xff,
1581         REG_HDCP2X_INTR0_MASK, 0x00,
1582         REG_INTR9, 0xff,
1583         REG_INTR9_MASK, 0x00,
1584         REG_INTR3, 0xff,
1585         REG_INTR3_MASK, 0x00,
1586         REG_INTR5, 0xff,
1587         REG_INTR5_MASK, 0x00,
1588         REG_INTR2, 0xff,
1589         REG_INTR2_MASK, 0x00,
1590     );
1591     memset(ctx->stat, 0, sizeof(ctx->stat));
1592     memset(ctx->xstat, 0, sizeof(ctx->xstat));
1593     memset(ctx->devcap, 0, sizeof(ctx->devcap));
1594     memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap));
1595     ctx->devcap_read = false;
1596     ctx->cbus_status = 0;
1597     sii8620_mt_cleanup(ctx);
1598 }
1599 
1600 static void sii8620_mhl_disconnected(struct sii8620 *ctx)
1601 {
1602     sii8620_write_seq_static(ctx,
1603         REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1604         REG_CBUS_MSC_COMPAT_CTRL,
1605             BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
1606     );
1607     sii8620_disconnect(ctx);
1608 }
1609 
1610 static void sii8620_irq_disc(struct sii8620 *ctx)
1611 {
1612     u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0);
1613 
1614     if (stat & VAL_CBUS_MHL_DISCON)
1615         sii8620_mhl_disconnected(ctx);
1616 
1617     if (stat & BIT_RGND_READY_INT) {
1618         u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2);
1619 
1620         if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) {
1621             sii8620_mhl_discover(ctx);
1622         } else {
1623             sii8620_write_seq_static(ctx,
1624                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1625                     | BIT_DISC_CTRL9_NOMHL_EST
1626                     | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1627                 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT
1628                     | BIT_CBUS_MHL3_DISCON_INT
1629                     | BIT_CBUS_MHL12_DISCON_INT
1630                     | BIT_NOT_MHL_EST_INT
1631             );
1632         }
1633     }
1634     if (stat & BIT_MHL_EST_INT)
1635         sii8620_mhl_init(ctx);
1636 
1637     sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
1638 }
1639 
1640 static void sii8620_read_burst(struct sii8620 *ctx)
1641 {
1642     u8 buf[17];
1643 
1644     sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf));
1645     sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN |
1646               BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN |
1647               BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR);
1648     sii8620_readb(ctx, REG_MDT_RFIFO_STAT);
1649 }
1650 
1651 static void sii8620_irq_g2wb(struct sii8620 *ctx)
1652 {
1653     u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
1654 
1655     if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
1656         if (sii8620_is_mhl3(ctx))
1657             sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
1658                 MHL_INT_RC_FEAT_COMPLETE);
1659 
1660     if (stat & BIT_MDT_RFIFO_DATA_RDY)
1661         sii8620_read_burst(ctx);
1662 
1663     if (stat & BIT_MDT_XFIFO_EMPTY)
1664         sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0);
1665 
1666     sii8620_write(ctx, REG_MDT_INT_0, stat);
1667 }
1668 
1669 static void sii8620_status_dcap_ready(struct sii8620 *ctx)
1670 {
1671     enum sii8620_mode mode;
1672 
1673     mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1;
1674     if (mode > ctx->mode)
1675         sii8620_set_mode(ctx, mode);
1676     sii8620_peer_specific_init(ctx);
1677     sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
1678               | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
1679 }
1680 
1681 static void sii8620_status_changed_path(struct sii8620 *ctx)
1682 {
1683     u8 link_mode;
1684 
1685     if (ctx->use_packed_pixel)
1686         link_mode = MHL_DST_LM_CLK_MODE_PACKED_PIXEL;
1687     else
1688         link_mode = MHL_DST_LM_CLK_MODE_NORMAL;
1689 
1690     if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1691         link_mode |= MHL_DST_LM_PATH_ENABLED;
1692 
1693     sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1694                   link_mode);
1695 }
1696 
1697 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
1698 {
1699     u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE];
1700 
1701     sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE);
1702     sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE);
1703 
1704     sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
1705     sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
1706 
1707     if (ctx->stat[MHL_DST_CONNECTED_RDY] & st[MHL_DST_CONNECTED_RDY] &
1708         MHL_DST_CONN_DCAP_RDY) {
1709         sii8620_status_dcap_ready(ctx);
1710 
1711         if (!sii8620_is_mhl3(ctx))
1712             sii8620_mt_read_devcap(ctx, false);
1713     }
1714 
1715     if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1716         sii8620_status_changed_path(ctx);
1717 }
1718 
1719 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret)
1720 {
1721     if (ret < 0)
1722         return;
1723 
1724     sii8620_set_mode(ctx, CM_ECBUS_S);
1725 }
1726 
1727 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret)
1728 {
1729     if (ret < 0)
1730         return;
1731 
1732     sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
1733                   MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
1734     sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
1735     sii8620_mt_set_cont(ctx, sii8620_ecbus_up);
1736 }
1737 
1738 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d,
1739     enum mhl_burst_id id)
1740 {
1741     sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT);
1742     d->num_entries = 1;
1743     d->burst_id[0] = cpu_to_be16(id);
1744 }
1745 
1746 static void sii8620_send_features(struct sii8620 *ctx)
1747 {
1748     u8 buf[16];
1749 
1750     sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN
1751         | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN);
1752     sii8620_mhl_burst_emsc_support_set((void *)buf,
1753         MHL_BURST_ID_HID_PAYLOAD);
1754     sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
1755 }
1756 
1757 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode)
1758 {
1759     bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK);
1760 
1761     scancode &= MHL_RCP_KEY_ID_MASK;
1762 
1763     if (!IS_ENABLED(CONFIG_RC_CORE) || !ctx->rc_dev)
1764         return false;
1765 
1766     if (pressed)
1767         rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0);
1768     else
1769         rc_keyup(ctx->rc_dev);
1770 
1771     return true;
1772 }
1773 
1774 static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
1775 {
1776     u8 ints[MHL_INT_SIZE];
1777 
1778     sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1779     sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1780 
1781     if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) {
1782         switch (ctx->mode) {
1783         case CM_MHL3:
1784             sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS);
1785             sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed);
1786             break;
1787         case CM_ECBUS_S:
1788             sii8620_mt_read_devcap(ctx, true);
1789             break;
1790         default:
1791             break;
1792         }
1793     }
1794     if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ)
1795         sii8620_send_features(ctx);
1796     if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) {
1797         ctx->feature_complete = true;
1798         if (ctx->edid)
1799             sii8620_enable_hpd(ctx);
1800     }
1801 }
1802 
1803 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
1804 {
1805     struct device *dev = ctx->dev;
1806 
1807     if (list_empty(&ctx->mt_queue)) {
1808         dev_err(dev, "unexpected MSC MT response\n");
1809         return NULL;
1810     }
1811 
1812     return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
1813 }
1814 
1815 static void sii8620_msc_mt_done(struct sii8620 *ctx)
1816 {
1817     struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1818 
1819     if (!msg)
1820         return;
1821 
1822     msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0);
1823     ctx->mt_state = MT_STATE_DONE;
1824 }
1825 
1826 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
1827 {
1828     struct sii8620_mt_msg *msg;
1829     u8 buf[2];
1830 
1831     sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
1832 
1833     switch (buf[0]) {
1834     case MHL_MSC_MSG_RAPK:
1835         msg = sii8620_msc_msg_first(ctx);
1836         if (!msg)
1837             return;
1838         msg->ret = buf[1];
1839         ctx->mt_state = MT_STATE_DONE;
1840         break;
1841     case MHL_MSC_MSG_RCP:
1842         if (!sii8620_rcp_consume(ctx, buf[1]))
1843             sii8620_mt_rcpe(ctx,
1844                     MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE);
1845         sii8620_mt_rcpk(ctx, buf[1]);
1846         break;
1847     default:
1848         dev_err(ctx->dev, "%s message type %d,%d not supported",
1849             __func__, buf[0], buf[1]);
1850     }
1851 }
1852 
1853 static void sii8620_irq_msc(struct sii8620 *ctx)
1854 {
1855     u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0);
1856 
1857     if (stat & ~BIT_CBUS_HPD_CHG)
1858         sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG);
1859 
1860     if (stat & BIT_CBUS_HPD_CHG) {
1861         u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS);
1862 
1863         if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) {
1864             sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG);
1865         } else {
1866             stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1867             cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1868         }
1869         ctx->cbus_status = cbus_stat;
1870     }
1871 
1872     if (stat & BIT_CBUS_MSC_MR_WRITE_STAT)
1873         sii8620_msc_mr_write_stat(ctx);
1874 
1875     if (stat & BIT_CBUS_HPD_CHG) {
1876         if (ctx->cbus_status & BIT_CBUS_STATUS_CBUS_HPD) {
1877             ctx->sink_detected = true;
1878             sii8620_identify_sink(ctx);
1879         } else {
1880             sii8620_hpd_unplugged(ctx);
1881         }
1882     }
1883 
1884     if (stat & BIT_CBUS_MSC_MR_SET_INT)
1885         sii8620_msc_mr_set_int(ctx);
1886 
1887     if (stat & BIT_CBUS_MSC_MT_DONE)
1888         sii8620_msc_mt_done(ctx);
1889 
1890     if (stat & BIT_CBUS_MSC_MR_MSC_MSG)
1891         sii8620_msc_mr_msc_msg(ctx);
1892 }
1893 
1894 static void sii8620_irq_coc(struct sii8620 *ctx)
1895 {
1896     u8 stat = sii8620_readb(ctx, REG_COC_INTR);
1897 
1898     if (stat & BIT_COC_CALIBRATION_DONE) {
1899         u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
1900 
1901         cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
1902         if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
1903             sii8620_write_seq_static(ctx,
1904                 REG_COC_CTLB, 0,
1905                 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
1906                           | BIT_TDM_INTR_SYNC_WAIT
1907             );
1908         }
1909     }
1910 
1911     sii8620_write(ctx, REG_COC_INTR, stat);
1912 }
1913 
1914 static void sii8620_irq_merr(struct sii8620 *ctx)
1915 {
1916     u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1);
1917 
1918     sii8620_write(ctx, REG_CBUS_INT_1, stat);
1919 }
1920 
1921 static void sii8620_irq_edid(struct sii8620 *ctx)
1922 {
1923     u8 stat = sii8620_readb(ctx, REG_INTR9);
1924 
1925     sii8620_write(ctx, REG_INTR9, stat);
1926 
1927     if (stat & BIT_INTR9_DEVCAP_DONE)
1928         ctx->mt_state = MT_STATE_DONE;
1929 }
1930 
1931 static void sii8620_irq_scdt(struct sii8620 *ctx)
1932 {
1933     u8 stat = sii8620_readb(ctx, REG_INTR5);
1934 
1935     if (stat & BIT_INTR_SCDT_CHANGE) {
1936         u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
1937 
1938         if (cstat & BIT_TMDS_CSTAT_P3_SCDT)
1939             sii8620_start_video(ctx);
1940     }
1941 
1942     sii8620_write(ctx, REG_INTR5, stat);
1943 }
1944 
1945 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret)
1946 {
1947     if (ret < 0)
1948         return;
1949 
1950     sii8620_mt_read_devcap(ctx, false);
1951 }
1952 
1953 static void sii8620_irq_tdm(struct sii8620 *ctx)
1954 {
1955     u8 stat = sii8620_readb(ctx, REG_TRXINTH);
1956     u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
1957 
1958     if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
1959         ctx->mode = CM_ECBUS_S;
1960         ctx->burst.rx_ack = 0;
1961         ctx->burst.r_size = SII8620_BURST_BUF_LEN;
1962         sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
1963         sii8620_mt_read_devcap(ctx, true);
1964         sii8620_mt_set_cont(ctx, sii8620_got_xdevcap);
1965     } else {
1966         sii8620_write_seq_static(ctx,
1967             REG_MHL_PLL_CTL2, 0,
1968             REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
1969         );
1970     }
1971 
1972     sii8620_write(ctx, REG_TRXINTH, stat);
1973 }
1974 
1975 static void sii8620_irq_block(struct sii8620 *ctx)
1976 {
1977     u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
1978 
1979     if (stat & BIT_EMSCINTR_SPI_DVLD) {
1980         u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
1981 
1982         if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
1983             sii8620_burst_receive(ctx);
1984     }
1985 
1986     sii8620_write(ctx, REG_EMSCINTR, stat);
1987 }
1988 
1989 static void sii8620_irq_ddc(struct sii8620 *ctx)
1990 {
1991     u8 stat = sii8620_readb(ctx, REG_INTR3);
1992 
1993     if (stat & BIT_DDC_CMD_DONE) {
1994         sii8620_write(ctx, REG_INTR3_MASK, 0);
1995         if (sii8620_is_mhl3(ctx) && !ctx->feature_complete)
1996             sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
1997                        MHL_INT_RC_FEAT_REQ);
1998         else
1999             sii8620_enable_hpd(ctx);
2000     }
2001     sii8620_write(ctx, REG_INTR3, stat);
2002 }
2003 
2004 /* endian agnostic, non-volatile version of test_bit */
2005 static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
2006 {
2007     return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE));
2008 }
2009 
2010 static irqreturn_t sii8620_irq_thread(int irq, void *data)
2011 {
2012     static const struct {
2013         int bit;
2014         void (*handler)(struct sii8620 *ctx);
2015     } irq_vec[] = {
2016         { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
2017         { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
2018         { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
2019         { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
2020         { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
2021         { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
2022         { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
2023         { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
2024         { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc },
2025         { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
2026     };
2027     struct sii8620 *ctx = data;
2028     u8 stats[LEN_FAST_INTR_STAT];
2029     int i, ret;
2030 
2031     mutex_lock(&ctx->lock);
2032 
2033     sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats));
2034     for (i = 0; i < ARRAY_SIZE(irq_vec); ++i)
2035         if (sii8620_test_bit(irq_vec[i].bit, stats))
2036             irq_vec[i].handler(ctx);
2037 
2038     sii8620_burst_rx_all(ctx);
2039     sii8620_mt_work(ctx);
2040     sii8620_burst_send(ctx);
2041 
2042     ret = sii8620_clear_error(ctx);
2043     if (ret) {
2044         dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret);
2045         sii8620_mhl_disconnected(ctx);
2046     }
2047     mutex_unlock(&ctx->lock);
2048 
2049     return IRQ_HANDLED;
2050 }
2051 
2052 static void sii8620_cable_in(struct sii8620 *ctx)
2053 {
2054     struct device *dev = ctx->dev;
2055     u8 ver[5];
2056     int ret;
2057 
2058     ret = sii8620_hw_on(ctx);
2059     if (ret) {
2060         dev_err(dev, "Error powering on, %d.\n", ret);
2061         return;
2062     }
2063 
2064     sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver));
2065     ret = sii8620_clear_error(ctx);
2066     if (ret) {
2067         dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2068         return;
2069     }
2070 
2071     dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0],
2072          ver[3], ver[2], ver[4]);
2073 
2074     sii8620_write(ctx, REG_DPD,
2075               BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN);
2076 
2077     sii8620_xtal_set_rate(ctx);
2078     sii8620_disconnect(ctx);
2079 
2080     sii8620_write_seq_static(ctx,
2081         REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
2082             | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734,
2083         REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM,
2084         REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN,
2085     );
2086 
2087     ret = sii8620_clear_error(ctx);
2088     if (ret) {
2089         dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2090         return;
2091     }
2092 
2093     enable_irq(to_i2c_client(ctx->dev)->irq);
2094 }
2095 
2096 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx)
2097 {
2098     struct rc_dev *rc_dev;
2099     int ret;
2100 
2101     if (!IS_ENABLED(CONFIG_RC_CORE))
2102         return;
2103 
2104     rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE);
2105     if (!rc_dev) {
2106         dev_err(ctx->dev, "Failed to allocate RC device\n");
2107         ctx->error = -ENOMEM;
2108         return;
2109     }
2110 
2111     rc_dev->input_phys = "sii8620/input0";
2112     rc_dev->input_id.bustype = BUS_VIRTUAL;
2113     rc_dev->map_name = RC_MAP_CEC;
2114     rc_dev->allowed_protocols = RC_PROTO_BIT_CEC;
2115     rc_dev->driver_name = "sii8620";
2116     rc_dev->device_name = "sii8620";
2117 
2118     ret = rc_register_device(rc_dev);
2119 
2120     if (ret) {
2121         dev_err(ctx->dev, "Failed to register RC device\n");
2122         ctx->error = ret;
2123         rc_free_device(rc_dev);
2124         return;
2125     }
2126     ctx->rc_dev = rc_dev;
2127 }
2128 
2129 static void sii8620_cable_out(struct sii8620 *ctx)
2130 {
2131     disable_irq(to_i2c_client(ctx->dev)->irq);
2132     sii8620_hw_off(ctx);
2133 }
2134 
2135 static void sii8620_extcon_work(struct work_struct *work)
2136 {
2137     struct sii8620 *ctx =
2138         container_of(work, struct sii8620, extcon_wq);
2139     int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL);
2140 
2141     if (state == ctx->cable_state)
2142         return;
2143 
2144     ctx->cable_state = state;
2145 
2146     if (state > 0)
2147         sii8620_cable_in(ctx);
2148     else
2149         sii8620_cable_out(ctx);
2150 }
2151 
2152 static int sii8620_extcon_notifier(struct notifier_block *self,
2153             unsigned long event, void *ptr)
2154 {
2155     struct sii8620 *ctx =
2156         container_of(self, struct sii8620, extcon_nb);
2157 
2158     schedule_work(&ctx->extcon_wq);
2159 
2160     return NOTIFY_DONE;
2161 }
2162 
2163 static int sii8620_extcon_init(struct sii8620 *ctx)
2164 {
2165     struct extcon_dev *edev;
2166     struct device_node *musb, *muic;
2167     int ret;
2168 
2169     /* get micro-USB connector node */
2170     musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1);
2171     /* next get micro-USB Interface Controller node */
2172     muic = of_get_next_parent(musb);
2173 
2174     if (!muic) {
2175         dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n");
2176         return 0;
2177     }
2178 
2179     edev = extcon_find_edev_by_node(muic);
2180     of_node_put(muic);
2181     if (IS_ERR(edev)) {
2182         if (PTR_ERR(edev) == -EPROBE_DEFER)
2183             return -EPROBE_DEFER;
2184         dev_err(ctx->dev, "Invalid or missing extcon\n");
2185         return PTR_ERR(edev);
2186     }
2187 
2188     ctx->extcon = edev;
2189     ctx->extcon_nb.notifier_call = sii8620_extcon_notifier;
2190     INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work);
2191     ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb);
2192     if (ret) {
2193         dev_err(ctx->dev, "failed to register notifier for MHL\n");
2194         return ret;
2195     }
2196 
2197     return 0;
2198 }
2199 
2200 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
2201 {
2202     return container_of(bridge, struct sii8620, bridge);
2203 }
2204 
2205 static int sii8620_attach(struct drm_bridge *bridge,
2206               enum drm_bridge_attach_flags flags)
2207 {
2208     struct sii8620 *ctx = bridge_to_sii8620(bridge);
2209 
2210     sii8620_init_rcp_input_dev(ctx);
2211 
2212     return sii8620_clear_error(ctx);
2213 }
2214 
2215 static void sii8620_detach(struct drm_bridge *bridge)
2216 {
2217     struct sii8620 *ctx = bridge_to_sii8620(bridge);
2218 
2219     if (!IS_ENABLED(CONFIG_RC_CORE))
2220         return;
2221 
2222     rc_unregister_device(ctx->rc_dev);
2223 }
2224 
2225 static int sii8620_is_packing_required(struct sii8620 *ctx,
2226                        const struct drm_display_mode *mode)
2227 {
2228     int max_pclk, max_pclk_pp_mode;
2229 
2230     if (sii8620_is_mhl3(ctx)) {
2231         max_pclk = MHL3_MAX_PCLK;
2232         max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE;
2233     } else {
2234         max_pclk = MHL1_MAX_PCLK;
2235         max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE;
2236     }
2237 
2238     if (mode->clock < max_pclk)
2239         return 0;
2240     else if (mode->clock < max_pclk_pp_mode)
2241         return 1;
2242     else
2243         return -1;
2244 }
2245 
2246 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge,
2247                      const struct drm_display_info *info,
2248                      const struct drm_display_mode *mode)
2249 {
2250     struct sii8620 *ctx = bridge_to_sii8620(bridge);
2251     int pack_required = sii8620_is_packing_required(ctx, mode);
2252     bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] &
2253             MHL_DCAP_VID_LINK_PPIXEL;
2254 
2255     switch (pack_required) {
2256     case 0:
2257         return MODE_OK;
2258     case 1:
2259         return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH;
2260     default:
2261         return MODE_CLOCK_HIGH;
2262     }
2263 }
2264 
2265 static bool sii8620_mode_fixup(struct drm_bridge *bridge,
2266                    const struct drm_display_mode *mode,
2267                    struct drm_display_mode *adjusted_mode)
2268 {
2269     struct sii8620 *ctx = bridge_to_sii8620(bridge);
2270 
2271     mutex_lock(&ctx->lock);
2272 
2273     ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode);
2274 
2275     mutex_unlock(&ctx->lock);
2276 
2277     return true;
2278 }
2279 
2280 static const struct drm_bridge_funcs sii8620_bridge_funcs = {
2281     .attach = sii8620_attach,
2282     .detach = sii8620_detach,
2283     .mode_fixup = sii8620_mode_fixup,
2284     .mode_valid = sii8620_mode_valid,
2285 };
2286 
2287 static int sii8620_probe(struct i2c_client *client,
2288              const struct i2c_device_id *id)
2289 {
2290     struct device *dev = &client->dev;
2291     struct sii8620 *ctx;
2292     int ret;
2293 
2294     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2295     if (!ctx)
2296         return -ENOMEM;
2297 
2298     ctx->dev = dev;
2299     mutex_init(&ctx->lock);
2300     INIT_LIST_HEAD(&ctx->mt_queue);
2301 
2302     ctx->clk_xtal = devm_clk_get(dev, "xtal");
2303     if (IS_ERR(ctx->clk_xtal))
2304         return dev_err_probe(dev, PTR_ERR(ctx->clk_xtal),
2305                      "failed to get xtal clock from DT\n");
2306 
2307     if (!client->irq) {
2308         dev_err(dev, "no irq provided\n");
2309         return -EINVAL;
2310     }
2311     irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
2312     ret = devm_request_threaded_irq(dev, client->irq, NULL,
2313                     sii8620_irq_thread,
2314                     IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2315                     "sii8620", ctx);
2316     if (ret < 0)
2317         return dev_err_probe(dev, ret,
2318                      "failed to install IRQ handler\n");
2319 
2320     ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
2321     if (IS_ERR(ctx->gpio_reset))
2322         return dev_err_probe(dev, PTR_ERR(ctx->gpio_reset),
2323                      "failed to get reset gpio from DT\n");
2324 
2325     ctx->supplies[0].supply = "cvcc10";
2326     ctx->supplies[1].supply = "iovcc18";
2327     ret = devm_regulator_bulk_get(dev, 2, ctx->supplies);
2328     if (ret)
2329         return ret;
2330 
2331     ret = sii8620_extcon_init(ctx);
2332     if (ret < 0) {
2333         dev_err(ctx->dev, "failed to initialize EXTCON\n");
2334         return ret;
2335     }
2336 
2337     i2c_set_clientdata(client, ctx);
2338 
2339     ctx->bridge.funcs = &sii8620_bridge_funcs;
2340     ctx->bridge.of_node = dev->of_node;
2341     drm_bridge_add(&ctx->bridge);
2342 
2343     if (!ctx->extcon)
2344         sii8620_cable_in(ctx);
2345 
2346     return 0;
2347 }
2348 
2349 static int sii8620_remove(struct i2c_client *client)
2350 {
2351     struct sii8620 *ctx = i2c_get_clientdata(client);
2352 
2353     if (ctx->extcon) {
2354         extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL,
2355                        &ctx->extcon_nb);
2356         flush_work(&ctx->extcon_wq);
2357         if (ctx->cable_state > 0)
2358             sii8620_cable_out(ctx);
2359     } else {
2360         sii8620_cable_out(ctx);
2361     }
2362     drm_bridge_remove(&ctx->bridge);
2363 
2364     return 0;
2365 }
2366 
2367 static const struct of_device_id sii8620_dt_match[] = {
2368     { .compatible = "sil,sii8620" },
2369     { },
2370 };
2371 MODULE_DEVICE_TABLE(of, sii8620_dt_match);
2372 
2373 static const struct i2c_device_id sii8620_id[] = {
2374     { "sii8620", 0 },
2375     { },
2376 };
2377 
2378 MODULE_DEVICE_TABLE(i2c, sii8620_id);
2379 static struct i2c_driver sii8620_driver = {
2380     .driver = {
2381         .name   = "sii8620",
2382         .of_match_table = of_match_ptr(sii8620_dt_match),
2383     },
2384     .probe      = sii8620_probe,
2385     .remove     = sii8620_remove,
2386     .id_table = sii8620_id,
2387 };
2388 
2389 module_i2c_driver(sii8620_driver);
2390 MODULE_LICENSE("GPL v2");
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