drm/bridge/parade-ps8640.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016 MediaTek Inc.
0004  */
0005
0006 #include <linux/delay.h>
0007 #include <linux/err.h>
0008 #include <linux/gpio/consumer.h>
0009 #include <linux/i2c.h>
0010 #include <linux/module.h>
0011 #include <linux/of_graph.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/regmap.h>
0014 #include <linux/regulator/consumer.h>
0015
0016 #include <drm/display/drm_dp_aux_bus.h>
0017 #include <drm/display/drm_dp_helper.h>
0018 #include <drm/drm_bridge.h>
0019 #include <drm/drm_edid.h>
0020 #include <drm/drm_mipi_dsi.h>
0021 #include <drm/drm_of.h>
0022 #include <drm/drm_panel.h>
0023 #include <drm/drm_print.h>
0024
0025 #define PAGE0_AUXCH_CFG3    0x76
0026 #define  AUXCH_CFG3_RESET   0xff
0027 #define PAGE0_SWAUX_ADDR_7_0    0x7d
0028 #define PAGE0_SWAUX_ADDR_15_8   0x7e
0029 #define PAGE0_SWAUX_ADDR_23_16  0x7f
0030 #define  SWAUX_ADDR_MASK    GENMASK(19, 0)
0031 #define PAGE0_SWAUX_LENGTH  0x80
0032 #define  SWAUX_LENGTH_MASK  GENMASK(3, 0)
0033 #define  SWAUX_NO_PAYLOAD   BIT(7)
0034 #define PAGE0_SWAUX_WDATA   0x81
0035 #define PAGE0_SWAUX_RDATA   0x82
0036 #define PAGE0_SWAUX_CTRL    0x83
0037 #define  SWAUX_SEND     BIT(0)
0038 #define PAGE0_SWAUX_STATUS  0x84
0039 #define  SWAUX_M_MASK       GENMASK(4, 0)
0040 #define  SWAUX_STATUS_MASK  GENMASK(7, 5)
0041 #define  SWAUX_STATUS_NACK  (0x1 << 5)
0042 #define  SWAUX_STATUS_DEFER (0x2 << 5)
0043 #define  SWAUX_STATUS_ACKM  (0x3 << 5)
0044 #define  SWAUX_STATUS_INVALID   (0x4 << 5)
0045 #define  SWAUX_STATUS_I2C_NACK  (0x5 << 5)
0046 #define  SWAUX_STATUS_I2C_DEFER (0x6 << 5)
0047 #define  SWAUX_STATUS_TIMEOUT   (0x7 << 5)
0048
0049 #define PAGE2_GPIO_H        0xa7
0050 #define  PS_GPIO9       BIT(1)
0051 #define PAGE2_I2C_BYPASS    0xea
0052 #define  I2C_BYPASS_EN      0xd0
0053 #define PAGE2_MCS_EN        0xf3
0054 #define  MCS_EN         BIT(0)
0055
0056 #define PAGE3_SET_ADD       0xfe
0057 #define  VDO_CTL_ADD        0x13
0058 #define  VDO_DIS        0x18
0059 #define  VDO_EN         0x1c
0060
0061 #define NUM_MIPI_LANES      4
0062
0063 #define COMMON_PS8640_REGMAP_CONFIG \
0064     .reg_bits = 8, \
0065     .val_bits = 8, \
0066     .cache_type = REGCACHE_NONE
0067
0068 /*
0069  * PS8640 uses multiple addresses:
0070  * page[0]: for DP control
0071  * page[1]: for VIDEO Bridge
0072  * page[2]: for control top
0073  * page[3]: for DSI Link Control1
0074  * page[4]: for MIPI Phy
0075  * page[5]: for VPLL
0076  * page[6]: for DSI Link Control2
0077  * page[7]: for SPI ROM mapping
0078  */
0079 enum page_addr_offset {
0080     PAGE0_DP_CNTL = 0,
0081     PAGE1_VDO_BDG,
0082     PAGE2_TOP_CNTL,
0083     PAGE3_DSI_CNTL1,
0084     PAGE4_MIPI_PHY,
0085     PAGE5_VPLL,
0086     PAGE6_DSI_CNTL2,
0087     PAGE7_SPI_CNTL,
0088     MAX_DEVS
0089 };
0090
0091 enum ps8640_vdo_control {
0092     DISABLE = VDO_DIS,
0093     ENABLE = VDO_EN,
0094 };
0095
0096 struct ps8640 {
0097     struct drm_bridge bridge;
0098     struct drm_bridge *panel_bridge;
0099     struct drm_dp_aux aux;
0100     struct mipi_dsi_device *dsi;
0101     struct i2c_client *page[MAX_DEVS];
0102     struct regmap   *regmap[MAX_DEVS];
0103     struct regulator_bulk_data supplies[2];
0104     struct gpio_desc *gpio_reset;
0105     struct gpio_desc *gpio_powerdown;
0106     struct device_link *link;
0107     bool pre_enabled;
0108 };
0109
0110 static const struct regmap_config ps8640_regmap_config[] = {
0111     [PAGE0_DP_CNTL] = {
0112         COMMON_PS8640_REGMAP_CONFIG,
0113         .max_register = 0xbf,
0114     },
0115     [PAGE1_VDO_BDG] = {
0116         COMMON_PS8640_REGMAP_CONFIG,
0117         .max_register = 0xff,
0118     },
0119     [PAGE2_TOP_CNTL] = {
0120         COMMON_PS8640_REGMAP_CONFIG,
0121         .max_register = 0xff,
0122     },
0123     [PAGE3_DSI_CNTL1] = {
0124         COMMON_PS8640_REGMAP_CONFIG,
0125         .max_register = 0xff,
0126     },
0127     [PAGE4_MIPI_PHY] = {
0128         COMMON_PS8640_REGMAP_CONFIG,
0129         .max_register = 0xff,
0130     },
0131     [PAGE5_VPLL] = {
0132         COMMON_PS8640_REGMAP_CONFIG,
0133         .max_register = 0x7f,
0134     },
0135     [PAGE6_DSI_CNTL2] = {
0136         COMMON_PS8640_REGMAP_CONFIG,
0137         .max_register = 0xff,
0138     },
0139     [PAGE7_SPI_CNTL] = {
0140         COMMON_PS8640_REGMAP_CONFIG,
0141         .max_register = 0xff,
0142     },
0143 };
0144
0145 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
0146 {
0147     return container_of(e, struct ps8640, bridge);
0148 }
0149
0150 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
0151 {
0152     return container_of(aux, struct ps8640, aux);
0153 }
0154
0155 static bool ps8640_of_panel_on_aux_bus(struct device *dev)
0156 {
0157     struct device_node *bus, *panel;
0158
0159     bus = of_get_child_by_name(dev->of_node, "aux-bus");
0160     if (!bus)
0161         return false;
0162
0163     panel = of_get_child_by_name(bus, "panel");
0164     of_node_put(bus);
0165     if (!panel)
0166         return false;
0167     of_node_put(panel);
0168
0169     return true;
0170 }
0171
0172 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
0173 {
0174     struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
0175     int status;
0176
0177     /*
0178      * Apparently something about the firmware in the chip signals that
0179      * HPD goes high by reporting GPIO9 as high (even though HPD isn't
0180      * actually connected to GPIO9).
0181      */
0182     return regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
0183                     status & PS_GPIO9, wait_us / 10, wait_us);
0184 }
0185
0186 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
0187 {
0188     struct ps8640 *ps_bridge = aux_to_ps8640(aux);
0189     struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
0190     int ret;
0191
0192     /*
0193      * Note that this function is called by code that has already powered
0194      * the panel. We have to power ourselves up but we don't need to worry
0195      * about powering the panel.
0196      */
0197     pm_runtime_get_sync(dev);
0198     ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
0199     pm_runtime_mark_last_busy(dev);
0200     pm_runtime_put_autosuspend(dev);
0201
0202     return ret;
0203 }
0204
0205 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
0206                        struct drm_dp_aux_msg *msg)
0207 {
0208     struct ps8640 *ps_bridge = aux_to_ps8640(aux);
0209     struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
0210     struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
0211     unsigned int len = msg->size;
0212     unsigned int data;
0213     unsigned int base;
0214     int ret;
0215     u8 request = msg->request &
0216              ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
0217     u8 *buf = msg->buffer;
0218     u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
0219     u8 i;
0220     bool is_native_aux = false;
0221
0222     if (len > DP_AUX_MAX_PAYLOAD_BYTES)
0223         return -EINVAL;
0224
0225     if (msg->address & ~SWAUX_ADDR_MASK)
0226         return -EINVAL;
0227
0228     switch (request) {
0229     case DP_AUX_NATIVE_WRITE:
0230     case DP_AUX_NATIVE_READ:
0231         is_native_aux = true;
0232         fallthrough;
0233     case DP_AUX_I2C_WRITE:
0234     case DP_AUX_I2C_READ:
0235         break;
0236     default:
0237         return -EINVAL;
0238     }
0239
0240     ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
0241     if (ret) {
0242         DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
0243                   ret);
0244         return ret;
0245     }
0246
0247     /* Assume it's good */
0248     msg->reply = 0;
0249
0250     base = PAGE0_SWAUX_ADDR_7_0;
0251     addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
0252     addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
0253     addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
0254                           (msg->request << 4);
0255     addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
0256                           ((len - 1) & SWAUX_LENGTH_MASK);
0257
0258     regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
0259               ARRAY_SIZE(addr_len));
0260
0261     if (len && (request == DP_AUX_NATIVE_WRITE ||
0262             request == DP_AUX_I2C_WRITE)) {
0263         /* Write to the internal FIFO buffer */
0264         for (i = 0; i < len; i++) {
0265             ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
0266             if (ret) {
0267                 DRM_DEV_ERROR(dev,
0268                           "failed to write WDATA: %d\n",
0269                           ret);
0270                 return ret;
0271             }
0272         }
0273     }
0274
0275     regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
0276
0277     /* Zero delay loop because i2c transactions are slow already */
0278     regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
0279                  !(data & SWAUX_SEND), 0, 50 * 1000);
0280
0281     regmap_read(map, PAGE0_SWAUX_STATUS, &data);
0282     if (ret) {
0283         DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
0284                   ret);
0285         return ret;
0286     }
0287
0288     switch (data & SWAUX_STATUS_MASK) {
0289     /* Ignore the DEFER cases as they are already handled in hardware */
0290     case SWAUX_STATUS_NACK:
0291     case SWAUX_STATUS_I2C_NACK:
0292         /*
0293          * The programming guide is not clear about whether a I2C NACK
0294          * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
0295          * we handle both cases together.
0296          */
0297         if (is_native_aux)
0298             msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
0299         else
0300             msg->reply |= DP_AUX_I2C_REPLY_NACK;
0301
0302         fallthrough;
0303     case SWAUX_STATUS_ACKM:
0304         len = data & SWAUX_M_MASK;
0305         break;
0306     case SWAUX_STATUS_INVALID:
0307         return -EOPNOTSUPP;
0308     case SWAUX_STATUS_TIMEOUT:
0309         return -ETIMEDOUT;
0310     }
0311
0312     if (len && (request == DP_AUX_NATIVE_READ ||
0313             request == DP_AUX_I2C_READ)) {
0314         /* Read from the internal FIFO buffer */
0315         for (i = 0; i < len; i++) {
0316             ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
0317             if (ret) {
0318                 DRM_DEV_ERROR(dev,
0319                           "failed to read RDATA: %d\n",
0320                           ret);
0321                 return ret;
0322             }
0323
0324             buf[i] = data;
0325         }
0326     }
0327
0328     return len;
0329 }
0330
0331 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
0332                    struct drm_dp_aux_msg *msg)
0333 {
0334     struct ps8640 *ps_bridge = aux_to_ps8640(aux);
0335     struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
0336     int ret;
0337
0338     pm_runtime_get_sync(dev);
0339     ret = ps8640_aux_transfer_msg(aux, msg);
0340     pm_runtime_mark_last_busy(dev);
0341     pm_runtime_put_autosuspend(dev);
0342
0343     return ret;
0344 }
0345
0346 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
0347                       const enum ps8640_vdo_control ctrl)
0348 {
0349     struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
0350     struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
0351     u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
0352     int ret;
0353
0354     ret = regmap_bulk_write(map, PAGE3_SET_ADD,
0355                 vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
0356
0357     if (ret < 0)
0358         dev_err(dev, "failed to %sable VDO: %d\n",
0359             ctrl == ENABLE ? "en" : "dis", ret);
0360 }
0361
0362 static int __maybe_unused ps8640_resume(struct device *dev)
0363 {
0364     struct ps8640 *ps_bridge = dev_get_drvdata(dev);
0365     int ret;
0366
0367     ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
0368                     ps_bridge->supplies);
0369     if (ret < 0) {
0370         dev_err(dev, "cannot enable regulators %d\n", ret);
0371         return ret;
0372     }
0373
0374     gpiod_set_value(ps_bridge->gpio_powerdown, 0);
0375     gpiod_set_value(ps_bridge->gpio_reset, 1);
0376     usleep_range(2000, 2500);
0377     gpiod_set_value(ps_bridge->gpio_reset, 0);
0378
0379     /*
0380      * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
0381      * this is truly necessary since the MCU will already signal that
0382      * things are "good to go" by signaling HPD on "gpio 9". See
0383      * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
0384      * just in case.
0385      */
0386     msleep(200);
0387
0388     return 0;
0389 }
0390
0391 static int __maybe_unused ps8640_suspend(struct device *dev)
0392 {
0393     struct ps8640 *ps_bridge = dev_get_drvdata(dev);
0394     int ret;
0395
0396     gpiod_set_value(ps_bridge->gpio_reset, 1);
0397     gpiod_set_value(ps_bridge->gpio_powerdown, 1);
0398     ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
0399                      ps_bridge->supplies);
0400     if (ret < 0)
0401         dev_err(dev, "cannot disable regulators %d\n", ret);
0402
0403     return ret;
0404 }
0405
0406 static const struct dev_pm_ops ps8640_pm_ops = {
0407     SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
0408     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0409                 pm_runtime_force_resume)
0410 };
0411
0412 static void ps8640_pre_enable(struct drm_bridge *bridge)
0413 {
0414     struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
0415     struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
0416     struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
0417     int ret;
0418
0419     pm_runtime_get_sync(dev);
0420     ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
0421     if (ret < 0)
0422         dev_warn(dev, "HPD didn't go high: %d\n", ret);
0423
0424     /*
0425      * The Manufacturer Command Set (MCS) is a device dependent interface
0426      * intended for factory programming of the display module default
0427      * parameters. Once the display module is configured, the MCS shall be
0428      * disabled by the manufacturer. Once disabled, all MCS commands are
0429      * ignored by the display interface.
0430      */
0431
0432     ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
0433     if (ret < 0)
0434         dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
0435
0436     /* Switch access edp panel's edid through i2c */
0437     ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
0438     if (ret < 0)
0439         dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
0440
0441     ps8640_bridge_vdo_control(ps_bridge, ENABLE);
0442
0443     ps_bridge->pre_enabled = true;
0444 }
0445
0446 static void ps8640_post_disable(struct drm_bridge *bridge)
0447 {
0448     struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
0449
0450     ps_bridge->pre_enabled = false;
0451
0452     ps8640_bridge_vdo_control(ps_bridge, DISABLE);
0453     pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
0454 }
0455
0456 static int ps8640_bridge_attach(struct drm_bridge *bridge,
0457                 enum drm_bridge_attach_flags flags)
0458 {
0459     struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
0460     struct device *dev = &ps_bridge->page[0]->dev;
0461     int ret;
0462
0463     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
0464         return -EINVAL;
0465
0466     ps_bridge->aux.drm_dev = bridge->dev;
0467     ret = drm_dp_aux_register(&ps_bridge->aux);
0468     if (ret) {
0469         dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
0470         return ret;
0471     }
0472
0473     ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
0474     if (!ps_bridge->link) {
0475         dev_err(dev, "failed to create device link");
0476         ret = -EINVAL;
0477         goto err_devlink;
0478     }
0479
0480     /* Attach the panel-bridge to the dsi bridge */
0481     ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
0482                 &ps_bridge->bridge, flags);
0483     if (ret)
0484         goto err_bridge_attach;
0485
0486     return 0;
0487
0488 err_bridge_attach:
0489     device_link_del(ps_bridge->link);
0490 err_devlink:
0491     drm_dp_aux_unregister(&ps_bridge->aux);
0492
0493     return ret;
0494 }
0495
0496 static void ps8640_bridge_detach(struct drm_bridge *bridge)
0497 {
0498     struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
0499
0500     drm_dp_aux_unregister(&ps_bridge->aux);
0501     if (ps_bridge->link)
0502         device_link_del(ps_bridge->link);
0503 }
0504
0505 static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
0506                        struct drm_connector *connector)
0507 {
0508     struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
0509     bool poweroff = !ps_bridge->pre_enabled;
0510     struct edid *edid;
0511
0512     /*
0513      * When we end calling get_edid() triggered by an ioctl, i.e
0514      *
0515      *   drm_mode_getconnector (ioctl)
0516      *     -> drm_helper_probe_single_connector_modes
0517      *        -> drm_bridge_connector_get_modes
0518      *           -> ps8640_bridge_get_edid
0519      *
0520      * We need to make sure that what we need is enabled before reading
0521      * EDID, for this chip, we need to do a full poweron, otherwise it will
0522      * fail.
0523      */
0524     drm_bridge_chain_pre_enable(bridge);
0525
0526     edid = drm_get_edid(connector,
0527                 ps_bridge->page[PAGE0_DP_CNTL]->adapter);
0528
0529     /*
0530      * If we call the get_edid() function without having enabled the chip
0531      * before, return the chip to its original power state.
0532      */
0533     if (poweroff)
0534         drm_bridge_chain_post_disable(bridge);
0535
0536     return edid;
0537 }
0538
0539 static void ps8640_runtime_disable(void *data)
0540 {
0541     pm_runtime_dont_use_autosuspend(data);
0542     pm_runtime_disable(data);
0543 }
0544
0545 static const struct drm_bridge_funcs ps8640_bridge_funcs = {
0546     .attach = ps8640_bridge_attach,
0547     .detach = ps8640_bridge_detach,
0548     .get_edid = ps8640_bridge_get_edid,
0549     .post_disable = ps8640_post_disable,
0550     .pre_enable = ps8640_pre_enable,
0551 };
0552
0553 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
0554 {
0555     struct device_node *in_ep, *dsi_node;
0556     struct mipi_dsi_device *dsi;
0557     struct mipi_dsi_host *host;
0558     const struct mipi_dsi_device_info info = { .type = "ps8640",
0559                            .channel = 0,
0560                            .node = NULL,
0561                          };
0562
0563     /* port@0 is ps8640 dsi input port */
0564     in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
0565     if (!in_ep)
0566         return -ENODEV;
0567
0568     dsi_node = of_graph_get_remote_port_parent(in_ep);
0569     of_node_put(in_ep);
0570     if (!dsi_node)
0571         return -ENODEV;
0572
0573     host = of_find_mipi_dsi_host_by_node(dsi_node);
0574     of_node_put(dsi_node);
0575     if (!host)
0576         return -EPROBE_DEFER;
0577
0578     dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
0579     if (IS_ERR(dsi)) {
0580         dev_err(dev, "failed to create dsi device\n");
0581         return PTR_ERR(dsi);
0582     }
0583
0584     ps_bridge->dsi = dsi;
0585
0586     dsi->host = host;
0587     dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
0588               MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
0589     dsi->format = MIPI_DSI_FMT_RGB888;
0590     dsi->lanes = NUM_MIPI_LANES;
0591
0592     return 0;
0593 }
0594
0595 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
0596 {
0597     struct ps8640 *ps_bridge = aux_to_ps8640(aux);
0598     struct device *dev = aux->dev;
0599     struct device_node *np = dev->of_node;
0600     int ret;
0601
0602     /*
0603      * NOTE about returning -EPROBE_DEFER from this function: if we
0604      * return an error (most relevant to -EPROBE_DEFER) it will only
0605      * be passed out to ps8640_probe() if it called this directly (AKA the
0606      * panel isn't under the "aux-bus" node). That should be fine because
0607      * if the panel is under "aux-bus" it's guaranteed to have probed by
0608      * the time this function has been called.
0609      */
0610
0611     /* port@1 is ps8640 output port */
0612     ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
0613     if (IS_ERR(ps_bridge->panel_bridge))
0614         return PTR_ERR(ps_bridge->panel_bridge);
0615
0616     ret = devm_drm_bridge_add(dev, &ps_bridge->bridge);
0617     if (ret)
0618         return ret;
0619
0620     return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
0621 }
0622
0623 static int ps8640_probe(struct i2c_client *client)
0624 {
0625     struct device *dev = &client->dev;
0626     struct ps8640 *ps_bridge;
0627     int ret;
0628     u32 i;
0629
0630     ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
0631     if (!ps_bridge)
0632         return -ENOMEM;
0633
0634     ps_bridge->supplies[0].supply = "vdd33";
0635     ps_bridge->supplies[1].supply = "vdd12";
0636     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
0637                       ps_bridge->supplies);
0638     if (ret)
0639         return ret;
0640
0641     ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
0642                            GPIOD_OUT_HIGH);
0643     if (IS_ERR(ps_bridge->gpio_powerdown))
0644         return PTR_ERR(ps_bridge->gpio_powerdown);
0645
0646     /*
0647      * Assert the reset to avoid the bridge being initialized prematurely
0648      */
0649     ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
0650                            GPIOD_OUT_HIGH);
0651     if (IS_ERR(ps_bridge->gpio_reset))
0652         return PTR_ERR(ps_bridge->gpio_reset);
0653
0654     ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
0655     ps_bridge->bridge.of_node = dev->of_node;
0656     ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
0657
0658     /*
0659      * In the device tree, if panel is listed under aux-bus of the bridge
0660      * node, panel driver should be able to retrieve EDID by itself using
0661      * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here.
0662      */
0663     if (!ps8640_of_panel_on_aux_bus(&client->dev))
0664         ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
0665
0666     /*
0667      * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
0668      * we want to get them out of the way sooner.
0669      */
0670     ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge);
0671     if (ret)
0672         return ret;
0673
0674     ps_bridge->page[PAGE0_DP_CNTL] = client;
0675
0676     ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
0677     if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
0678         return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
0679
0680     for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
0681         ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
0682                                  client->adapter,
0683                                  client->addr + i);
0684         if (IS_ERR(ps_bridge->page[i]))
0685             return PTR_ERR(ps_bridge->page[i]);
0686
0687         ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
0688                                 ps8640_regmap_config + i);
0689         if (IS_ERR(ps_bridge->regmap[i]))
0690             return PTR_ERR(ps_bridge->regmap[i]);
0691     }
0692
0693     i2c_set_clientdata(client, ps_bridge);
0694
0695     ps_bridge->aux.name = "parade-ps8640-aux";
0696     ps_bridge->aux.dev = dev;
0697     ps_bridge->aux.transfer = ps8640_aux_transfer;
0698     ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
0699     drm_dp_aux_init(&ps_bridge->aux);
0700
0701     pm_runtime_enable(dev);
0702     /*
0703      * Powering on ps8640 takes ~300ms. To avoid wasting time on power
0704      * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure
0705      * the bridge wouldn't suspend in between each _aux_transfer_msg() call
0706      * during EDID read (~20ms in my experiment) and in between the last
0707      * _aux_transfer_msg() call during EDID read and the _pre_enable() call
0708      * (~100ms in my experiment).
0709      */
0710     pm_runtime_set_autosuspend_delay(dev, 1000);
0711     pm_runtime_use_autosuspend(dev);
0712     pm_suspend_ignore_children(dev, true);
0713     ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
0714     if (ret)
0715         return ret;
0716
0717     ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel);
0718
0719     /*
0720      * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
0721      * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
0722      * the function is allowed to -EPROBE_DEFER.
0723      */
0724     if (ret == -ENODEV)
0725         return ps8640_bridge_link_panel(&ps_bridge->aux);
0726
0727     return ret;
0728 }
0729
0730 static const struct of_device_id ps8640_match[] = {
0731     { .compatible = "parade,ps8640" },
0732     { }
0733 };
0734 MODULE_DEVICE_TABLE(of, ps8640_match);
0735
0736 static struct i2c_driver ps8640_driver = {
0737     .probe_new = ps8640_probe,
0738     .driver = {
0739         .name = "ps8640",
0740         .of_match_table = ps8640_match,
0741         .pm = &ps8640_pm_ops,
0742     },
0743 };
0744 module_i2c_driver(ps8640_driver);
0745
0746 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
0747 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
0748 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
0749 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
0750 MODULE_LICENSE("GPL v2");