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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2020 BayLibre, SAS
0004  * Author: Phong LE <ple@baylibre.com>
0005  * Copyright (C) 2018-2019, Artem Mygaiev
0006  * Copyright (C) 2017, Fresco Logic, Incorporated.
0007  *
0008  */
0009 
0010 #include <linux/media-bus-format.h>
0011 #include <linux/module.h>
0012 #include <linux/device.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/i2c.h>
0015 #include <linux/bitfield.h>
0016 #include <linux/property.h>
0017 #include <linux/regmap.h>
0018 #include <linux/of_graph.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/regulator/consumer.h>
0022 
0023 #include <drm/drm_atomic_helper.h>
0024 #include <drm/drm_bridge.h>
0025 #include <drm/drm_crtc_helper.h>
0026 #include <drm/drm_edid.h>
0027 #include <drm/drm_modes.h>
0028 #include <drm/drm_print.h>
0029 #include <drm/drm_probe_helper.h>
0030 
0031 #include <sound/hdmi-codec.h>
0032 
0033 #define IT66121_VENDOR_ID0_REG          0x00
0034 #define IT66121_VENDOR_ID1_REG          0x01
0035 #define IT66121_DEVICE_ID0_REG          0x02
0036 #define IT66121_DEVICE_ID1_REG          0x03
0037 
0038 #define IT66121_VENDOR_ID0          0x54
0039 #define IT66121_VENDOR_ID1          0x49
0040 #define IT66121_DEVICE_ID0          0x12
0041 #define IT66121_DEVICE_ID1          0x06
0042 #define IT66121_REVISION_MASK           GENMASK(7, 4)
0043 #define IT66121_DEVICE_ID1_MASK         GENMASK(3, 0)
0044 
0045 #define IT66121_MASTER_SEL_REG          0x10
0046 #define IT66121_MASTER_SEL_HOST         BIT(0)
0047 
0048 #define IT66121_AFE_DRV_REG         0x61
0049 #define IT66121_AFE_DRV_RST         BIT(4)
0050 #define IT66121_AFE_DRV_PWD         BIT(5)
0051 
0052 #define IT66121_INPUT_MODE_REG          0x70
0053 #define IT66121_INPUT_MODE_RGB          (0 << 6)
0054 #define IT66121_INPUT_MODE_YUV422       BIT(6)
0055 #define IT66121_INPUT_MODE_YUV444       (2 << 6)
0056 #define IT66121_INPUT_MODE_CCIR656      BIT(4)
0057 #define IT66121_INPUT_MODE_SYNCEMB      BIT(3)
0058 #define IT66121_INPUT_MODE_DDR          BIT(2)
0059 
0060 #define IT66121_INPUT_CSC_REG           0x72
0061 #define IT66121_INPUT_CSC_ENDITHER      BIT(7)
0062 #define IT66121_INPUT_CSC_ENUDFILTER        BIT(6)
0063 #define IT66121_INPUT_CSC_DNFREE_GO     BIT(5)
0064 #define IT66121_INPUT_CSC_RGB_TO_YUV        0x02
0065 #define IT66121_INPUT_CSC_YUV_TO_RGB        0x03
0066 #define IT66121_INPUT_CSC_NO_CONV       0x00
0067 
0068 #define IT66121_AFE_XP_REG          0x62
0069 #define IT66121_AFE_XP_GAINBIT          BIT(7)
0070 #define IT66121_AFE_XP_PWDPLL           BIT(6)
0071 #define IT66121_AFE_XP_ENI          BIT(5)
0072 #define IT66121_AFE_XP_ENO          BIT(4)
0073 #define IT66121_AFE_XP_RESETB           BIT(3)
0074 #define IT66121_AFE_XP_PWDI         BIT(2)
0075 
0076 #define IT66121_AFE_IP_REG          0x64
0077 #define IT66121_AFE_IP_GAINBIT          BIT(7)
0078 #define IT66121_AFE_IP_PWDPLL           BIT(6)
0079 #define IT66121_AFE_IP_CKSEL_05         (0 << 4)
0080 #define IT66121_AFE_IP_CKSEL_1          BIT(4)
0081 #define IT66121_AFE_IP_CKSEL_2          (2 << 4)
0082 #define IT66121_AFE_IP_CKSEL_2OR4       (3 << 4)
0083 #define IT66121_AFE_IP_ER0          BIT(3)
0084 #define IT66121_AFE_IP_RESETB           BIT(2)
0085 #define IT66121_AFE_IP_ENC          BIT(1)
0086 #define IT66121_AFE_IP_EC1          BIT(0)
0087 
0088 #define IT66121_AFE_XP_EC1_REG          0x68
0089 #define IT66121_AFE_XP_EC1_LOWCLK       BIT(4)
0090 
0091 #define IT66121_SW_RST_REG          0x04
0092 #define IT66121_SW_RST_REF          BIT(5)
0093 #define IT66121_SW_RST_AREF         BIT(4)
0094 #define IT66121_SW_RST_VID          BIT(3)
0095 #define IT66121_SW_RST_AUD          BIT(2)
0096 #define IT66121_SW_RST_HDCP         BIT(0)
0097 
0098 #define IT66121_DDC_COMMAND_REG         0x15
0099 #define IT66121_DDC_COMMAND_BURST_READ      0x0
0100 #define IT66121_DDC_COMMAND_EDID_READ       0x3
0101 #define IT66121_DDC_COMMAND_FIFO_CLR        0x9
0102 #define IT66121_DDC_COMMAND_SCL_PULSE       0xA
0103 #define IT66121_DDC_COMMAND_ABORT       0xF
0104 
0105 #define IT66121_HDCP_REG            0x20
0106 #define IT66121_HDCP_CPDESIRED          BIT(0)
0107 #define IT66121_HDCP_EN1P1FEAT          BIT(1)
0108 
0109 #define IT66121_INT_STATUS1_REG         0x06
0110 #define IT66121_INT_STATUS1_AUD_OVF     BIT(7)
0111 #define IT66121_INT_STATUS1_DDC_NOACK       BIT(5)
0112 #define IT66121_INT_STATUS1_DDC_FIFOERR     BIT(4)
0113 #define IT66121_INT_STATUS1_DDC_BUSHANG     BIT(2)
0114 #define IT66121_INT_STATUS1_RX_SENS_STATUS  BIT(1)
0115 #define IT66121_INT_STATUS1_HPD_STATUS      BIT(0)
0116 
0117 #define IT66121_DDC_HEADER_REG          0x11
0118 #define IT66121_DDC_HEADER_HDCP         0x74
0119 #define IT66121_DDC_HEADER_EDID         0xA0
0120 
0121 #define IT66121_DDC_OFFSET_REG          0x12
0122 #define IT66121_DDC_BYTE_REG            0x13
0123 #define IT66121_DDC_SEGMENT_REG         0x14
0124 #define IT66121_DDC_RD_FIFO_REG         0x17
0125 
0126 #define IT66121_CLK_BANK_REG            0x0F
0127 #define IT66121_CLK_BANK_PWROFF_RCLK        BIT(6)
0128 #define IT66121_CLK_BANK_PWROFF_ACLK        BIT(5)
0129 #define IT66121_CLK_BANK_PWROFF_TXCLK       BIT(4)
0130 #define IT66121_CLK_BANK_PWROFF_CRCLK       BIT(3)
0131 #define IT66121_CLK_BANK_0          0
0132 #define IT66121_CLK_BANK_1          1
0133 
0134 #define IT66121_INT_REG             0x05
0135 #define IT66121_INT_ACTIVE_HIGH         BIT(7)
0136 #define IT66121_INT_OPEN_DRAIN          BIT(6)
0137 #define IT66121_INT_TX_CLK_OFF          BIT(0)
0138 
0139 #define IT66121_INT_MASK1_REG           0x09
0140 #define IT66121_INT_MASK1_AUD_OVF       BIT(7)
0141 #define IT66121_INT_MASK1_DDC_NOACK     BIT(5)
0142 #define IT66121_INT_MASK1_DDC_FIFOERR       BIT(4)
0143 #define IT66121_INT_MASK1_DDC_BUSHANG       BIT(2)
0144 #define IT66121_INT_MASK1_RX_SENS       BIT(1)
0145 #define IT66121_INT_MASK1_HPD           BIT(0)
0146 
0147 #define IT66121_INT_CLR1_REG            0x0C
0148 #define IT66121_INT_CLR1_PKTACP         BIT(7)
0149 #define IT66121_INT_CLR1_PKTNULL        BIT(6)
0150 #define IT66121_INT_CLR1_PKTGEN         BIT(5)
0151 #define IT66121_INT_CLR1_KSVLISTCHK     BIT(4)
0152 #define IT66121_INT_CLR1_AUTHDONE       BIT(3)
0153 #define IT66121_INT_CLR1_AUTHFAIL       BIT(2)
0154 #define IT66121_INT_CLR1_RX_SENS        BIT(1)
0155 #define IT66121_INT_CLR1_HPD            BIT(0)
0156 
0157 #define IT66121_AV_MUTE_REG         0xC1
0158 #define IT66121_AV_MUTE_ON          BIT(0)
0159 #define IT66121_AV_MUTE_BLUESCR         BIT(1)
0160 
0161 #define IT66121_PKT_CTS_CTRL_REG        0xC5
0162 #define IT66121_PKT_CTS_CTRL_SEL        BIT(1)
0163 
0164 #define IT66121_PKT_GEN_CTRL_REG        0xC6
0165 #define IT66121_PKT_GEN_CTRL_ON         BIT(0)
0166 #define IT66121_PKT_GEN_CTRL_RPT        BIT(1)
0167 
0168 #define IT66121_AVIINFO_DB1_REG         0x158
0169 #define IT66121_AVIINFO_DB2_REG         0x159
0170 #define IT66121_AVIINFO_DB3_REG         0x15A
0171 #define IT66121_AVIINFO_DB4_REG         0x15B
0172 #define IT66121_AVIINFO_DB5_REG         0x15C
0173 #define IT66121_AVIINFO_CSUM_REG        0x15D
0174 #define IT66121_AVIINFO_DB6_REG         0x15E
0175 #define IT66121_AVIINFO_DB7_REG         0x15F
0176 #define IT66121_AVIINFO_DB8_REG         0x160
0177 #define IT66121_AVIINFO_DB9_REG         0x161
0178 #define IT66121_AVIINFO_DB10_REG        0x162
0179 #define IT66121_AVIINFO_DB11_REG        0x163
0180 #define IT66121_AVIINFO_DB12_REG        0x164
0181 #define IT66121_AVIINFO_DB13_REG        0x165
0182 
0183 #define IT66121_AVI_INFO_PKT_REG        0xCD
0184 #define IT66121_AVI_INFO_PKT_ON         BIT(0)
0185 #define IT66121_AVI_INFO_PKT_RPT        BIT(1)
0186 
0187 #define IT66121_HDMI_MODE_REG           0xC0
0188 #define IT66121_HDMI_MODE_HDMI          BIT(0)
0189 
0190 #define IT66121_SYS_STATUS_REG          0x0E
0191 #define IT66121_SYS_STATUS_ACTIVE_IRQ       BIT(7)
0192 #define IT66121_SYS_STATUS_HPDETECT     BIT(6)
0193 #define IT66121_SYS_STATUS_SENDECTECT       BIT(5)
0194 #define IT66121_SYS_STATUS_VID_STABLE       BIT(4)
0195 #define IT66121_SYS_STATUS_AUD_CTS_CLR      BIT(1)
0196 #define IT66121_SYS_STATUS_CLEAR_IRQ        BIT(0)
0197 
0198 #define IT66121_DDC_STATUS_REG          0x16
0199 #define IT66121_DDC_STATUS_TX_DONE      BIT(7)
0200 #define IT66121_DDC_STATUS_ACTIVE       BIT(6)
0201 #define IT66121_DDC_STATUS_NOACK        BIT(5)
0202 #define IT66121_DDC_STATUS_WAIT_BUS     BIT(4)
0203 #define IT66121_DDC_STATUS_ARBI_LOSE        BIT(3)
0204 #define IT66121_DDC_STATUS_FIFO_FULL        BIT(2)
0205 #define IT66121_DDC_STATUS_FIFO_EMPTY       BIT(1)
0206 #define IT66121_DDC_STATUS_FIFO_VALID       BIT(0)
0207 
0208 #define IT66121_EDID_SLEEP_US           20000
0209 #define IT66121_EDID_TIMEOUT_US         200000
0210 #define IT66121_EDID_FIFO_SIZE          32
0211 
0212 #define IT66121_CLK_CTRL0_REG           0x58
0213 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING    BIT(4)
0214 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK     GENMASK(3, 2)
0215 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS    (0 << 2)
0216 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS    BIT(2)
0217 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS    (2 << 2)
0218 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS   (3 << 2)
0219 #define IT66121_CLK_CTRL0_AUTO_IPCLK        BIT(0)
0220 #define IT66121_CLK_STATUS1_REG         0x5E
0221 #define IT66121_CLK_STATUS2_REG         0x5F
0222 
0223 #define IT66121_AUD_CTRL0_REG           0xE0
0224 #define IT66121_AUD_SWL             (3 << 6)
0225 #define IT66121_AUD_16BIT           (0 << 6)
0226 #define IT66121_AUD_18BIT           BIT(6)
0227 #define IT66121_AUD_20BIT           (2 << 6)
0228 #define IT66121_AUD_24BIT           (3 << 6)
0229 #define IT66121_AUD_SPDIFTC         BIT(5)
0230 #define IT66121_AUD_SPDIF           BIT(4)
0231 #define IT66121_AUD_I2S             (0 << 4)
0232 #define IT66121_AUD_EN_I2S3         BIT(3)
0233 #define IT66121_AUD_EN_I2S2         BIT(2)
0234 #define IT66121_AUD_EN_I2S1         BIT(1)
0235 #define IT66121_AUD_EN_I2S0         BIT(0)
0236 #define IT66121_AUD_CTRL0_AUD_SEL       BIT(4)
0237 
0238 #define IT66121_AUD_CTRL1_REG           0xE1
0239 #define IT66121_AUD_FIFOMAP_REG         0xE2
0240 #define IT66121_AUD_CTRL3_REG           0xE3
0241 #define IT66121_AUD_SRCVALID_FLAT_REG       0xE4
0242 #define IT66121_AUD_FLAT_SRC0           BIT(4)
0243 #define IT66121_AUD_FLAT_SRC1           BIT(5)
0244 #define IT66121_AUD_FLAT_SRC2           BIT(6)
0245 #define IT66121_AUD_FLAT_SRC3           BIT(7)
0246 #define IT66121_AUD_HDAUDIO_REG         0xE5
0247 
0248 #define IT66121_AUD_PKT_CTS0_REG        0x130
0249 #define IT66121_AUD_PKT_CTS1_REG        0x131
0250 #define IT66121_AUD_PKT_CTS2_REG        0x132
0251 #define IT66121_AUD_PKT_N0_REG          0x133
0252 #define IT66121_AUD_PKT_N1_REG          0x134
0253 #define IT66121_AUD_PKT_N2_REG          0x135
0254 
0255 #define IT66121_AUD_CHST_MODE_REG       0x191
0256 #define IT66121_AUD_CHST_CAT_REG        0x192
0257 #define IT66121_AUD_CHST_SRCNUM_REG     0x193
0258 #define IT66121_AUD_CHST_CHTNUM_REG     0x194
0259 #define IT66121_AUD_CHST_CA_FS_REG      0x198
0260 #define IT66121_AUD_CHST_OFS_WL_REG     0x199
0261 
0262 #define IT66121_AUD_PKT_CTS_CNT0_REG        0x1A0
0263 #define IT66121_AUD_PKT_CTS_CNT1_REG        0x1A1
0264 #define IT66121_AUD_PKT_CTS_CNT2_REG        0x1A2
0265 
0266 #define IT66121_AUD_FS_22P05K           0x4
0267 #define IT66121_AUD_FS_44P1K            0x0
0268 #define IT66121_AUD_FS_88P2K            0x8
0269 #define IT66121_AUD_FS_176P4K           0xC
0270 #define IT66121_AUD_FS_24K          0x6
0271 #define IT66121_AUD_FS_48K          0x2
0272 #define IT66121_AUD_FS_96K          0xA
0273 #define IT66121_AUD_FS_192K         0xE
0274 #define IT66121_AUD_FS_768K         0x9
0275 #define IT66121_AUD_FS_32K          0x3
0276 #define IT66121_AUD_FS_OTHER            0x1
0277 
0278 #define IT66121_AUD_SWL_21BIT           0xD
0279 #define IT66121_AUD_SWL_24BIT           0xB
0280 #define IT66121_AUD_SWL_23BIT           0x9
0281 #define IT66121_AUD_SWL_22BIT           0x5
0282 #define IT66121_AUD_SWL_20BIT           0x3
0283 #define IT66121_AUD_SWL_17BIT           0xC
0284 #define IT66121_AUD_SWL_19BIT           0x8
0285 #define IT66121_AUD_SWL_18BIT           0x4
0286 #define IT66121_AUD_SWL_16BIT           0x2
0287 #define IT66121_AUD_SWL_NOT_INDICATED       0x0
0288 
0289 #define IT66121_VENDOR_ID0          0x54
0290 #define IT66121_VENDOR_ID1          0x49
0291 #define IT66121_DEVICE_ID0          0x12
0292 #define IT66121_DEVICE_ID1          0x06
0293 #define IT66121_DEVICE_MASK         0x0F
0294 #define IT66121_AFE_CLK_HIGH            80000 /* Khz */
0295 
0296 struct it66121_ctx {
0297     struct regmap *regmap;
0298     struct drm_bridge bridge;
0299     struct drm_bridge *next_bridge;
0300     struct drm_connector *connector;
0301     struct device *dev;
0302     struct gpio_desc *gpio_reset;
0303     struct i2c_client *client;
0304     struct regulator_bulk_data supplies[3];
0305     u32 bus_width;
0306     struct mutex lock; /* Protects fields below and device registers */
0307     struct hdmi_avi_infoframe hdmi_avi_infoframe;
0308     struct {
0309         struct platform_device *pdev;
0310         u8 ch_enable;
0311         u8 fs;
0312         u8 swl;
0313         bool auto_cts;
0314     } audio;
0315 };
0316 
0317 static const struct regmap_range_cfg it66121_regmap_banks[] = {
0318     {
0319         .name = "it66121",
0320         .range_min = 0x00,
0321         .range_max = 0x1FF,
0322         .selector_reg = IT66121_CLK_BANK_REG,
0323         .selector_mask = 0x1,
0324         .selector_shift = 0,
0325         .window_start = 0x00,
0326         .window_len = 0x100,
0327     },
0328 };
0329 
0330 static const struct regmap_config it66121_regmap_config = {
0331     .val_bits = 8,
0332     .reg_bits = 8,
0333     .max_register = 0x1FF,
0334     .ranges = it66121_regmap_banks,
0335     .num_ranges = ARRAY_SIZE(it66121_regmap_banks),
0336 };
0337 
0338 static void it66121_hw_reset(struct it66121_ctx *ctx)
0339 {
0340     gpiod_set_value(ctx->gpio_reset, 1);
0341     msleep(20);
0342     gpiod_set_value(ctx->gpio_reset, 0);
0343 }
0344 
0345 static inline int ite66121_power_on(struct it66121_ctx *ctx)
0346 {
0347     return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
0348 }
0349 
0350 static inline int ite66121_power_off(struct it66121_ctx *ctx)
0351 {
0352     return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
0353 }
0354 
0355 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx)
0356 {
0357     return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST);
0358 }
0359 
0360 static inline int it66121_fire_afe(struct it66121_ctx *ctx)
0361 {
0362     return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);
0363 }
0364 
0365 /* TOFIX: Handle YCbCr Input & Output */
0366 static int it66121_configure_input(struct it66121_ctx *ctx)
0367 {
0368     int ret;
0369     u8 mode = IT66121_INPUT_MODE_RGB;
0370 
0371     if (ctx->bus_width == 12)
0372         mode |= IT66121_INPUT_MODE_DDR;
0373 
0374     ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode);
0375     if (ret)
0376         return ret;
0377 
0378     return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV);
0379 }
0380 
0381 /**
0382  * it66121_configure_afe() - Configure the analog front end
0383  * @ctx: it66121_ctx object
0384  * @mode: mode to configure
0385  *
0386  * RETURNS:
0387  * zero if success, a negative error code otherwise.
0388  */
0389 static int it66121_configure_afe(struct it66121_ctx *ctx,
0390                  const struct drm_display_mode *mode)
0391 {
0392     int ret;
0393 
0394     ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG,
0395                IT66121_AFE_DRV_RST);
0396     if (ret)
0397         return ret;
0398 
0399     if (mode->clock > IT66121_AFE_CLK_HIGH) {
0400         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
0401                     IT66121_AFE_XP_GAINBIT |
0402                     IT66121_AFE_XP_ENO,
0403                     IT66121_AFE_XP_GAINBIT);
0404         if (ret)
0405             return ret;
0406 
0407         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
0408                     IT66121_AFE_IP_GAINBIT |
0409                     IT66121_AFE_IP_ER0 |
0410                     IT66121_AFE_IP_EC1,
0411                     IT66121_AFE_IP_GAINBIT);
0412         if (ret)
0413             return ret;
0414 
0415         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
0416                     IT66121_AFE_XP_EC1_LOWCLK, 0x80);
0417         if (ret)
0418             return ret;
0419     } else {
0420         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
0421                     IT66121_AFE_XP_GAINBIT |
0422                     IT66121_AFE_XP_ENO,
0423                     IT66121_AFE_XP_ENO);
0424         if (ret)
0425             return ret;
0426 
0427         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
0428                     IT66121_AFE_IP_GAINBIT |
0429                     IT66121_AFE_IP_ER0 |
0430                     IT66121_AFE_IP_EC1, IT66121_AFE_IP_ER0 |
0431                     IT66121_AFE_IP_EC1);
0432         if (ret)
0433             return ret;
0434 
0435         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
0436                     IT66121_AFE_XP_EC1_LOWCLK,
0437                     IT66121_AFE_XP_EC1_LOWCLK);
0438         if (ret)
0439             return ret;
0440     }
0441 
0442     /* Clear reset flags */
0443     ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
0444                 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);
0445     if (ret)
0446         return ret;
0447 
0448     return it66121_fire_afe(ctx);
0449 }
0450 
0451 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx)
0452 {
0453     int ret, val;
0454     u32 busy = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS |
0455            IT66121_DDC_STATUS_ARBI_LOSE;
0456 
0457     ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, true,
0458                        IT66121_EDID_SLEEP_US, IT66121_EDID_TIMEOUT_US);
0459     if (ret)
0460         return ret;
0461 
0462     if (val & busy)
0463         return -EAGAIN;
0464 
0465     return 0;
0466 }
0467 
0468 static int it66121_clear_ddc_fifo(struct it66121_ctx *ctx)
0469 {
0470     int ret;
0471 
0472     ret = it66121_preamble_ddc(ctx);
0473     if (ret)
0474         return ret;
0475 
0476     return regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
0477                 IT66121_DDC_COMMAND_FIFO_CLR);
0478 }
0479 
0480 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx)
0481 {
0482     int ret;
0483     unsigned int swreset, cpdesire;
0484 
0485     ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset);
0486     if (ret)
0487         return ret;
0488 
0489     ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire);
0490     if (ret)
0491         return ret;
0492 
0493     ret = regmap_write(ctx->regmap, IT66121_HDCP_REG,
0494                cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));
0495     if (ret)
0496         return ret;
0497 
0498     ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG,
0499                (swreset | IT66121_SW_RST_HDCP));
0500     if (ret)
0501         return ret;
0502 
0503     ret = it66121_preamble_ddc(ctx);
0504     if (ret)
0505         return ret;
0506 
0507     ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
0508                IT66121_DDC_COMMAND_ABORT);
0509     if (ret)
0510         return ret;
0511 
0512     return it66121_wait_ddc_ready(ctx);
0513 }
0514 
0515 static int it66121_get_edid_block(void *context, u8 *buf,
0516                   unsigned int block, size_t len)
0517 {
0518     struct it66121_ctx *ctx = context;
0519     unsigned int val;
0520     int remain = len;
0521     int offset = 0;
0522     int ret, cnt;
0523 
0524     offset = (block % 2) * len;
0525     block = block / 2;
0526 
0527     ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
0528     if (ret)
0529         return ret;
0530 
0531     if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
0532         ret = it66121_abort_ddc_ops(ctx);
0533         if (ret)
0534             return ret;
0535     }
0536 
0537     ret = it66121_clear_ddc_fifo(ctx);
0538     if (ret)
0539         return ret;
0540 
0541     while (remain > 0) {
0542         cnt = (remain > IT66121_EDID_FIFO_SIZE) ?
0543                 IT66121_EDID_FIFO_SIZE : remain;
0544         ret = it66121_preamble_ddc(ctx);
0545         if (ret)
0546             return ret;
0547 
0548         ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
0549                    IT66121_DDC_COMMAND_FIFO_CLR);
0550         if (ret)
0551             return ret;
0552 
0553         ret = it66121_wait_ddc_ready(ctx);
0554         if (ret)
0555             return ret;
0556 
0557         ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
0558         if (ret)
0559             return ret;
0560 
0561         if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
0562             ret = it66121_abort_ddc_ops(ctx);
0563             if (ret)
0564                 return ret;
0565         }
0566 
0567         ret = it66121_preamble_ddc(ctx);
0568         if (ret)
0569             return ret;
0570 
0571         ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG,
0572                    IT66121_DDC_HEADER_EDID);
0573         if (ret)
0574             return ret;
0575 
0576         ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset);
0577         if (ret)
0578             return ret;
0579 
0580         ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt);
0581         if (ret)
0582             return ret;
0583 
0584         ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
0585         if (ret)
0586             return ret;
0587 
0588         ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
0589                    IT66121_DDC_COMMAND_EDID_READ);
0590         if (ret)
0591             return ret;
0592 
0593         offset += cnt;
0594         remain -= cnt;
0595 
0596         /* Per programming manual, sleep here before emptying the FIFO */
0597         msleep(20);
0598 
0599         ret = it66121_wait_ddc_ready(ctx);
0600         if (ret)
0601             return ret;
0602 
0603         do {
0604             ret = regmap_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, &val);
0605             if (ret)
0606                 return ret;
0607             *(buf++) = val;
0608             cnt--;
0609         } while (cnt > 0);
0610     }
0611 
0612     return 0;
0613 }
0614 
0615 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx)
0616 {
0617     int val;
0618 
0619     if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val))
0620         return false;
0621 
0622     return val & IT66121_SYS_STATUS_HPDETECT;
0623 }
0624 
0625 static int it66121_bridge_attach(struct drm_bridge *bridge,
0626                  enum drm_bridge_attach_flags flags)
0627 {
0628     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0629     int ret;
0630 
0631     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
0632         return -EINVAL;
0633 
0634     ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags);
0635     if (ret)
0636         return ret;
0637 
0638     ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
0639                 IT66121_CLK_BANK_PWROFF_RCLK, 0);
0640     if (ret)
0641         return ret;
0642 
0643     ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG,
0644                 IT66121_INT_TX_CLK_OFF, 0);
0645     if (ret)
0646         return ret;
0647 
0648     ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
0649                 IT66121_AFE_DRV_PWD, 0);
0650     if (ret)
0651         return ret;
0652 
0653     ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
0654                 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);
0655     if (ret)
0656         return ret;
0657 
0658     ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
0659                 IT66121_AFE_IP_PWDPLL, 0);
0660     if (ret)
0661         return ret;
0662 
0663     ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
0664                 IT66121_AFE_DRV_RST, 0);
0665     if (ret)
0666         return ret;
0667 
0668     ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
0669                 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB);
0670     if (ret)
0671         return ret;
0672 
0673     ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
0674                 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB);
0675     if (ret)
0676         return ret;
0677 
0678     ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
0679                 IT66121_SW_RST_REF,
0680                 IT66121_SW_RST_REF);
0681     if (ret)
0682         return ret;
0683 
0684     /* Per programming manual, sleep here for bridge to settle */
0685     msleep(50);
0686 
0687     /* Start interrupts */
0688     return regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
0689                  IT66121_INT_MASK1_DDC_NOACK |
0690                  IT66121_INT_MASK1_DDC_FIFOERR |
0691                  IT66121_INT_MASK1_DDC_BUSHANG, 0);
0692 }
0693 
0694 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute)
0695 {
0696     int ret;
0697     unsigned int val = 0;
0698 
0699     if (mute)
0700         val = IT66121_AV_MUTE_ON;
0701 
0702     ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val);
0703     if (ret)
0704         return ret;
0705 
0706     return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG,
0707                 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT);
0708 }
0709 
0710 #define MAX_OUTPUT_SEL_FORMATS  1
0711 
0712 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
0713                               struct drm_bridge_state *bridge_state,
0714                               struct drm_crtc_state *crtc_state,
0715                               struct drm_connector_state *conn_state,
0716                               unsigned int *num_output_fmts)
0717 {
0718     u32 *output_fmts;
0719 
0720     output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
0721                   GFP_KERNEL);
0722     if (!output_fmts)
0723         return NULL;
0724 
0725     /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */
0726     output_fmts[0] =  MEDIA_BUS_FMT_RGB888_1X24;
0727     *num_output_fmts = 1;
0728 
0729     return output_fmts;
0730 }
0731 
0732 #define MAX_INPUT_SEL_FORMATS   1
0733 
0734 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
0735                              struct drm_bridge_state *bridge_state,
0736                              struct drm_crtc_state *crtc_state,
0737                              struct drm_connector_state *conn_state,
0738                              u32 output_fmt,
0739                              unsigned int *num_input_fmts)
0740 {
0741     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0742     u32 *input_fmts;
0743 
0744     *num_input_fmts = 0;
0745 
0746     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
0747                  GFP_KERNEL);
0748     if (!input_fmts)
0749         return NULL;
0750 
0751     if (ctx->bus_width == 12)
0752         /* IT66121FN Datasheet specifies Little-Endian ordering */
0753         input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
0754     else
0755         /* TOFIX support more input bus formats in 24bit width */
0756         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
0757     *num_input_fmts = 1;
0758 
0759     return input_fmts;
0760 }
0761 
0762 static void it66121_bridge_enable(struct drm_bridge *bridge,
0763                   struct drm_bridge_state *bridge_state)
0764 {
0765     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0766     struct drm_atomic_state *state = bridge_state->base.state;
0767 
0768     ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
0769 
0770     it66121_set_mute(ctx, false);
0771 }
0772 
0773 static void it66121_bridge_disable(struct drm_bridge *bridge,
0774                    struct drm_bridge_state *bridge_state)
0775 {
0776     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0777 
0778     it66121_set_mute(ctx, true);
0779 
0780     ctx->connector = NULL;
0781 }
0782 
0783 static
0784 void it66121_bridge_mode_set(struct drm_bridge *bridge,
0785                  const struct drm_display_mode *mode,
0786                  const struct drm_display_mode *adjusted_mode)
0787 {
0788     int ret, i;
0789     u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
0790     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0791     const u16 aviinfo_reg[HDMI_AVI_INFOFRAME_SIZE] = {
0792         IT66121_AVIINFO_DB1_REG,
0793         IT66121_AVIINFO_DB2_REG,
0794         IT66121_AVIINFO_DB3_REG,
0795         IT66121_AVIINFO_DB4_REG,
0796         IT66121_AVIINFO_DB5_REG,
0797         IT66121_AVIINFO_DB6_REG,
0798         IT66121_AVIINFO_DB7_REG,
0799         IT66121_AVIINFO_DB8_REG,
0800         IT66121_AVIINFO_DB9_REG,
0801         IT66121_AVIINFO_DB10_REG,
0802         IT66121_AVIINFO_DB11_REG,
0803         IT66121_AVIINFO_DB12_REG,
0804         IT66121_AVIINFO_DB13_REG
0805     };
0806 
0807     mutex_lock(&ctx->lock);
0808 
0809     hdmi_avi_infoframe_init(&ctx->hdmi_avi_infoframe);
0810 
0811     ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector,
0812                                adjusted_mode);
0813     if (ret) {
0814         DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret);
0815         goto unlock;
0816     }
0817 
0818     ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf));
0819     if (ret < 0) {
0820         DRM_ERROR("Failed to pack infoframe: %d\n", ret);
0821         goto unlock;
0822     }
0823 
0824     /* Write new AVI infoframe packet */
0825     for (i = 0; i < HDMI_AVI_INFOFRAME_SIZE; i++) {
0826         if (regmap_write(ctx->regmap, aviinfo_reg[i], buf[i + HDMI_INFOFRAME_HEADER_SIZE]))
0827             goto unlock;
0828     }
0829     if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3]))
0830         goto unlock;
0831 
0832     /* Enable AVI infoframe */
0833     if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG,
0834              IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT))
0835         goto unlock;
0836 
0837     /* Set TX mode to HDMI */
0838     if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI))
0839         goto unlock;
0840 
0841     if (regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
0842                   IT66121_CLK_BANK_PWROFF_TXCLK, IT66121_CLK_BANK_PWROFF_TXCLK))
0843         goto unlock;
0844 
0845     if (it66121_configure_input(ctx))
0846         goto unlock;
0847 
0848     if (it66121_configure_afe(ctx, adjusted_mode))
0849         goto unlock;
0850 
0851     regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, IT66121_CLK_BANK_PWROFF_TXCLK, 0);
0852 
0853 unlock:
0854     mutex_unlock(&ctx->lock);
0855 }
0856 
0857 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge,
0858                               const struct drm_display_info *info,
0859                               const struct drm_display_mode *mode)
0860 {
0861     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0862     unsigned long max_clock;
0863 
0864     max_clock = (ctx->bus_width == 12) ? 74250 : 148500;
0865 
0866     if (mode->clock > max_clock)
0867         return MODE_CLOCK_HIGH;
0868 
0869     if (mode->clock < 25000)
0870         return MODE_CLOCK_LOW;
0871 
0872     return MODE_OK;
0873 }
0874 
0875 static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge)
0876 {
0877     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0878 
0879     return it66121_is_hpd_detect(ctx) ? connector_status_connected
0880                       : connector_status_disconnected;
0881 }
0882 
0883 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge)
0884 {
0885     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0886     int ret;
0887 
0888     ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);
0889     if (ret)
0890         dev_err(ctx->dev, "failed to enable HPD IRQ\n");
0891 }
0892 
0893 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge)
0894 {
0895     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0896     int ret;
0897 
0898     ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
0899                 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD);
0900     if (ret)
0901         dev_err(ctx->dev, "failed to disable HPD IRQ\n");
0902 }
0903 
0904 static struct edid *it66121_bridge_get_edid(struct drm_bridge *bridge,
0905                         struct drm_connector *connector)
0906 {
0907     struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
0908     struct edid *edid;
0909 
0910     mutex_lock(&ctx->lock);
0911     edid = drm_do_get_edid(connector, it66121_get_edid_block, ctx);
0912     mutex_unlock(&ctx->lock);
0913 
0914     return edid;
0915 }
0916 
0917 static const struct drm_bridge_funcs it66121_bridge_funcs = {
0918     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0919     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
0920     .atomic_reset = drm_atomic_helper_bridge_reset,
0921     .attach = it66121_bridge_attach,
0922     .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts,
0923     .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts,
0924     .atomic_enable = it66121_bridge_enable,
0925     .atomic_disable = it66121_bridge_disable,
0926     .mode_set = it66121_bridge_mode_set,
0927     .mode_valid = it66121_bridge_mode_valid,
0928     .detect = it66121_bridge_detect,
0929     .get_edid = it66121_bridge_get_edid,
0930     .hpd_enable = it66121_bridge_hpd_enable,
0931     .hpd_disable = it66121_bridge_hpd_disable,
0932 };
0933 
0934 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id)
0935 {
0936     int ret;
0937     unsigned int val;
0938     struct it66121_ctx *ctx = dev_id;
0939     struct device *dev = ctx->dev;
0940     enum drm_connector_status status;
0941     bool event = false;
0942 
0943     mutex_lock(&ctx->lock);
0944 
0945     ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val);
0946     if (ret)
0947         goto unlock;
0948 
0949     if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ))
0950         goto unlock;
0951 
0952     ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
0953     if (ret) {
0954         dev_err(dev, "Cannot read STATUS1_REG %d\n", ret);
0955     } else {
0956         if (val & IT66121_INT_STATUS1_DDC_FIFOERR)
0957             it66121_clear_ddc_fifo(ctx);
0958         if (val & (IT66121_INT_STATUS1_DDC_BUSHANG |
0959                IT66121_INT_STATUS1_DDC_NOACK))
0960             it66121_abort_ddc_ops(ctx);
0961         if (val & IT66121_INT_STATUS1_HPD_STATUS) {
0962             regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG,
0963                       IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD);
0964 
0965             status = it66121_is_hpd_detect(ctx) ? connector_status_connected
0966                                 : connector_status_disconnected;
0967 
0968             event = true;
0969         }
0970     }
0971 
0972     regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG,
0973               IT66121_SYS_STATUS_CLEAR_IRQ,
0974               IT66121_SYS_STATUS_CLEAR_IRQ);
0975 
0976 unlock:
0977     mutex_unlock(&ctx->lock);
0978 
0979     if (event)
0980         drm_bridge_hpd_notify(&ctx->bridge, status);
0981 
0982     return IRQ_HANDLED;
0983 }
0984 
0985 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[])
0986 {
0987     int ret;
0988 
0989     ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C);
0990     if (ret)
0991         return ret;
0992 
0993     ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]);
0994     if (ret)
0995         return ret;
0996 
0997     ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F);
0998     if (ret)
0999         return ret;
1000 
1001     ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG,
1002                (iec60958_chstat[2] >> 4) & 0x0F);
1003     if (ret)
1004         return ret;
1005 
1006     ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]);
1007     if (ret)
1008         return ret;
1009 
1010     return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]);
1011 }
1012 
1013 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl)
1014 {
1015     int ret;
1016     unsigned int audio_enable = 0;
1017     unsigned int audio_format = 0;
1018 
1019     switch (audio_swl) {
1020     case 16:
1021         audio_enable |= IT66121_AUD_16BIT;
1022         break;
1023     case 18:
1024         audio_enable |= IT66121_AUD_18BIT;
1025         break;
1026     case 20:
1027         audio_enable |= IT66121_AUD_20BIT;
1028         break;
1029     case 24:
1030     default:
1031         audio_enable |= IT66121_AUD_24BIT;
1032         break;
1033     }
1034 
1035     audio_format |= 0x40;
1036     switch (audio_src_num) {
1037     case 4:
1038         audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1039                 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1040         break;
1041     case 3:
1042         audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 |
1043                 IT66121_AUD_EN_I2S0;
1044         break;
1045     case 2:
1046         audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1047         break;
1048     case 1:
1049     default:
1050         audio_format &= ~0x40;
1051         audio_enable |= IT66121_AUD_EN_I2S0;
1052         break;
1053     }
1054 
1055     audio_format |= 0x01;
1056     ctx->audio.ch_enable = audio_enable;
1057 
1058     ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0);
1059     if (ret)
1060         return ret;
1061 
1062     ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format);
1063     if (ret)
1064         return ret;
1065 
1066     ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4);
1067     if (ret)
1068         return ret;
1069 
1070     ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00);
1071     if (ret)
1072         return ret;
1073 
1074     ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00);
1075     if (ret)
1076         return ret;
1077 
1078     return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00);
1079 }
1080 
1081 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs)
1082 {
1083     int ret;
1084     unsigned int n;
1085 
1086     switch (fs) {
1087     case IT66121_AUD_FS_32K:
1088         n = 4096;
1089         break;
1090     case IT66121_AUD_FS_44P1K:
1091         n = 6272;
1092         break;
1093     case IT66121_AUD_FS_48K:
1094         n = 6144;
1095         break;
1096     case IT66121_AUD_FS_88P2K:
1097         n = 12544;
1098         break;
1099     case IT66121_AUD_FS_96K:
1100         n = 12288;
1101         break;
1102     case IT66121_AUD_FS_176P4K:
1103         n = 25088;
1104         break;
1105     case IT66121_AUD_FS_192K:
1106         n = 24576;
1107         break;
1108     case IT66121_AUD_FS_768K:
1109         n = 24576;
1110         break;
1111     default:
1112         n = 6144;
1113         break;
1114     }
1115 
1116     ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF));
1117     if (ret)
1118         return ret;
1119 
1120     ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF));
1121     if (ret)
1122         return ret;
1123 
1124     ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF));
1125     if (ret)
1126         return ret;
1127 
1128     if (ctx->audio.auto_cts) {
1129         u8 loop_cnt = 255;
1130         u8 cts_stable_cnt = 0;
1131         unsigned int sum_cts = 0;
1132         unsigned int cts = 0;
1133         unsigned int last_cts = 0;
1134         unsigned int diff;
1135         unsigned int val;
1136 
1137         while (loop_cnt--) {
1138             msleep(30);
1139             regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val);
1140             cts = val << 12;
1141             regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val);
1142             cts |= val << 4;
1143             regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val);
1144             cts |= val >> 4;
1145             if (cts == 0) {
1146                 continue;
1147             } else {
1148                 if (last_cts > cts)
1149                     diff = last_cts - cts;
1150                 else
1151                     diff = cts - last_cts;
1152                 last_cts = cts;
1153                 if (diff < 5) {
1154                     cts_stable_cnt++;
1155                     sum_cts += cts;
1156                 } else {
1157                     cts_stable_cnt = 0;
1158                     sum_cts = 0;
1159                     continue;
1160                 }
1161 
1162                 if (cts_stable_cnt >= 32) {
1163                     last_cts = (sum_cts >> 5);
1164                     break;
1165                 }
1166             }
1167         }
1168 
1169         regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF));
1170         regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF));
1171         regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F));
1172     }
1173 
1174     ret = regmap_write(ctx->regmap, 0xF8, 0xC3);
1175     if (ret)
1176         return ret;
1177 
1178     ret = regmap_write(ctx->regmap, 0xF8, 0xA5);
1179     if (ret)
1180         return ret;
1181 
1182     if (ctx->audio.auto_cts) {
1183         ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1184                     IT66121_PKT_CTS_CTRL_SEL,
1185                     1);
1186     } else {
1187         ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1188                     IT66121_PKT_CTS_CTRL_SEL,
1189                     0);
1190     }
1191 
1192     if (ret)
1193         return ret;
1194 
1195     return regmap_write(ctx->regmap, 0xF8, 0xFF);
1196 }
1197 
1198 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable)
1199 {
1200     int ret;
1201 
1202     if (enable) {
1203         ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1204                     IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1205                     0);
1206         if (ret)
1207             return ret;
1208 
1209         ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1210                     IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1211                     IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1212                     ctx->audio.ch_enable);
1213     } else {
1214         ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1215                     IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1216                     IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1217                     ctx->audio.ch_enable & 0xF0);
1218         if (ret)
1219             return ret;
1220 
1221         ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1222                     IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1223                     IT66121_SW_RST_AUD | IT66121_SW_RST_AREF);
1224     }
1225 
1226     return ret;
1227 }
1228 
1229 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable)
1230 {
1231     int ret;
1232 
1233     if (enable) {
1234         ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0);
1235         if (ret)
1236             return ret;
1237 
1238         ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable);
1239     } else {
1240         ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0);
1241     }
1242 
1243     return ret;
1244 }
1245 
1246 static int it66121_audio_hw_params(struct device *dev, void *data,
1247                    struct hdmi_codec_daifmt *daifmt,
1248                    struct hdmi_codec_params *params)
1249 {
1250     u8 fs;
1251     u8 swl;
1252     int ret;
1253     struct it66121_ctx *ctx = dev_get_drvdata(dev);
1254     static u8 iec60958_chstat[5];
1255     unsigned int channels = params->channels;
1256     unsigned int sample_rate = params->sample_rate;
1257     unsigned int sample_width = params->sample_width;
1258 
1259     mutex_lock(&ctx->lock);
1260     dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__,
1261         daifmt->fmt, sample_rate, sample_width, channels);
1262 
1263     switch (daifmt->fmt) {
1264     case HDMI_I2S:
1265         dev_dbg(dev, "Using HDMI I2S\n");
1266         break;
1267     default:
1268         dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt);
1269         ret = -EINVAL;
1270         goto out;
1271     }
1272 
1273     // Set audio clock recovery (N/CTS)
1274     ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG,
1275                IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING |
1276                IT66121_CLK_CTRL0_EXT_MCLK_256FS |
1277                IT66121_CLK_CTRL0_AUTO_IPCLK);
1278     if (ret)
1279         goto out;
1280 
1281     ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1282                 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection
1283     if (ret)
1284         goto out;
1285 
1286     switch (sample_rate) {
1287     case 44100L:
1288         fs = IT66121_AUD_FS_44P1K;
1289         break;
1290     case 88200L:
1291         fs = IT66121_AUD_FS_88P2K;
1292         break;
1293     case 176400L:
1294         fs = IT66121_AUD_FS_176P4K;
1295         break;
1296     case 32000L:
1297         fs = IT66121_AUD_FS_32K;
1298         break;
1299     case 48000L:
1300         fs = IT66121_AUD_FS_48K;
1301         break;
1302     case 96000L:
1303         fs = IT66121_AUD_FS_96K;
1304         break;
1305     case 192000L:
1306         fs = IT66121_AUD_FS_192K;
1307         break;
1308     case 768000L:
1309         fs = IT66121_AUD_FS_768K;
1310         break;
1311     default:
1312         fs = IT66121_AUD_FS_48K;
1313         break;
1314     }
1315 
1316     ctx->audio.fs = fs;
1317     ret = it661221_set_ncts(ctx, fs);
1318     if (ret) {
1319         dev_err(dev, "Failed to set N/CTS: %d\n", ret);
1320         goto out;
1321     }
1322 
1323     // Set audio format register (except audio channel enable)
1324     ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width);
1325     if (ret) {
1326         dev_err(dev, "Failed to set LPCM audio: %d\n", ret);
1327         goto out;
1328     }
1329 
1330     // Set audio channel status
1331     iec60958_chstat[0] = 0;
1332     if ((channels + 1) / 2 == 1)
1333         iec60958_chstat[0] |= 0x1;
1334     iec60958_chstat[0] &= ~(1 << 1);
1335     iec60958_chstat[1] = 0;
1336     iec60958_chstat[2] = (channels + 1) / 2;
1337     iec60958_chstat[2] |= (channels << 4) & 0xF0;
1338     iec60958_chstat[3] = fs;
1339 
1340     switch (sample_width) {
1341     case 21L:
1342         swl = IT66121_AUD_SWL_21BIT;
1343         break;
1344     case 24L:
1345         swl = IT66121_AUD_SWL_24BIT;
1346         break;
1347     case 23L:
1348         swl = IT66121_AUD_SWL_23BIT;
1349         break;
1350     case 22L:
1351         swl = IT66121_AUD_SWL_22BIT;
1352         break;
1353     case 20L:
1354         swl = IT66121_AUD_SWL_20BIT;
1355         break;
1356     case 17L:
1357         swl = IT66121_AUD_SWL_17BIT;
1358         break;
1359     case 19L:
1360         swl = IT66121_AUD_SWL_19BIT;
1361         break;
1362     case 18L:
1363         swl = IT66121_AUD_SWL_18BIT;
1364         break;
1365     case 16L:
1366         swl = IT66121_AUD_SWL_16BIT;
1367         break;
1368     default:
1369         swl = IT66121_AUD_SWL_NOT_INDICATED;
1370         break;
1371     }
1372 
1373     iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl;
1374     ret = it661221_set_chstat(ctx, iec60958_chstat);
1375     if (ret) {
1376         dev_err(dev, "Failed to set channel status: %d\n", ret);
1377         goto out;
1378     }
1379 
1380     // Enable audio channel enable while input clock stable (if SPDIF).
1381     ret = it661221_audio_ch_enable(ctx, true);
1382     if (ret) {
1383         dev_err(dev, "Failed to enable audio channel: %d\n", ret);
1384         goto out;
1385     }
1386 
1387     ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
1388                 IT66121_INT_MASK1_AUD_OVF,
1389                 0);
1390     if (ret)
1391         goto out;
1392 
1393     dev_dbg(dev, "HDMI audio enabled.\n");
1394 out:
1395     mutex_unlock(&ctx->lock);
1396 
1397     return ret;
1398 }
1399 
1400 static int it66121_audio_startup(struct device *dev, void *data)
1401 {
1402     int ret;
1403     struct it66121_ctx *ctx = dev_get_drvdata(dev);
1404 
1405     dev_dbg(dev, "%s\n", __func__);
1406 
1407     mutex_lock(&ctx->lock);
1408     ret = it661221_audio_output_enable(ctx, true);
1409     if (ret)
1410         dev_err(dev, "Failed to enable audio output: %d\n", ret);
1411 
1412     mutex_unlock(&ctx->lock);
1413 
1414     return ret;
1415 }
1416 
1417 static void it66121_audio_shutdown(struct device *dev, void *data)
1418 {
1419     int ret;
1420     struct it66121_ctx *ctx = dev_get_drvdata(dev);
1421 
1422     dev_dbg(dev, "%s\n", __func__);
1423 
1424     mutex_lock(&ctx->lock);
1425     ret = it661221_audio_output_enable(ctx, false);
1426     if (ret)
1427         dev_err(dev, "Failed to disable audio output: %d\n", ret);
1428 
1429     mutex_unlock(&ctx->lock);
1430 }
1431 
1432 static int it66121_audio_mute(struct device *dev, void *data,
1433                   bool enable, int direction)
1434 {
1435     int ret;
1436     struct it66121_ctx *ctx = dev_get_drvdata(dev);
1437 
1438     dev_dbg(dev, "%s: enable=%s, direction=%d\n",
1439         __func__, enable ? "true" : "false", direction);
1440 
1441     mutex_lock(&ctx->lock);
1442 
1443     if (enable) {
1444         ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1445                     IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1446                     IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1447                     IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1448                     IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3);
1449     } else {
1450         ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1451                     IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1452                     IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1453                     0);
1454     }
1455 
1456     mutex_unlock(&ctx->lock);
1457 
1458     return ret;
1459 }
1460 
1461 static int it66121_audio_get_eld(struct device *dev, void *data,
1462                  u8 *buf, size_t len)
1463 {
1464     struct it66121_ctx *ctx = dev_get_drvdata(dev);
1465 
1466     mutex_lock(&ctx->lock);
1467 
1468     memcpy(buf, ctx->connector->eld,
1469            min(sizeof(ctx->connector->eld), len));
1470 
1471     mutex_unlock(&ctx->lock);
1472 
1473     return 0;
1474 }
1475 
1476 static const struct hdmi_codec_ops it66121_audio_codec_ops = {
1477     .hw_params = it66121_audio_hw_params,
1478     .audio_startup = it66121_audio_startup,
1479     .audio_shutdown = it66121_audio_shutdown,
1480     .mute_stream = it66121_audio_mute,
1481     .get_eld = it66121_audio_get_eld,
1482     .no_capture_mute = 1,
1483 };
1484 
1485 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev)
1486 {
1487     struct hdmi_codec_pdata codec_data = {
1488         .ops = &it66121_audio_codec_ops,
1489         .i2s = 1, /* Only i2s support for now */
1490         .spdif = 0,
1491         .max_i2s_channels = 8,
1492     };
1493 
1494     dev_dbg(dev, "%s\n", __func__);
1495 
1496     if (!of_property_read_bool(dev->of_node, "#sound-dai-cells")) {
1497         dev_info(dev, "No \"#sound-dai-cells\", no audio\n");
1498         return 0;
1499     }
1500 
1501     ctx->audio.pdev = platform_device_register_data(dev,
1502                             HDMI_CODEC_DRV_NAME,
1503                             PLATFORM_DEVID_AUTO,
1504                             &codec_data,
1505                             sizeof(codec_data));
1506 
1507     if (IS_ERR(ctx->audio.pdev)) {
1508         dev_err(dev, "Failed to initialize HDMI audio codec: %d\n",
1509             PTR_ERR_OR_ZERO(ctx->audio.pdev));
1510     }
1511 
1512     return PTR_ERR_OR_ZERO(ctx->audio.pdev);
1513 }
1514 
1515 static int it66121_probe(struct i2c_client *client,
1516              const struct i2c_device_id *id)
1517 {
1518     u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 };
1519     struct device_node *ep;
1520     int ret;
1521     struct it66121_ctx *ctx;
1522     struct device *dev = &client->dev;
1523 
1524     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1525         dev_err(dev, "I2C check functionality failed.\n");
1526         return -ENXIO;
1527     }
1528 
1529     ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1530     if (!ctx)
1531         return -ENOMEM;
1532 
1533     ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
1534     if (!ep)
1535         return -EINVAL;
1536 
1537     ctx->dev = dev;
1538     ctx->client = client;
1539 
1540     of_property_read_u32(ep, "bus-width", &ctx->bus_width);
1541     of_node_put(ep);
1542 
1543     if (ctx->bus_width != 12 && ctx->bus_width != 24)
1544         return -EINVAL;
1545 
1546     ep = of_graph_get_remote_node(dev->of_node, 1, -1);
1547     if (!ep) {
1548         dev_err(ctx->dev, "The endpoint is unconnected\n");
1549         return -EINVAL;
1550     }
1551 
1552     if (!of_device_is_available(ep)) {
1553         of_node_put(ep);
1554         dev_err(ctx->dev, "The remote device is disabled\n");
1555         return -ENODEV;
1556     }
1557 
1558     ctx->next_bridge = of_drm_find_bridge(ep);
1559     of_node_put(ep);
1560     if (!ctx->next_bridge) {
1561         dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n");
1562         return -EPROBE_DEFER;
1563     }
1564 
1565     i2c_set_clientdata(client, ctx);
1566     mutex_init(&ctx->lock);
1567 
1568     ctx->supplies[0].supply = "vcn33";
1569     ctx->supplies[1].supply = "vcn18";
1570     ctx->supplies[2].supply = "vrf12";
1571     ret = devm_regulator_bulk_get(ctx->dev, 3, ctx->supplies);
1572     if (ret) {
1573         dev_err(ctx->dev, "regulator_bulk failed\n");
1574         return ret;
1575     }
1576 
1577     ret = ite66121_power_on(ctx);
1578     if (ret)
1579         return ret;
1580 
1581     it66121_hw_reset(ctx);
1582 
1583     ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config);
1584     if (IS_ERR(ctx->regmap)) {
1585         ite66121_power_off(ctx);
1586         return PTR_ERR(ctx->regmap);
1587     }
1588 
1589     regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);
1590     regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]);
1591     regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);
1592     regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]);
1593 
1594     /* Revision is shared with DEVICE_ID1 */
1595     revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]);
1596     device_ids[1] &= IT66121_DEVICE_ID1_MASK;
1597 
1598     if (vendor_ids[0] != IT66121_VENDOR_ID0 || vendor_ids[1] != IT66121_VENDOR_ID1 ||
1599         device_ids[0] != IT66121_DEVICE_ID0 || device_ids[1] != IT66121_DEVICE_ID1) {
1600         ite66121_power_off(ctx);
1601         return -ENODEV;
1602     }
1603 
1604     ctx->bridge.funcs = &it66121_bridge_funcs;
1605     ctx->bridge.of_node = dev->of_node;
1606     ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1607     ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
1608 
1609     ret = devm_request_threaded_irq(dev, client->irq, NULL, it66121_irq_threaded_handler,
1610                     IRQF_ONESHOT, dev_name(dev), ctx);
1611     if (ret < 0) {
1612         dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret);
1613         ite66121_power_off(ctx);
1614         return ret;
1615     }
1616 
1617     it66121_audio_codec_init(ctx, dev);
1618 
1619     drm_bridge_add(&ctx->bridge);
1620 
1621     dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id);
1622 
1623     return 0;
1624 }
1625 
1626 static int it66121_remove(struct i2c_client *client)
1627 {
1628     struct it66121_ctx *ctx = i2c_get_clientdata(client);
1629 
1630     ite66121_power_off(ctx);
1631     drm_bridge_remove(&ctx->bridge);
1632     mutex_destroy(&ctx->lock);
1633 
1634     return 0;
1635 }
1636 
1637 static const struct of_device_id it66121_dt_match[] = {
1638     { .compatible = "ite,it66121" },
1639     { }
1640 };
1641 MODULE_DEVICE_TABLE(of, it66121_dt_match);
1642 
1643 static const struct i2c_device_id it66121_id[] = {
1644     { "it66121", 0 },
1645     { }
1646 };
1647 MODULE_DEVICE_TABLE(i2c, it66121_id);
1648 
1649 static struct i2c_driver it66121_driver = {
1650     .driver = {
1651         .name   = "it66121",
1652         .of_match_table = it66121_dt_match,
1653     },
1654     .probe = it66121_probe,
1655     .remove = it66121_remove,
1656     .id_table = it66121_id,
1657 };
1658 
1659 module_i2c_driver(it66121_driver);
1660 
1661 MODULE_AUTHOR("Phong LE");
1662 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver");
1663 MODULE_LICENSE("GPL v2");
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