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0001 // SPDX-License-Identifier: GPL-2.0+
0002 
0003 /*
0004  * Copyright 2020 NXP
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/media-bus-format.h>
0009 #include <linux/mfd/syscon.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_graph.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regmap.h>
0017 
0018 #include <drm/drm_atomic_state_helper.h>
0019 #include <drm/drm_bridge.h>
0020 #include <drm/drm_connector.h>
0021 #include <drm/drm_fourcc.h>
0022 #include <drm/drm_of.h>
0023 #include <drm/drm_print.h>
0024 
0025 #include "imx-ldb-helper.h"
0026 
0027 #define  LDB_CH_SEL     BIT(28)
0028 
0029 #define SS_CTRL         0x20
0030 #define  CH_HSYNC_M(id)     BIT(0 + ((id) * 2))
0031 #define  CH_VSYNC_M(id)     BIT(1 + ((id) * 2))
0032 #define  CH_PHSYNC(id)      BIT(0 + ((id) * 2))
0033 #define  CH_PVSYNC(id)      BIT(1 + ((id) * 2))
0034 
0035 #define DRIVER_NAME     "imx8qxp-ldb"
0036 
0037 struct imx8qxp_ldb_channel {
0038     struct ldb_channel base;
0039     struct phy *phy;
0040     unsigned int di_id;
0041 };
0042 
0043 struct imx8qxp_ldb {
0044     struct ldb base;
0045     struct device *dev;
0046     struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM];
0047     struct clk *clk_pixel;
0048     struct clk *clk_bypass;
0049     struct drm_bridge *companion;
0050     int active_chno;
0051 };
0052 
0053 static inline struct imx8qxp_ldb_channel *
0054 base_to_imx8qxp_ldb_channel(struct ldb_channel *base)
0055 {
0056     return container_of(base, struct imx8qxp_ldb_channel, base);
0057 }
0058 
0059 static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base)
0060 {
0061     return container_of(base, struct imx8qxp_ldb, base);
0062 }
0063 
0064 static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,
0065                     unsigned long di_clk, bool is_split,
0066                     struct phy_configure_opts_lvds *phy_cfg)
0067 {
0068     phy_cfg->bits_per_lane_and_dclk_cycle = 7;
0069     phy_cfg->lanes = 4;
0070 
0071     if (is_split) {
0072         phy_cfg->differential_clk_rate = di_clk / 2;
0073         phy_cfg->is_slave = !imx8qxp_ldb->companion;
0074     } else {
0075         phy_cfg->differential_clk_rate = di_clk;
0076         phy_cfg->is_slave = false;
0077     }
0078 }
0079 
0080 static int
0081 imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,
0082                 struct drm_bridge_state *bridge_state,
0083                 struct drm_crtc_state *crtc_state,
0084                 struct drm_connector_state *conn_state)
0085 {
0086     struct ldb_channel *ldb_ch = bridge->driver_private;
0087     struct ldb *ldb = ldb_ch->ldb;
0088     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
0089                     base_to_imx8qxp_ldb_channel(ldb_ch);
0090     struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
0091     struct drm_bridge *companion = imx8qxp_ldb->companion;
0092     struct drm_display_mode *adj = &crtc_state->adjusted_mode;
0093     unsigned long di_clk = adj->clock * 1000;
0094     bool is_split = ldb_channel_is_split_link(ldb_ch);
0095     union phy_configure_opts opts = { };
0096     struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
0097     int ret;
0098 
0099     ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
0100                          crtc_state, conn_state);
0101     if (ret)
0102         return ret;
0103 
0104     imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
0105     ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
0106     if (ret < 0) {
0107         DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev,
0108                      "failed to validate PHY: %d\n", ret);
0109         return ret;
0110     }
0111 
0112     if (is_split && companion) {
0113         ret = companion->funcs->atomic_check(companion,
0114                     bridge_state, crtc_state, conn_state);
0115         if (ret)
0116             return ret;
0117     }
0118 
0119     return ret;
0120 }
0121 
0122 static void
0123 imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge,
0124                 const struct drm_display_mode *mode,
0125                 const struct drm_display_mode *adjusted_mode)
0126 {
0127     struct ldb_channel *ldb_ch = bridge->driver_private;
0128     struct ldb_channel *companion_ldb_ch;
0129     struct ldb *ldb = ldb_ch->ldb;
0130     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
0131                     base_to_imx8qxp_ldb_channel(ldb_ch);
0132     struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
0133     struct drm_bridge *companion = imx8qxp_ldb->companion;
0134     struct device *dev = imx8qxp_ldb->dev;
0135     unsigned long di_clk = adjusted_mode->clock * 1000;
0136     bool is_split = ldb_channel_is_split_link(ldb_ch);
0137     union phy_configure_opts opts = { };
0138     struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
0139     u32 chno = ldb_ch->chno;
0140     int ret;
0141 
0142     ret = pm_runtime_get_sync(dev);
0143     if (ret < 0)
0144         DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
0145 
0146     ret = phy_init(imx8qxp_ldb_ch->phy);
0147     if (ret < 0)
0148         DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
0149 
0150     ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS);
0151     if (ret < 0)
0152         DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret);
0153 
0154     if (is_split && companion) {
0155         companion_ldb_ch = bridge_to_ldb_ch(companion);
0156 
0157         companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format;
0158         companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format;
0159     }
0160 
0161     clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk);
0162     clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk);
0163 
0164     imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg);
0165     ret = phy_configure(imx8qxp_ldb_ch->phy, &opts);
0166     if (ret < 0)
0167         DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
0168 
0169     if (chno == 0)
0170         ldb->ldb_ctrl &= ~LDB_CH_SEL;
0171     else
0172         ldb->ldb_ctrl |= LDB_CH_SEL;
0173 
0174     /* input VSYNC signal from pixel link is active low */
0175     if (imx8qxp_ldb_ch->di_id == 0)
0176         ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
0177     else
0178         ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
0179 
0180     /*
0181      * For split mode, settle input VSYNC signal polarity and
0182      * channel selection down early.
0183      */
0184     if (is_split)
0185         regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
0186 
0187     ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
0188 
0189     if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
0190         regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
0191     else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0192         regmap_update_bits(ldb->regmap, SS_CTRL,
0193                    CH_VSYNC_M(chno), CH_PVSYNC(chno));
0194 
0195     if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
0196         regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
0197     else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0198         regmap_update_bits(ldb->regmap, SS_CTRL,
0199                    CH_HSYNC_M(chno), CH_PHSYNC(chno));
0200 
0201     if (is_split && companion)
0202         companion->funcs->mode_set(companion, mode, adjusted_mode);
0203 }
0204 
0205 static void
0206 imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge,
0207                      struct drm_bridge_state *old_bridge_state)
0208 {
0209     struct ldb_channel *ldb_ch = bridge->driver_private;
0210     struct ldb *ldb = ldb_ch->ldb;
0211     struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
0212     struct drm_bridge *companion = imx8qxp_ldb->companion;
0213     bool is_split = ldb_channel_is_split_link(ldb_ch);
0214 
0215     clk_prepare_enable(imx8qxp_ldb->clk_pixel);
0216     clk_prepare_enable(imx8qxp_ldb->clk_bypass);
0217 
0218     if (is_split && companion)
0219         companion->funcs->atomic_pre_enable(companion, old_bridge_state);
0220 }
0221 
0222 static void
0223 imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
0224                  struct drm_bridge_state *old_bridge_state)
0225 {
0226     struct ldb_channel *ldb_ch = bridge->driver_private;
0227     struct ldb *ldb = ldb_ch->ldb;
0228     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
0229                     base_to_imx8qxp_ldb_channel(ldb_ch);
0230     struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
0231     struct drm_bridge *companion = imx8qxp_ldb->companion;
0232     struct device *dev = imx8qxp_ldb->dev;
0233     bool is_split = ldb_channel_is_split_link(ldb_ch);
0234     int ret;
0235 
0236     if (ldb_ch->chno == 0 || is_split) {
0237         ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
0238         ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
0239                 LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1;
0240     }
0241     if (ldb_ch->chno == 1 || is_split) {
0242         ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
0243         ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ?
0244                 LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1;
0245     }
0246 
0247     ldb_bridge_enable_helper(bridge);
0248 
0249     ret = phy_power_on(imx8qxp_ldb_ch->phy);
0250     if (ret)
0251         DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
0252 
0253     if (is_split && companion)
0254         companion->funcs->atomic_enable(companion, old_bridge_state);
0255 }
0256 
0257 static void
0258 imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
0259                   struct drm_bridge_state *old_bridge_state)
0260 {
0261     struct ldb_channel *ldb_ch = bridge->driver_private;
0262     struct ldb *ldb = ldb_ch->ldb;
0263     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
0264                     base_to_imx8qxp_ldb_channel(ldb_ch);
0265     struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb);
0266     struct drm_bridge *companion = imx8qxp_ldb->companion;
0267     struct device *dev = imx8qxp_ldb->dev;
0268     bool is_split = ldb_channel_is_split_link(ldb_ch);
0269     int ret;
0270 
0271     ret = phy_power_off(imx8qxp_ldb_ch->phy);
0272     if (ret)
0273         DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
0274 
0275     ret = phy_exit(imx8qxp_ldb_ch->phy);
0276     if (ret < 0)
0277         DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret);
0278 
0279     ldb_bridge_disable_helper(bridge);
0280 
0281     clk_disable_unprepare(imx8qxp_ldb->clk_bypass);
0282     clk_disable_unprepare(imx8qxp_ldb->clk_pixel);
0283 
0284     if (is_split && companion)
0285         companion->funcs->atomic_disable(companion, old_bridge_state);
0286 
0287     ret = pm_runtime_put(dev);
0288     if (ret < 0)
0289         DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
0290 }
0291 
0292 static const u32 imx8qxp_ldb_bus_output_fmts[] = {
0293     MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
0294     MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
0295     MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
0296     MEDIA_BUS_FMT_FIXED,
0297 };
0298 
0299 static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt)
0300 {
0301     int i;
0302 
0303     for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) {
0304         if (imx8qxp_ldb_bus_output_fmts[i] == fmt)
0305             return true;
0306     }
0307 
0308     return false;
0309 }
0310 
0311 static u32 *
0312 imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
0313                          struct drm_bridge_state *bridge_state,
0314                          struct drm_crtc_state *crtc_state,
0315                          struct drm_connector_state *conn_state,
0316                          u32 output_fmt,
0317                          unsigned int *num_input_fmts)
0318 {
0319     struct drm_display_info *di;
0320     const struct drm_format_info *finfo;
0321     u32 *input_fmts;
0322 
0323     if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt))
0324         return NULL;
0325 
0326     *num_input_fmts = 1;
0327 
0328     input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
0329     if (!input_fmts)
0330         return NULL;
0331 
0332     switch (output_fmt) {
0333     case MEDIA_BUS_FMT_FIXED:
0334         di = &conn_state->connector->display_info;
0335 
0336         /*
0337          * Look at the first bus format to determine input format.
0338          * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match.
0339          */
0340         if (di->num_bus_formats) {
0341             finfo = drm_format_info(di->bus_formats[0]);
0342 
0343             input_fmts[0] = finfo->depth == 18 ?
0344                     MEDIA_BUS_FMT_RGB666_1X24_CPADHI :
0345                     MEDIA_BUS_FMT_RGB888_1X24;
0346         } else {
0347             input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
0348         }
0349         break;
0350     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0351         input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
0352         break;
0353     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0354     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0355         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
0356         break;
0357     default:
0358         kfree(input_fmts);
0359         input_fmts = NULL;
0360         break;
0361     }
0362 
0363     return input_fmts;
0364 }
0365 
0366 static u32 *
0367 imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
0368                           struct drm_bridge_state *bridge_state,
0369                           struct drm_crtc_state *crtc_state,
0370                           struct drm_connector_state *conn_state,
0371                           unsigned int *num_output_fmts)
0372 {
0373     *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts);
0374     return kmemdup(imx8qxp_ldb_bus_output_fmts,
0375             sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL);
0376 }
0377 
0378 static enum drm_mode_status
0379 imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge,
0380                   const struct drm_display_info *info,
0381                   const struct drm_display_mode *mode)
0382 {
0383     struct ldb_channel *ldb_ch = bridge->driver_private;
0384     bool is_single = ldb_channel_is_single_link(ldb_ch);
0385 
0386     if (mode->clock > 170000)
0387         return MODE_CLOCK_HIGH;
0388 
0389     if (mode->clock > 150000 && is_single)
0390         return MODE_CLOCK_HIGH;
0391 
0392     return MODE_OK;
0393 }
0394 
0395 static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = {
0396     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0397     .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
0398     .atomic_reset       = drm_atomic_helper_bridge_reset,
0399     .mode_valid     = imx8qxp_ldb_bridge_mode_valid,
0400     .attach         = ldb_bridge_attach_helper,
0401     .atomic_check       = imx8qxp_ldb_bridge_atomic_check,
0402     .mode_set       = imx8qxp_ldb_bridge_mode_set,
0403     .atomic_pre_enable  = imx8qxp_ldb_bridge_atomic_pre_enable,
0404     .atomic_enable      = imx8qxp_ldb_bridge_atomic_enable,
0405     .atomic_disable     = imx8qxp_ldb_bridge_atomic_disable,
0406     .atomic_get_input_bus_fmts =
0407             imx8qxp_ldb_bridge_atomic_get_input_bus_fmts,
0408     .atomic_get_output_bus_fmts =
0409             imx8qxp_ldb_bridge_atomic_get_output_bus_fmts,
0410 };
0411 
0412 static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb)
0413 {
0414     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
0415              &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
0416     struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
0417     struct device_node *ep, *remote;
0418     struct device *dev = imx8qxp_ldb->dev;
0419     struct of_endpoint endpoint;
0420     int ret;
0421 
0422     ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1);
0423     if (!ep) {
0424         DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n");
0425         return -EINVAL;
0426     }
0427 
0428     remote = of_graph_get_remote_endpoint(ep);
0429     of_node_put(ep);
0430     if (!remote) {
0431         DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n");
0432         return -EINVAL;
0433     }
0434 
0435     ret = of_graph_parse_endpoint(remote, &endpoint);
0436     of_node_put(remote);
0437     if (ret) {
0438         DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n",
0439                   ret);
0440         return ret;
0441     }
0442 
0443     imx8qxp_ldb_ch->di_id = endpoint.id;
0444 
0445     return 0;
0446 }
0447 
0448 static int
0449 imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link)
0450 {
0451     if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) ||
0452         (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1))
0453         return -EINVAL;
0454 
0455     return 0;
0456 }
0457 
0458 static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb)
0459 {
0460     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch =
0461              &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno];
0462     struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base;
0463     struct ldb_channel *companion_ldb_ch;
0464     struct device_node *companion;
0465     struct device_node *child;
0466     struct device_node *companion_port = NULL;
0467     struct device_node *port1, *port2;
0468     struct device *dev = imx8qxp_ldb->dev;
0469     const struct of_device_id *match;
0470     u32 i;
0471     int dual_link;
0472     int ret;
0473 
0474     /* Locate the companion LDB for dual-link operation, if any. */
0475     companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0);
0476     if (!companion)
0477         return 0;
0478 
0479     if (!of_device_is_available(companion)) {
0480         DRM_DEV_ERROR(dev, "companion LDB is not available\n");
0481         ret = -ENODEV;
0482         goto out;
0483     }
0484 
0485     /*
0486      * Sanity check: the companion bridge must have the same compatible
0487      * string.
0488      */
0489     match = of_match_device(dev->driver->of_match_table, dev);
0490     if (!of_device_is_compatible(companion, match->compatible)) {
0491         DRM_DEV_ERROR(dev, "companion LDB is incompatible\n");
0492         ret = -ENXIO;
0493         goto out;
0494     }
0495 
0496     for_each_available_child_of_node(companion, child) {
0497         ret = of_property_read_u32(child, "reg", &i);
0498         if (ret || i > MAX_LDB_CHAN_NUM - 1) {
0499             DRM_DEV_ERROR(dev,
0500                       "invalid channel node address: %u\n", i);
0501             ret = -EINVAL;
0502             of_node_put(child);
0503             goto out;
0504         }
0505 
0506         /*
0507          * Channel numbers have to be different, because channel0
0508          * transmits odd pixels and channel1 transmits even pixels.
0509          */
0510         if (i == (ldb_ch->chno ^ 0x1)) {
0511             companion_port = child;
0512             break;
0513         }
0514     }
0515 
0516     if (!companion_port) {
0517         DRM_DEV_ERROR(dev,
0518                   "failed to find companion LDB channel port\n");
0519         ret = -EINVAL;
0520         goto out;
0521     }
0522 
0523     /*
0524      * We need to work out if the sink is expecting us to function in
0525      * dual-link mode.  We do this by looking at the DT port nodes we are
0526      * connected to.  If they are marked as expecting odd pixels and
0527      * even pixels than we need to enable LDB split mode.
0528      */
0529     port1 = of_graph_get_port_by_id(ldb_ch->np, 1);
0530     port2 = of_graph_get_port_by_id(companion_port, 1);
0531     dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
0532     of_node_put(port1);
0533     of_node_put(port2);
0534 
0535     switch (dual_link) {
0536     case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
0537         ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
0538         break;
0539     case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
0540         ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS;
0541         break;
0542     default:
0543         ret = dual_link;
0544         DRM_DEV_ERROR(dev,
0545                   "failed to get dual link pixel order: %d\n", ret);
0546         goto out;
0547     }
0548 
0549     ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link);
0550     if (ret < 0) {
0551         DRM_DEV_ERROR(dev,
0552                   "unmatched channel number(%u) vs dual link(%d)\n",
0553                   ldb_ch->chno, dual_link);
0554         goto out;
0555     }
0556 
0557     imx8qxp_ldb->companion = of_drm_find_bridge(companion_port);
0558     if (!imx8qxp_ldb->companion) {
0559         ret = -EPROBE_DEFER;
0560         DRM_DEV_DEBUG_DRIVER(dev,
0561                      "failed to find bridge for companion bridge: %d\n",
0562                      ret);
0563         goto out;
0564     }
0565 
0566     DRM_DEV_DEBUG_DRIVER(dev,
0567                  "dual-link configuration detected (companion bridge %pOF)\n",
0568                  companion);
0569 
0570     companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion);
0571     companion_ldb_ch->link_type = ldb_ch->link_type;
0572 out:
0573     of_node_put(companion_port);
0574     of_node_put(companion);
0575     return ret;
0576 }
0577 
0578 static int imx8qxp_ldb_probe(struct platform_device *pdev)
0579 {
0580     struct device *dev = &pdev->dev;
0581     struct imx8qxp_ldb *imx8qxp_ldb;
0582     struct imx8qxp_ldb_channel *imx8qxp_ldb_ch;
0583     struct ldb *ldb;
0584     struct ldb_channel *ldb_ch;
0585     int ret, i;
0586 
0587     imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL);
0588     if (!imx8qxp_ldb)
0589         return -ENOMEM;
0590 
0591     imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel");
0592     if (IS_ERR(imx8qxp_ldb->clk_pixel)) {
0593         ret = PTR_ERR(imx8qxp_ldb->clk_pixel);
0594         if (ret != -EPROBE_DEFER)
0595             DRM_DEV_ERROR(dev,
0596                       "failed to get pixel clock: %d\n", ret);
0597         return ret;
0598     }
0599 
0600     imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass");
0601     if (IS_ERR(imx8qxp_ldb->clk_bypass)) {
0602         ret = PTR_ERR(imx8qxp_ldb->clk_bypass);
0603         if (ret != -EPROBE_DEFER)
0604             DRM_DEV_ERROR(dev,
0605                       "failed to get bypass clock: %d\n", ret);
0606         return ret;
0607     }
0608 
0609     imx8qxp_ldb->dev = dev;
0610 
0611     ldb = &imx8qxp_ldb->base;
0612     ldb->dev = dev;
0613     ldb->ctrl_reg = 0xe0;
0614 
0615     for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
0616         ldb->channel[i] = &imx8qxp_ldb->channel[i].base;
0617 
0618     ret = ldb_init_helper(ldb);
0619     if (ret)
0620         return ret;
0621 
0622     if (ldb->available_ch_cnt == 0) {
0623         DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
0624         return 0;
0625     } else if (ldb->available_ch_cnt > 1) {
0626         DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n",
0627                   ldb->available_ch_cnt);
0628         return -EINVAL;
0629     }
0630 
0631     for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
0632         imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i];
0633         ldb_ch = &imx8qxp_ldb_ch->base;
0634 
0635         if (ldb_ch->is_available) {
0636             imx8qxp_ldb->active_chno = ldb_ch->chno;
0637             break;
0638         }
0639     }
0640 
0641     imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy");
0642     if (IS_ERR(imx8qxp_ldb_ch->phy)) {
0643         ret = PTR_ERR(imx8qxp_ldb_ch->phy);
0644         if (ret != -EPROBE_DEFER)
0645             DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n",
0646                       imx8qxp_ldb->active_chno, ret);
0647         return ret;
0648     }
0649 
0650     ret = ldb_find_next_bridge_helper(ldb);
0651     if (ret)
0652         return ret;
0653 
0654     ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb);
0655     if (ret)
0656         return ret;
0657 
0658     ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb);
0659     if (ret)
0660         return ret;
0661 
0662     platform_set_drvdata(pdev, imx8qxp_ldb);
0663     pm_runtime_enable(dev);
0664 
0665     ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs);
0666 
0667     return ret;
0668 }
0669 
0670 static int imx8qxp_ldb_remove(struct platform_device *pdev)
0671 {
0672     struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev);
0673     struct ldb *ldb = &imx8qxp_ldb->base;
0674 
0675     ldb_remove_bridge_helper(ldb);
0676 
0677     pm_runtime_disable(&pdev->dev);
0678 
0679     return 0;
0680 }
0681 
0682 static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev)
0683 {
0684     return 0;
0685 }
0686 
0687 static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev)
0688 {
0689     struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev);
0690     struct ldb *ldb = &imx8qxp_ldb->base;
0691 
0692     /* disable LDB by resetting the control register to POR default */
0693     regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
0694 
0695     return 0;
0696 }
0697 
0698 static const struct dev_pm_ops imx8qxp_ldb_pm_ops = {
0699     SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend,
0700                imx8qxp_ldb_runtime_resume, NULL)
0701 };
0702 
0703 static const struct of_device_id imx8qxp_ldb_dt_ids[] = {
0704     { .compatible = "fsl,imx8qxp-ldb" },
0705     { /* sentinel */ }
0706 };
0707 MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids);
0708 
0709 static struct platform_driver imx8qxp_ldb_driver = {
0710     .probe  = imx8qxp_ldb_probe,
0711     .remove = imx8qxp_ldb_remove,
0712     .driver = {
0713         .pm = &imx8qxp_ldb_pm_ops,
0714         .name = DRIVER_NAME,
0715         .of_match_table = imx8qxp_ldb_dt_ids,
0716     },
0717 };
0718 module_platform_driver(imx8qxp_ldb_driver);
0719 
0720 MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
0721 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
0722 MODULE_LICENSE("GPL v2");
0723 MODULE_ALIAS("platform:" DRIVER_NAME);
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