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0001 // SPDX-License-Identifier: GPL-2.0+
0002 
0003 /*
0004  * Copyright 2020 NXP
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/media-bus-format.h>
0009 #include <linux/mfd/syscon.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_graph.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regmap.h>
0017 
0018 #include <drm/drm_atomic_state_helper.h>
0019 #include <drm/drm_bridge.h>
0020 #include <drm/drm_connector.h>
0021 #include <drm/drm_fourcc.h>
0022 #include <drm/drm_of.h>
0023 #include <drm/drm_print.h>
0024 
0025 #include "imx-ldb-helper.h"
0026 
0027 #define  LDB_CH0_10BIT_EN       BIT(22)
0028 #define  LDB_CH1_10BIT_EN       BIT(23)
0029 #define  LDB_CH0_DATA_WIDTH_24BIT   BIT(24)
0030 #define  LDB_CH1_DATA_WIDTH_24BIT   BIT(26)
0031 #define  LDB_CH0_DATA_WIDTH_30BIT   (2 << 24)
0032 #define  LDB_CH1_DATA_WIDTH_30BIT   (2 << 26)
0033 
0034 #define SS_CTRL             0x20
0035 #define  CH_HSYNC_M(id)         BIT(0 + ((id) * 2))
0036 #define  CH_VSYNC_M(id)         BIT(1 + ((id) * 2))
0037 #define  CH_PHSYNC(id)          BIT(0 + ((id) * 2))
0038 #define  CH_PVSYNC(id)          BIT(1 + ((id) * 2))
0039 
0040 #define DRIVER_NAME         "imx8qm-ldb"
0041 
0042 struct imx8qm_ldb_channel {
0043     struct ldb_channel base;
0044     struct phy *phy;
0045 };
0046 
0047 struct imx8qm_ldb {
0048     struct ldb base;
0049     struct device *dev;
0050     struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM];
0051     struct clk *clk_pixel;
0052     struct clk *clk_bypass;
0053     int active_chno;
0054 };
0055 
0056 static inline struct imx8qm_ldb_channel *
0057 base_to_imx8qm_ldb_channel(struct ldb_channel *base)
0058 {
0059     return container_of(base, struct imx8qm_ldb_channel, base);
0060 }
0061 
0062 static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base)
0063 {
0064     return container_of(base, struct imx8qm_ldb, base);
0065 }
0066 
0067 static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb,
0068                    unsigned long di_clk,
0069                    bool is_split, bool is_slave,
0070                    struct phy_configure_opts_lvds *phy_cfg)
0071 {
0072     phy_cfg->bits_per_lane_and_dclk_cycle = 7;
0073     phy_cfg->lanes = 4;
0074     phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk;
0075     phy_cfg->is_slave = is_slave;
0076 }
0077 
0078 static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge,
0079                       struct drm_bridge_state *bridge_state,
0080                       struct drm_crtc_state *crtc_state,
0081                       struct drm_connector_state *conn_state)
0082 {
0083     struct ldb_channel *ldb_ch = bridge->driver_private;
0084     struct ldb *ldb = ldb_ch->ldb;
0085     struct imx8qm_ldb_channel *imx8qm_ldb_ch =
0086                     base_to_imx8qm_ldb_channel(ldb_ch);
0087     struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
0088     struct drm_display_mode *adj = &crtc_state->adjusted_mode;
0089     unsigned long di_clk = adj->clock * 1000;
0090     bool is_split = ldb_channel_is_split_link(ldb_ch);
0091     union phy_configure_opts opts = { };
0092     struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
0093     int ret;
0094 
0095     ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
0096                          crtc_state, conn_state);
0097     if (ret)
0098         return ret;
0099 
0100     imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
0101     ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
0102     if (ret < 0) {
0103         DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
0104                      "failed to validate PHY: %d\n", ret);
0105         return ret;
0106     }
0107 
0108     if (is_split) {
0109         imx8qm_ldb_ch =
0110             &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
0111         imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
0112                        phy_cfg);
0113         ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
0114         if (ret < 0) {
0115             DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
0116                          "failed to validate slave PHY: %d\n",
0117                          ret);
0118             return ret;
0119         }
0120     }
0121 
0122     return ret;
0123 }
0124 
0125 static void
0126 imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge,
0127                const struct drm_display_mode *mode,
0128                const struct drm_display_mode *adjusted_mode)
0129 {
0130     struct ldb_channel *ldb_ch = bridge->driver_private;
0131     struct ldb *ldb = ldb_ch->ldb;
0132     struct imx8qm_ldb_channel *imx8qm_ldb_ch =
0133                     base_to_imx8qm_ldb_channel(ldb_ch);
0134     struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
0135     struct device *dev = imx8qm_ldb->dev;
0136     unsigned long di_clk = adjusted_mode->clock * 1000;
0137     bool is_split = ldb_channel_is_split_link(ldb_ch);
0138     union phy_configure_opts opts = { };
0139     struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
0140     u32 chno = ldb_ch->chno;
0141     int ret;
0142 
0143     ret = pm_runtime_get_sync(dev);
0144     if (ret < 0)
0145         DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
0146 
0147     ret = phy_init(imx8qm_ldb_ch->phy);
0148     if (ret < 0)
0149         DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
0150 
0151     clk_set_rate(imx8qm_ldb->clk_bypass, di_clk);
0152     clk_set_rate(imx8qm_ldb->clk_pixel, di_clk);
0153 
0154     imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
0155     ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
0156     if (ret < 0)
0157         DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
0158 
0159     if (is_split) {
0160         imx8qm_ldb_ch =
0161             &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
0162         imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
0163                        phy_cfg);
0164         ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
0165         if (ret < 0)
0166             DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n",
0167                       ret);
0168     }
0169 
0170     /* input VSYNC signal from pixel link is active low */
0171     if (ldb_ch->chno == 0 || is_split)
0172         ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
0173     if (ldb_ch->chno == 1 || is_split)
0174         ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
0175 
0176     switch (ldb_ch->out_bus_format) {
0177     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0178         break;
0179     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0180     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0181         if (ldb_ch->chno == 0 || is_split)
0182             ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT;
0183         if (ldb_ch->chno == 1 || is_split)
0184             ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT;
0185         break;
0186     }
0187 
0188     ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
0189 
0190     if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
0191         regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
0192     else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
0193         regmap_update_bits(ldb->regmap, SS_CTRL,
0194                    CH_VSYNC_M(chno), CH_PVSYNC(chno));
0195 
0196     if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
0197         regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
0198     else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
0199         regmap_update_bits(ldb->regmap, SS_CTRL,
0200                    CH_HSYNC_M(chno), CH_PHSYNC(chno));
0201 }
0202 
0203 static void
0204 imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
0205                 struct drm_bridge_state *old_bridge_state)
0206 {
0207     struct ldb_channel *ldb_ch = bridge->driver_private;
0208     struct ldb *ldb = ldb_ch->ldb;
0209     struct imx8qm_ldb_channel *imx8qm_ldb_ch =
0210                     base_to_imx8qm_ldb_channel(ldb_ch);
0211     struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
0212     struct device *dev = imx8qm_ldb->dev;
0213     bool is_split = ldb_channel_is_split_link(ldb_ch);
0214     int ret;
0215 
0216     clk_prepare_enable(imx8qm_ldb->clk_pixel);
0217     clk_prepare_enable(imx8qm_ldb->clk_bypass);
0218 
0219     /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */
0220     if (ldb_ch->chno == 0 || is_split) {
0221         ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
0222         ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
0223     }
0224     if (ldb_ch->chno == 1 || is_split) {
0225         ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
0226         ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
0227     }
0228 
0229     if (is_split) {
0230         ret = phy_power_on(imx8qm_ldb->channel[0].phy);
0231         if (ret)
0232             DRM_DEV_ERROR(dev,
0233                       "failed to power on channel0 PHY: %d\n",
0234                       ret);
0235 
0236         ret = phy_power_on(imx8qm_ldb->channel[1].phy);
0237         if (ret)
0238             DRM_DEV_ERROR(dev,
0239                       "failed to power on channel1 PHY: %d\n",
0240                       ret);
0241     } else {
0242         ret = phy_power_on(imx8qm_ldb_ch->phy);
0243         if (ret)
0244             DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
0245     }
0246 
0247     ldb_bridge_enable_helper(bridge);
0248 }
0249 
0250 static void
0251 imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
0252                  struct drm_bridge_state *old_bridge_state)
0253 {
0254     struct ldb_channel *ldb_ch = bridge->driver_private;
0255     struct ldb *ldb = ldb_ch->ldb;
0256     struct imx8qm_ldb_channel *imx8qm_ldb_ch =
0257                     base_to_imx8qm_ldb_channel(ldb_ch);
0258     struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
0259     struct device *dev = imx8qm_ldb->dev;
0260     bool is_split = ldb_channel_is_split_link(ldb_ch);
0261     int ret;
0262 
0263     ldb_bridge_disable_helper(bridge);
0264 
0265     if (is_split) {
0266         ret = phy_power_off(imx8qm_ldb->channel[0].phy);
0267         if (ret)
0268             DRM_DEV_ERROR(dev,
0269                       "failed to power off channel0 PHY: %d\n",
0270                       ret);
0271         ret = phy_power_off(imx8qm_ldb->channel[1].phy);
0272         if (ret)
0273             DRM_DEV_ERROR(dev,
0274                       "failed to power off channel1 PHY: %d\n",
0275                       ret);
0276     } else {
0277         ret = phy_power_off(imx8qm_ldb_ch->phy);
0278         if (ret)
0279             DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
0280     }
0281 
0282     clk_disable_unprepare(imx8qm_ldb->clk_bypass);
0283     clk_disable_unprepare(imx8qm_ldb->clk_pixel);
0284 
0285     ret = pm_runtime_put(dev);
0286     if (ret < 0)
0287         DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
0288 }
0289 
0290 static const u32 imx8qm_ldb_bus_output_fmts[] = {
0291     MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
0292     MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
0293     MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
0294     MEDIA_BUS_FMT_FIXED,
0295 };
0296 
0297 static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt)
0298 {
0299     int i;
0300 
0301     for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) {
0302         if (imx8qm_ldb_bus_output_fmts[i] == fmt)
0303             return true;
0304     }
0305 
0306     return false;
0307 }
0308 
0309 static u32 *
0310 imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
0311                         struct drm_bridge_state *bridge_state,
0312                         struct drm_crtc_state *crtc_state,
0313                         struct drm_connector_state *conn_state,
0314                         u32 output_fmt,
0315                         unsigned int *num_input_fmts)
0316 {
0317     struct drm_display_info *di;
0318     const struct drm_format_info *finfo;
0319     u32 *input_fmts;
0320 
0321     if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt))
0322         return NULL;
0323 
0324     *num_input_fmts = 1;
0325 
0326     input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
0327     if (!input_fmts)
0328         return NULL;
0329 
0330     switch (output_fmt) {
0331     case MEDIA_BUS_FMT_FIXED:
0332         di = &conn_state->connector->display_info;
0333 
0334         /*
0335          * Look at the first bus format to determine input format.
0336          * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match.
0337          */
0338         if (di->num_bus_formats) {
0339             finfo = drm_format_info(di->bus_formats[0]);
0340 
0341             input_fmts[0] = finfo->depth == 18 ?
0342                     MEDIA_BUS_FMT_RGB666_1X36_CPADLO :
0343                     MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
0344         } else {
0345             input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
0346         }
0347         break;
0348     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0349         input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
0350         break;
0351     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0352     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0353         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
0354         break;
0355     default:
0356         kfree(input_fmts);
0357         input_fmts = NULL;
0358         break;
0359     }
0360 
0361     return input_fmts;
0362 }
0363 
0364 static u32 *
0365 imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
0366                          struct drm_bridge_state *bridge_state,
0367                          struct drm_crtc_state *crtc_state,
0368                          struct drm_connector_state *conn_state,
0369                          unsigned int *num_output_fmts)
0370 {
0371     *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts);
0372     return kmemdup(imx8qm_ldb_bus_output_fmts,
0373             sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL);
0374 }
0375 
0376 static enum drm_mode_status
0377 imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge,
0378                  const struct drm_display_info *info,
0379                  const struct drm_display_mode *mode)
0380 {
0381     struct ldb_channel *ldb_ch = bridge->driver_private;
0382     bool is_single = ldb_channel_is_single_link(ldb_ch);
0383 
0384     if (mode->clock > 300000)
0385         return MODE_CLOCK_HIGH;
0386 
0387     if (mode->clock > 150000 && is_single)
0388         return MODE_CLOCK_HIGH;
0389 
0390     return MODE_OK;
0391 }
0392 
0393 static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = {
0394     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0395     .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
0396     .atomic_reset       = drm_atomic_helper_bridge_reset,
0397     .mode_valid     = imx8qm_ldb_bridge_mode_valid,
0398     .attach         = ldb_bridge_attach_helper,
0399     .atomic_check       = imx8qm_ldb_bridge_atomic_check,
0400     .mode_set       = imx8qm_ldb_bridge_mode_set,
0401     .atomic_enable      = imx8qm_ldb_bridge_atomic_enable,
0402     .atomic_disable     = imx8qm_ldb_bridge_atomic_disable,
0403     .atomic_get_input_bus_fmts =
0404             imx8qm_ldb_bridge_atomic_get_input_bus_fmts,
0405     .atomic_get_output_bus_fmts =
0406             imx8qm_ldb_bridge_atomic_get_output_bus_fmts,
0407 };
0408 
0409 static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb)
0410 {
0411     struct imx8qm_ldb_channel *imx8qm_ldb_ch;
0412     struct ldb_channel *ldb_ch;
0413     struct device *dev = imx8qm_ldb->dev;
0414     int i, ret;
0415 
0416     for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
0417         imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
0418         ldb_ch = &imx8qm_ldb_ch->base;
0419 
0420         if (!ldb_ch->is_available)
0421             continue;
0422 
0423         imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np,
0424                              "lvds_phy");
0425         if (IS_ERR(imx8qm_ldb_ch->phy)) {
0426             ret = PTR_ERR(imx8qm_ldb_ch->phy);
0427             if (ret != -EPROBE_DEFER)
0428                 DRM_DEV_ERROR(dev,
0429                           "failed to get channel%d PHY: %d\n",
0430                           i, ret);
0431             return ret;
0432         }
0433     }
0434 
0435     return 0;
0436 }
0437 
0438 static int imx8qm_ldb_probe(struct platform_device *pdev)
0439 {
0440     struct device *dev = &pdev->dev;
0441     struct imx8qm_ldb *imx8qm_ldb;
0442     struct imx8qm_ldb_channel *imx8qm_ldb_ch;
0443     struct ldb *ldb;
0444     struct ldb_channel *ldb_ch;
0445     struct device_node *port1, *port2;
0446     int pixel_order;
0447     int ret, i;
0448 
0449     imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL);
0450     if (!imx8qm_ldb)
0451         return -ENOMEM;
0452 
0453     imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel");
0454     if (IS_ERR(imx8qm_ldb->clk_pixel)) {
0455         ret = PTR_ERR(imx8qm_ldb->clk_pixel);
0456         if (ret != -EPROBE_DEFER)
0457             DRM_DEV_ERROR(dev,
0458                       "failed to get pixel clock: %d\n", ret);
0459         return ret;
0460     }
0461 
0462     imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass");
0463     if (IS_ERR(imx8qm_ldb->clk_bypass)) {
0464         ret = PTR_ERR(imx8qm_ldb->clk_bypass);
0465         if (ret != -EPROBE_DEFER)
0466             DRM_DEV_ERROR(dev,
0467                       "failed to get bypass clock: %d\n", ret);
0468         return ret;
0469     }
0470 
0471     imx8qm_ldb->dev = dev;
0472 
0473     ldb = &imx8qm_ldb->base;
0474     ldb->dev = dev;
0475     ldb->ctrl_reg = 0xe0;
0476 
0477     for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
0478         ldb->channel[i] = &imx8qm_ldb->channel[i].base;
0479 
0480     ret = ldb_init_helper(ldb);
0481     if (ret)
0482         return ret;
0483 
0484     if (ldb->available_ch_cnt == 0) {
0485         DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
0486         return 0;
0487     }
0488 
0489     if (ldb->available_ch_cnt == 2) {
0490         port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1);
0491         port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1);
0492         pixel_order =
0493             drm_of_lvds_get_dual_link_pixel_order(port1, port2);
0494         of_node_put(port1);
0495         of_node_put(port2);
0496 
0497         if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
0498             DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n",
0499                       pixel_order);
0500             return -EINVAL;
0501         }
0502 
0503         imx8qm_ldb->active_chno = 0;
0504         imx8qm_ldb_ch = &imx8qm_ldb->channel[0];
0505         ldb_ch = &imx8qm_ldb_ch->base;
0506         ldb_ch->link_type = pixel_order;
0507     } else {
0508         for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
0509             imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
0510             ldb_ch = &imx8qm_ldb_ch->base;
0511 
0512             if (ldb_ch->is_available) {
0513                 imx8qm_ldb->active_chno = ldb_ch->chno;
0514                 break;
0515             }
0516         }
0517     }
0518 
0519     ret = imx8qm_ldb_get_phy(imx8qm_ldb);
0520     if (ret)
0521         return ret;
0522 
0523     ret = ldb_find_next_bridge_helper(ldb);
0524     if (ret)
0525         return ret;
0526 
0527     platform_set_drvdata(pdev, imx8qm_ldb);
0528     pm_runtime_enable(dev);
0529 
0530     ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs);
0531 
0532     return ret;
0533 }
0534 
0535 static int imx8qm_ldb_remove(struct platform_device *pdev)
0536 {
0537     struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev);
0538     struct ldb *ldb = &imx8qm_ldb->base;
0539 
0540     ldb_remove_bridge_helper(ldb);
0541 
0542     pm_runtime_disable(&pdev->dev);
0543 
0544     return 0;
0545 }
0546 
0547 static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev)
0548 {
0549     return 0;
0550 }
0551 
0552 static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev)
0553 {
0554     struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
0555     struct ldb *ldb = &imx8qm_ldb->base;
0556 
0557     /* disable LDB by resetting the control register to POR default */
0558     regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
0559 
0560     return 0;
0561 }
0562 
0563 static const struct dev_pm_ops imx8qm_ldb_pm_ops = {
0564     SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend,
0565                imx8qm_ldb_runtime_resume, NULL)
0566 };
0567 
0568 static const struct of_device_id imx8qm_ldb_dt_ids[] = {
0569     { .compatible = "fsl,imx8qm-ldb" },
0570     { /* sentinel */ }
0571 };
0572 MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids);
0573 
0574 static struct platform_driver imx8qm_ldb_driver = {
0575     .probe  = imx8qm_ldb_probe,
0576     .remove = imx8qm_ldb_remove,
0577     .driver = {
0578         .pm = &imx8qm_ldb_pm_ops,
0579         .name = DRIVER_NAME,
0580         .of_match_table = imx8qm_ldb_dt_ids,
0581     },
0582 };
0583 module_platform_driver(imx8qm_ldb_driver);
0584 
0585 MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
0586 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
0587 MODULE_LICENSE("GPL v2");
0588 MODULE_ALIAS("platform:" DRIVER_NAME);
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