drm/bridge/fsl-ldb.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2022 Marek Vasut <marex@denx.de>
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/media-bus-format.h>
0008 #include <linux/mfd/syscon.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/of_device.h>
0012 #include <linux/of_graph.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015
0016 #include <drm/drm_atomic_helper.h>
0017 #include <drm/drm_bridge.h>
0018 #include <drm/drm_of.h>
0019 #include <drm/drm_panel.h>
0020
0021 #define LDB_CTRL                0x5c
0022 #define LDB_CTRL_CH0_ENABLE         BIT(0)
0023 #define LDB_CTRL_CH0_DI_SELECT          BIT(1)
0024 #define LDB_CTRL_CH1_ENABLE         BIT(2)
0025 #define LDB_CTRL_CH1_DI_SELECT          BIT(3)
0026 #define LDB_CTRL_SPLIT_MODE         BIT(4)
0027 #define LDB_CTRL_CH0_DATA_WIDTH         BIT(5)
0028 #define LDB_CTRL_CH0_BIT_MAPPING        BIT(6)
0029 #define LDB_CTRL_CH1_DATA_WIDTH         BIT(7)
0030 #define LDB_CTRL_CH1_BIT_MAPPING        BIT(8)
0031 #define LDB_CTRL_DI0_VSYNC_POLARITY     BIT(9)
0032 #define LDB_CTRL_DI1_VSYNC_POLARITY     BIT(10)
0033 #define LDB_CTRL_REG_CH0_FIFO_RESET     BIT(11)
0034 #define LDB_CTRL_REG_CH1_FIFO_RESET     BIT(12)
0035 #define LDB_CTRL_ASYNC_FIFO_ENABLE      BIT(24)
0036 #define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK  GENMASK(27, 25)
0037
0038 #define LVDS_CTRL               0x128
0039 #define LVDS_CTRL_CH0_EN            BIT(0)
0040 #define LVDS_CTRL_CH1_EN            BIT(1)
0041 #define LVDS_CTRL_VBG_EN            BIT(2)
0042 #define LVDS_CTRL_HS_EN             BIT(3)
0043 #define LVDS_CTRL_PRE_EMPH_EN           BIT(4)
0044 #define LVDS_CTRL_PRE_EMPH_ADJ(n)       (((n) & 0x7) << 5)
0045 #define LVDS_CTRL_PRE_EMPH_ADJ_MASK     GENMASK(7, 5)
0046 #define LVDS_CTRL_CM_ADJ(n)         (((n) & 0x7) << 8)
0047 #define LVDS_CTRL_CM_ADJ_MASK           GENMASK(10, 8)
0048 #define LVDS_CTRL_CC_ADJ(n)         (((n) & 0x7) << 11)
0049 #define LVDS_CTRL_CC_ADJ_MASK           GENMASK(13, 11)
0050 #define LVDS_CTRL_SLEW_ADJ(n)           (((n) & 0x7) << 14)
0051 #define LVDS_CTRL_SLEW_ADJ_MASK         GENMASK(16, 14)
0052 #define LVDS_CTRL_VBG_ADJ(n)            (((n) & 0x7) << 17)
0053 #define LVDS_CTRL_VBG_ADJ_MASK          GENMASK(19, 17)
0054
0055 struct fsl_ldb {
0056     struct device *dev;
0057     struct drm_bridge bridge;
0058     struct drm_bridge *panel_bridge;
0059     struct clk *clk;
0060     struct regmap *regmap;
0061     bool lvds_dual_link;
0062 };
0063
0064 static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge)
0065 {
0066     return container_of(bridge, struct fsl_ldb, bridge);
0067 }
0068
0069 static int fsl_ldb_attach(struct drm_bridge *bridge,
0070               enum drm_bridge_attach_flags flags)
0071 {
0072     struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
0073
0074     return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge,
0075                  bridge, flags);
0076 }
0077
0078 static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
0079                   struct drm_bridge_state *old_bridge_state)
0080 {
0081     struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
0082     struct drm_atomic_state *state = old_bridge_state->base.state;
0083     const struct drm_bridge_state *bridge_state;
0084     const struct drm_crtc_state *crtc_state;
0085     const struct drm_display_mode *mode;
0086     struct drm_connector *connector;
0087     struct drm_crtc *crtc;
0088     bool lvds_format_24bpp;
0089     bool lvds_format_jeida;
0090     u32 reg;
0091
0092     /* Get the LVDS format from the bridge state. */
0093     bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
0094
0095     switch (bridge_state->output_bus_cfg.format) {
0096     case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
0097         lvds_format_24bpp = false;
0098         lvds_format_jeida = true;
0099         break;
0100     case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
0101         lvds_format_24bpp = true;
0102         lvds_format_jeida = true;
0103         break;
0104     case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
0105         lvds_format_24bpp = true;
0106         lvds_format_jeida = false;
0107         break;
0108     default:
0109         /*
0110          * Some bridges still don't set the correct LVDS bus pixel
0111          * format, use SPWG24 default format until those are fixed.
0112          */
0113         lvds_format_24bpp = true;
0114         lvds_format_jeida = false;
0115         dev_warn(fsl_ldb->dev,
0116              "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
0117              bridge_state->output_bus_cfg.format);
0118         break;
0119     }
0120
0121     /*
0122      * Retrieve the CRTC adjusted mode. This requires a little dance to go
0123      * from the bridge to the encoder, to the connector and to the CRTC.
0124      */
0125     connector = drm_atomic_get_new_connector_for_encoder(state,
0126                                  bridge->encoder);
0127     crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
0128     crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
0129     mode = &crtc_state->adjusted_mode;
0130
0131     if (fsl_ldb->lvds_dual_link)
0132         clk_set_rate(fsl_ldb->clk, mode->clock * 3500);
0133     else
0134         clk_set_rate(fsl_ldb->clk, mode->clock * 7000);
0135     clk_prepare_enable(fsl_ldb->clk);
0136
0137     /* Program LDB_CTRL */
0138     reg = LDB_CTRL_CH0_ENABLE;
0139
0140     if (fsl_ldb->lvds_dual_link)
0141         reg |= LDB_CTRL_CH1_ENABLE | LDB_CTRL_SPLIT_MODE;
0142
0143     if (lvds_format_24bpp) {
0144         reg |= LDB_CTRL_CH0_DATA_WIDTH;
0145         if (fsl_ldb->lvds_dual_link)
0146             reg |= LDB_CTRL_CH1_DATA_WIDTH;
0147     }
0148
0149     if (lvds_format_jeida) {
0150         reg |= LDB_CTRL_CH0_BIT_MAPPING;
0151         if (fsl_ldb->lvds_dual_link)
0152             reg |= LDB_CTRL_CH1_BIT_MAPPING;
0153     }
0154
0155     if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
0156         reg |= LDB_CTRL_DI0_VSYNC_POLARITY;
0157         if (fsl_ldb->lvds_dual_link)
0158             reg |= LDB_CTRL_DI1_VSYNC_POLARITY;
0159     }
0160
0161     regmap_write(fsl_ldb->regmap, LDB_CTRL, reg);
0162
0163     /* Program LVDS_CTRL */
0164     reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
0165           LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
0166     regmap_write(fsl_ldb->regmap, LVDS_CTRL, reg);
0167
0168     /* Wait for VBG to stabilize. */
0169     usleep_range(15, 20);
0170
0171     reg |= LVDS_CTRL_CH0_EN;
0172     if (fsl_ldb->lvds_dual_link)
0173         reg |= LVDS_CTRL_CH1_EN;
0174
0175     regmap_write(fsl_ldb->regmap, LVDS_CTRL, reg);
0176 }
0177
0178 static void fsl_ldb_atomic_disable(struct drm_bridge *bridge,
0179                    struct drm_bridge_state *old_bridge_state)
0180 {
0181     struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
0182
0183     /* Stop both channels. */
0184     regmap_write(fsl_ldb->regmap, LVDS_CTRL, 0);
0185     regmap_write(fsl_ldb->regmap, LDB_CTRL, 0);
0186
0187     clk_disable_unprepare(fsl_ldb->clk);
0188 }
0189
0190 #define MAX_INPUT_SEL_FORMATS 1
0191 static u32 *
0192 fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
0193                   struct drm_bridge_state *bridge_state,
0194                   struct drm_crtc_state *crtc_state,
0195                   struct drm_connector_state *conn_state,
0196                   u32 output_fmt,
0197                   unsigned int *num_input_fmts)
0198 {
0199     u32 *input_fmts;
0200
0201     *num_input_fmts = 0;
0202
0203     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
0204                  GFP_KERNEL);
0205     if (!input_fmts)
0206         return NULL;
0207
0208     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
0209     *num_input_fmts = MAX_INPUT_SEL_FORMATS;
0210
0211     return input_fmts;
0212 }
0213
0214 static enum drm_mode_status
0215 fsl_ldb_mode_valid(struct drm_bridge *bridge,
0216            const struct drm_display_info *info,
0217            const struct drm_display_mode *mode)
0218 {
0219     struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
0220
0221     if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
0222         return MODE_CLOCK_HIGH;
0223
0224     return MODE_OK;
0225 }
0226
0227 static const struct drm_bridge_funcs funcs = {
0228     .attach = fsl_ldb_attach,
0229     .atomic_enable = fsl_ldb_atomic_enable,
0230     .atomic_disable = fsl_ldb_atomic_disable,
0231     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0232     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
0233     .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts,
0234     .atomic_reset = drm_atomic_helper_bridge_reset,
0235     .mode_valid = fsl_ldb_mode_valid,
0236 };
0237
0238 static int fsl_ldb_probe(struct platform_device *pdev)
0239 {
0240     struct device *dev = &pdev->dev;
0241     struct device_node *panel_node;
0242     struct device_node *port1, *port2;
0243     struct drm_panel *panel;
0244     struct fsl_ldb *fsl_ldb;
0245     int dual_link;
0246
0247     fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
0248     if (!fsl_ldb)
0249         return -ENOMEM;
0250
0251     fsl_ldb->dev = &pdev->dev;
0252     fsl_ldb->bridge.funcs = &funcs;
0253     fsl_ldb->bridge.of_node = dev->of_node;
0254
0255     fsl_ldb->clk = devm_clk_get(dev, "ldb");
0256     if (IS_ERR(fsl_ldb->clk))
0257         return PTR_ERR(fsl_ldb->clk);
0258
0259     fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent);
0260     if (IS_ERR(fsl_ldb->regmap))
0261         return PTR_ERR(fsl_ldb->regmap);
0262
0263     /* Locate the panel DT node. */
0264     panel_node = of_graph_get_remote_node(dev->of_node, 1, 0);
0265     if (!panel_node)
0266         return -ENXIO;
0267
0268     panel = of_drm_find_panel(panel_node);
0269     of_node_put(panel_node);
0270     if (IS_ERR(panel))
0271         return PTR_ERR(panel);
0272
0273     fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
0274     if (IS_ERR(fsl_ldb->panel_bridge))
0275         return PTR_ERR(fsl_ldb->panel_bridge);
0276
0277     /* Determine whether this is dual-link configuration */
0278     port1 = of_graph_get_port_by_id(dev->of_node, 1);
0279     port2 = of_graph_get_port_by_id(dev->of_node, 2);
0280     dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
0281     of_node_put(port1);
0282     of_node_put(port2);
0283
0284     if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
0285         dev_err(dev, "LVDS channel pixel swap not supported.\n");
0286         return -EINVAL;
0287     }
0288
0289     if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
0290         fsl_ldb->lvds_dual_link = true;
0291
0292     platform_set_drvdata(pdev, fsl_ldb);
0293
0294     drm_bridge_add(&fsl_ldb->bridge);
0295
0296     return 0;
0297 }
0298
0299 static int fsl_ldb_remove(struct platform_device *pdev)
0300 {
0301     struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev);
0302
0303     drm_bridge_remove(&fsl_ldb->bridge);
0304
0305     return 0;
0306 }
0307
0308 static const struct of_device_id fsl_ldb_match[] = {
0309     { .compatible = "fsl,imx8mp-ldb", },
0310     { /* sentinel */ },
0311 };
0312 MODULE_DEVICE_TABLE(of, fsl_ldb_match);
0313
0314 static struct platform_driver fsl_ldb_driver = {
0315     .probe  = fsl_ldb_probe,
0316     .remove = fsl_ldb_remove,
0317     .driver     = {
0318         .name       = "fsl-ldb",
0319         .of_match_table = fsl_ldb_match,
0320     },
0321 };
0322 module_platform_driver(fsl_ldb_driver);
0323
0324 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
0325 MODULE_DESCRIPTION("Freescale i.MX8MP LDB");
0326 MODULE_LICENSE("GPL");