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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2020 Amarula Solutions(India)
0004  * Author: Jagan Teki <jagan@amarulasolutions.com>
0005  */
0006 
0007 #include <drm/drm_atomic_helper.h>
0008 #include <drm/drm_of.h>
0009 #include <drm/drm_print.h>
0010 #include <drm/drm_mipi_dsi.h>
0011 
0012 #include <linux/bitfield.h>
0013 #include <linux/bits.h>
0014 #include <linux/delay.h>
0015 #include <linux/gpio/consumer.h>
0016 #include <linux/i2c.h>
0017 #include <linux/media-bus-format.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 #include <linux/regmap.h>
0021 #include <linux/regulator/consumer.h>
0022 
0023 #define VENDOR_ID       0x00
0024 #define DEVICE_ID_H     0x01
0025 #define DEVICE_ID_L     0x02
0026 #define VERSION_ID      0x03
0027 #define FIRMWARE_VERSION    0x08
0028 #define CONFIG_FINISH       0x09
0029 #define PD_CTRL(n)      (0x0a + ((n) & 0x3)) /* 0..3 */
0030 #define RST_CTRL(n)     (0x0e + ((n) & 0x1)) /* 0..1 */
0031 #define SYS_CTRL(n)     (0x10 + ((n) & 0x7)) /* 0..4 */
0032 #define SYS_CTRL_1_CLK_PHASE_MSK    GENMASK(5, 4)
0033 #define CLK_PHASE_0         0
0034 #define CLK_PHASE_1_4           1
0035 #define CLK_PHASE_1_2           2
0036 #define CLK_PHASE_3_4           3
0037 #define RGB_DRV(n)      (0x18 + ((n) & 0x3)) /* 0..3 */
0038 #define RGB_DLY(n)      (0x1c + ((n) & 0x1)) /* 0..1 */
0039 #define RGB_TEST_CTRL       0x1e
0040 #define ATE_PLL_EN      0x1f
0041 #define HACTIVE_LI      0x20
0042 #define VACTIVE_LI      0x21
0043 #define VACTIVE_HACTIVE_HI  0x22
0044 #define HFP_LI          0x23
0045 #define HSYNC_LI        0x24
0046 #define HBP_LI          0x25
0047 #define HFP_HSW_HBP_HI      0x26
0048 #define HFP_HSW_HBP_HI_HFP(n)       (((n) & 0x300) >> 4)
0049 #define HFP_HSW_HBP_HI_HS(n)        (((n) & 0x300) >> 6)
0050 #define HFP_HSW_HBP_HI_HBP(n)       (((n) & 0x300) >> 8)
0051 #define VFP         0x27
0052 #define VSYNC           0x28
0053 #define VBP         0x29
0054 #define BIST_POL        0x2a
0055 #define BIST_POL_BIST_MODE(n)       (((n) & 0xf) << 4)
0056 #define BIST_POL_BIST_GEN       BIT(3)
0057 #define BIST_POL_HSYNC_POL      BIT(2)
0058 #define BIST_POL_VSYNC_POL      BIT(1)
0059 #define BIST_POL_DE_POL         BIT(0)
0060 #define BIST_RED        0x2b
0061 #define BIST_GREEN      0x2c
0062 #define BIST_BLUE       0x2d
0063 #define BIST_CHESS_X        0x2e
0064 #define BIST_CHESS_Y        0x2f
0065 #define BIST_CHESS_XY_H     0x30
0066 #define BIST_FRAME_TIME_L   0x31
0067 #define BIST_FRAME_TIME_H   0x32
0068 #define FIFO_MAX_ADDR_LOW   0x33
0069 #define SYNC_EVENT_DLY      0x34
0070 #define HSW_MIN         0x35
0071 #define HFP_MIN         0x36
0072 #define LOGIC_RST_NUM       0x37
0073 #define OSC_CTRL(n)     (0x48 + ((n) & 0x7)) /* 0..5 */
0074 #define BG_CTRL         0x4e
0075 #define LDO_PLL         0x4f
0076 #define PLL_CTRL(n)     (0x50 + ((n) & 0xf)) /* 0..15 */
0077 #define PLL_CTRL_6_EXTERNAL     0x90
0078 #define PLL_CTRL_6_MIPI_CLK     0x92
0079 #define PLL_CTRL_6_INTERNAL     0x93
0080 #define PLL_REM(n)      (0x60 + ((n) & 0x3)) /* 0..2 */
0081 #define PLL_DIV(n)      (0x63 + ((n) & 0x3)) /* 0..2 */
0082 #define PLL_FRAC(n)     (0x66 + ((n) & 0x3)) /* 0..2 */
0083 #define PLL_INT(n)      (0x69 + ((n) & 0x1)) /* 0..1 */
0084 #define PLL_REF_DIV     0x6b
0085 #define PLL_REF_DIV_P(n)        ((n) & 0xf)
0086 #define PLL_REF_DIV_Pe          BIT(4)
0087 #define PLL_REF_DIV_S(n)        (((n) & 0x7) << 5)
0088 #define PLL_SSC_P(n)        (0x6c + ((n) & 0x3)) /* 0..2 */
0089 #define PLL_SSC_STEP(n)     (0x6f + ((n) & 0x3)) /* 0..2 */
0090 #define PLL_SSC_OFFSET(n)   (0x72 + ((n) & 0x3)) /* 0..3 */
0091 #define GPIO_OEN        0x79
0092 #define MIPI_CFG_PW     0x7a
0093 #define MIPI_CFG_PW_CONFIG_DSI      0xc1
0094 #define MIPI_CFG_PW_CONFIG_I2C      0x3e
0095 #define GPIO_SEL(n)     (0x7b + ((n) & 0x1)) /* 0..1 */
0096 #define IRQ_SEL         0x7d
0097 #define DBG_SEL         0x7e
0098 #define DBG_SIGNAL      0x7f
0099 #define MIPI_ERR_VECTOR_L   0x80
0100 #define MIPI_ERR_VECTOR_H   0x81
0101 #define MIPI_ERR_VECTOR_EN_L    0x82
0102 #define MIPI_ERR_VECTOR_EN_H    0x83
0103 #define MIPI_MAX_SIZE_L     0x84
0104 #define MIPI_MAX_SIZE_H     0x85
0105 #define DSI_CTRL        0x86
0106 #define DSI_CTRL_UNKNOWN        0x28
0107 #define DSI_CTRL_DSI_LANES(n)       ((n) & 0x3)
0108 #define MIPI_PN_SWAP        0x87
0109 #define MIPI_PN_SWAP_CLK        BIT(4)
0110 #define MIPI_PN_SWAP_D(n)       BIT((n) & 0x3)
0111 #define MIPI_SOT_SYNC_BIT(n)    (0x88 + ((n) & 0x1)) /* 0..1 */
0112 #define MIPI_ULPS_CTRL      0x8a
0113 #define MIPI_CLK_CHK_VAR    0x8e
0114 #define MIPI_CLK_CHK_INI    0x8f
0115 #define MIPI_T_TERM_EN      0x90
0116 #define MIPI_T_HS_SETTLE    0x91
0117 #define MIPI_T_TA_SURE_PRE  0x92
0118 #define MIPI_T_LPX_SET      0x94
0119 #define MIPI_T_CLK_MISS     0x95
0120 #define MIPI_INIT_TIME_L    0x96
0121 #define MIPI_INIT_TIME_H    0x97
0122 #define MIPI_T_CLK_TERM_EN  0x99
0123 #define MIPI_T_CLK_SETTLE   0x9a
0124 #define MIPI_TO_HS_RX_L     0x9e
0125 #define MIPI_TO_HS_RX_H     0x9f
0126 #define MIPI_PHY(n)     (0xa0 + ((n) & 0x7)) /* 0..5 */
0127 #define MIPI_PD_RX      0xb0
0128 #define MIPI_PD_TERM        0xb1
0129 #define MIPI_PD_HSRX        0xb2
0130 #define MIPI_PD_LPTX        0xb3
0131 #define MIPI_PD_LPRX        0xb4
0132 #define MIPI_PD_CK_LANE     0xb5
0133 #define MIPI_FORCE_0        0xb6
0134 #define MIPI_RST_CTRL       0xb7
0135 #define MIPI_RST_NUM        0xb8
0136 #define MIPI_DBG_SET(n)     (0xc0 + ((n) & 0xf)) /* 0..9 */
0137 #define MIPI_DBG_SEL        0xe0
0138 #define MIPI_DBG_DATA       0xe1
0139 #define MIPI_ATE_TEST_SEL   0xe2
0140 #define MIPI_ATE_STATUS(n)  (0xe3 + ((n) & 0x1)) /* 0..1 */
0141 
0142 struct chipone {
0143     struct device *dev;
0144     struct regmap *regmap;
0145     struct i2c_client *client;
0146     struct drm_bridge bridge;
0147     struct drm_display_mode mode;
0148     struct drm_bridge *panel_bridge;
0149     struct mipi_dsi_device *dsi;
0150     struct gpio_desc *enable_gpio;
0151     struct regulator *vdd1;
0152     struct regulator *vdd2;
0153     struct regulator *vdd3;
0154     bool interface_i2c;
0155 };
0156 
0157 static const struct regmap_range chipone_dsi_readable_ranges[] = {
0158     regmap_reg_range(VENDOR_ID, VERSION_ID),
0159     regmap_reg_range(FIRMWARE_VERSION, PLL_SSC_OFFSET(3)),
0160     regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),
0161     regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),
0162     regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),
0163     regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),
0164     regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)),
0165     regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),
0166     regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)),
0167     regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)),
0168 };
0169 
0170 static const struct regmap_access_table chipone_dsi_readable_table = {
0171     .yes_ranges = chipone_dsi_readable_ranges,
0172     .n_yes_ranges = ARRAY_SIZE(chipone_dsi_readable_ranges),
0173 };
0174 
0175 static const struct regmap_range chipone_dsi_writeable_ranges[] = {
0176     regmap_reg_range(CONFIG_FINISH, PLL_SSC_OFFSET(3)),
0177     regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),
0178     regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),
0179     regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),
0180     regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),
0181     regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)),
0182     regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),
0183     regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)),
0184     regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)),
0185 };
0186 
0187 static const struct regmap_access_table chipone_dsi_writeable_table = {
0188     .yes_ranges = chipone_dsi_writeable_ranges,
0189     .n_yes_ranges = ARRAY_SIZE(chipone_dsi_writeable_ranges),
0190 };
0191 
0192 static const struct regmap_config chipone_regmap_config = {
0193     .reg_bits = 8,
0194     .val_bits = 8,
0195     .rd_table = &chipone_dsi_readable_table,
0196     .wr_table = &chipone_dsi_writeable_table,
0197     .cache_type = REGCACHE_RBTREE,
0198     .max_register = MIPI_ATE_STATUS(1),
0199 };
0200 
0201 static int chipone_dsi_read(void *context,
0202                 const void *reg, size_t reg_size,
0203                 void *val, size_t val_size)
0204 {
0205     struct mipi_dsi_device *dsi = context;
0206     const u16 reg16 = (val_size << 8) | *(u8 *)reg;
0207     int ret;
0208 
0209     ret = mipi_dsi_generic_read(dsi, &reg16, 2, val, val_size);
0210 
0211     return ret == val_size ? 0 : -EINVAL;
0212 }
0213 
0214 static int chipone_dsi_write(void *context, const void *data, size_t count)
0215 {
0216     struct mipi_dsi_device *dsi = context;
0217 
0218     return mipi_dsi_generic_write(dsi, data, 2);
0219 }
0220 
0221 static const struct regmap_bus chipone_dsi_regmap_bus = {
0222     .read               = chipone_dsi_read,
0223     .write              = chipone_dsi_write,
0224     .reg_format_endian_default  = REGMAP_ENDIAN_NATIVE,
0225     .val_format_endian_default  = REGMAP_ENDIAN_NATIVE,
0226 };
0227 
0228 static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
0229 {
0230     return container_of(bridge, struct chipone, bridge);
0231 }
0232 
0233 static void chipone_readb(struct chipone *icn, u8 reg, u8 *val)
0234 {
0235     int ret, pval;
0236 
0237     ret = regmap_read(icn->regmap, reg, &pval);
0238 
0239     *val = ret ? 0 : pval & 0xff;
0240 }
0241 
0242 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)
0243 {
0244     return regmap_write(icn->regmap, reg, val);
0245 }
0246 
0247 static void chipone_configure_pll(struct chipone *icn,
0248                   const struct drm_display_mode *mode)
0249 {
0250     unsigned int best_p = 0, best_m = 0, best_s = 0;
0251     unsigned int mode_clock = mode->clock * 1000;
0252     unsigned int delta, min_delta = 0xffffffff;
0253     unsigned int freq_p, freq_s, freq_out;
0254     unsigned int p_min, p_max;
0255     unsigned int p, m, s;
0256     unsigned int fin;
0257     bool best_p_pot;
0258     u8 ref_div;
0259 
0260     /*
0261      * DSI byte clock frequency (input into PLL) is calculated as:
0262      *  DSI_CLK = mode clock * bpp / dsi_data_lanes / 8
0263      *
0264      * DPI pixel clock frequency (output from PLL) is mode clock.
0265      *
0266      * The chip contains fractional PLL which works as follows:
0267      *  DPI_CLK = ((DSI_CLK / P) * M) / S
0268      * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider
0269      *                   register PLL_REF_DIV[4] is extra 1:2 divider
0270      * M is integer multiplier, register PLL_INT(0) is multiplier
0271      * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider
0272      *
0273      * It seems the PLL input clock after applying P pre-divider have
0274      * to be lower than 20 MHz.
0275      */
0276     fin = mode_clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) /
0277           icn->dsi->lanes / 8; /* in Hz */
0278 
0279     /* Minimum value of P predivider for PLL input in 5..20 MHz */
0280     p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U);
0281     p_max = clamp(fin / 5000000, 1U, 31U);
0282 
0283     for (p = p_min; p < p_max; p++) {   /* PLL_REF_DIV[4,3:0] */
0284         if (p > 16 && p & 1)        /* P > 16 uses extra /2 */
0285             continue;
0286         freq_p = fin / p;
0287         if (freq_p == 0)        /* Divider too high */
0288             break;
0289 
0290         for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */
0291             freq_s = freq_p / BIT(s + 1);
0292             if (freq_s == 0)    /* Divider too high */
0293                 break;
0294 
0295             m = mode_clock / freq_s;
0296 
0297             /* Multiplier is 8 bit */
0298             if (m > 0xff)
0299                 continue;
0300 
0301             /* Limit PLL VCO frequency to 1 GHz */
0302             freq_out = (fin * m) / p;
0303             if (freq_out > 1000000000)
0304                 continue;
0305 
0306             /* Apply post-divider */
0307             freq_out /= BIT(s + 1);
0308 
0309             delta = abs(mode_clock - freq_out);
0310             if (delta < min_delta) {
0311                 best_p = p;
0312                 best_m = m;
0313                 best_s = s;
0314                 min_delta = delta;
0315             }
0316         }
0317     }
0318 
0319     best_p_pot = !(best_p & 1);
0320 
0321     dev_dbg(icn->dev,
0322         "PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in=%d Hz ; DPI f_out=%d Hz\n",
0323         best_p >> best_p_pot, best_p_pot, best_m, best_s + 1,
0324         min_delta, fin, (fin * best_m) / (best_p << (best_s + 1)));
0325 
0326     ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s);
0327     if (best_p_pot) /* Prefer /2 pre-divider */
0328         ref_div |= PLL_REF_DIV_Pe;
0329 
0330     /* Clock source selection fixed to MIPI DSI clock lane */
0331     chipone_writeb(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK);
0332     chipone_writeb(icn, PLL_REF_DIV, ref_div);
0333     chipone_writeb(icn, PLL_INT(0), best_m);
0334 }
0335 
0336 static void chipone_atomic_enable(struct drm_bridge *bridge,
0337                   struct drm_bridge_state *old_bridge_state)
0338 {
0339     struct chipone *icn = bridge_to_chipone(bridge);
0340     struct drm_atomic_state *state = old_bridge_state->base.state;
0341     struct drm_display_mode *mode = &icn->mode;
0342     const struct drm_bridge_state *bridge_state;
0343     u16 hfp, hbp, hsync;
0344     u32 bus_flags;
0345     u8 pol, sys_ctrl_1, id[4];
0346 
0347     chipone_readb(icn, VENDOR_ID, id);
0348     chipone_readb(icn, DEVICE_ID_H, id + 1);
0349     chipone_readb(icn, DEVICE_ID_L, id + 2);
0350     chipone_readb(icn, VERSION_ID, id + 3);
0351 
0352     dev_dbg(icn->dev,
0353         "Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n",
0354         id[0], id[1], id[2], id[3]);
0355 
0356     if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) {
0357         dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");
0358         return;
0359     }
0360 
0361     /* Get the DPI flags from the bridge state. */
0362     bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
0363     bus_flags = bridge_state->output_bus_cfg.flags;
0364 
0365     if (icn->interface_i2c)
0366         chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);
0367     else
0368         chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
0369 
0370     chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);
0371 
0372     chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);
0373 
0374     /*
0375      * lsb nibble: 2nd nibble of hdisplay
0376      * msb nibble: 2nd nibble of vdisplay
0377      */
0378     chipone_writeb(icn, VACTIVE_HACTIVE_HI,
0379                ((mode->hdisplay >> 8) & 0xf) |
0380                (((mode->vdisplay >> 8) & 0xf) << 4));
0381 
0382     hfp = mode->hsync_start - mode->hdisplay;
0383     hsync = mode->hsync_end - mode->hsync_start;
0384     hbp = mode->htotal - mode->hsync_end;
0385 
0386     chipone_writeb(icn, HFP_LI, hfp & 0xff);
0387     chipone_writeb(icn, HSYNC_LI, hsync & 0xff);
0388     chipone_writeb(icn, HBP_LI, hbp & 0xff);
0389     /* Top two bits of Horizontal Front porch/Sync/Back porch */
0390     chipone_writeb(icn, HFP_HSW_HBP_HI,
0391                HFP_HSW_HBP_HI_HFP(hfp) |
0392                HFP_HSW_HBP_HI_HS(hsync) |
0393                HFP_HSW_HBP_HI_HBP(hbp));
0394 
0395     chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);
0396 
0397     chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);
0398 
0399     chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);
0400 
0401     /* dsi specific sequence */
0402     chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);
0403     chipone_writeb(icn, HFP_MIN, hfp & 0xff);
0404 
0405     /* DSI data lane count */
0406     chipone_writeb(icn, DSI_CTRL,
0407                DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));
0408 
0409     chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);
0410     chipone_writeb(icn, PLL_CTRL(12), 0xff);
0411     chipone_writeb(icn, MIPI_PN_SWAP, 0x00);
0412 
0413     /* DPI HS/VS/DE polarity */
0414     pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) |
0415           ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) |
0416           ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0);
0417     chipone_writeb(icn, BIST_POL, pol);
0418 
0419     /* Configure PLL settings */
0420     chipone_configure_pll(icn, mode);
0421 
0422     chipone_writeb(icn, SYS_CTRL(0), 0x40);
0423     sys_ctrl_1 = 0x88;
0424 
0425     if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
0426         sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_0);
0427     else
0428         sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_1_2);
0429 
0430     chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1);
0431 
0432     /* icn6211 specific sequence */
0433     chipone_writeb(icn, MIPI_FORCE_0, 0x20);
0434     chipone_writeb(icn, PLL_CTRL(1), 0x20);
0435     chipone_writeb(icn, CONFIG_FINISH, 0x10);
0436 
0437     usleep_range(10000, 11000);
0438 }
0439 
0440 static void chipone_atomic_pre_enable(struct drm_bridge *bridge,
0441                       struct drm_bridge_state *old_bridge_state)
0442 {
0443     struct chipone *icn = bridge_to_chipone(bridge);
0444     int ret;
0445 
0446     if (icn->vdd1) {
0447         ret = regulator_enable(icn->vdd1);
0448         if (ret)
0449             DRM_DEV_ERROR(icn->dev,
0450                       "failed to enable VDD1 regulator: %d\n", ret);
0451     }
0452 
0453     if (icn->vdd2) {
0454         ret = regulator_enable(icn->vdd2);
0455         if (ret)
0456             DRM_DEV_ERROR(icn->dev,
0457                       "failed to enable VDD2 regulator: %d\n", ret);
0458     }
0459 
0460     if (icn->vdd3) {
0461         ret = regulator_enable(icn->vdd3);
0462         if (ret)
0463             DRM_DEV_ERROR(icn->dev,
0464                       "failed to enable VDD3 regulator: %d\n", ret);
0465     }
0466 
0467     gpiod_set_value(icn->enable_gpio, 1);
0468 
0469     usleep_range(10000, 11000);
0470 }
0471 
0472 static void chipone_atomic_post_disable(struct drm_bridge *bridge,
0473                     struct drm_bridge_state *old_bridge_state)
0474 {
0475     struct chipone *icn = bridge_to_chipone(bridge);
0476 
0477     if (icn->vdd1)
0478         regulator_disable(icn->vdd1);
0479 
0480     if (icn->vdd2)
0481         regulator_disable(icn->vdd2);
0482 
0483     if (icn->vdd3)
0484         regulator_disable(icn->vdd3);
0485 
0486     gpiod_set_value(icn->enable_gpio, 0);
0487 }
0488 
0489 static void chipone_mode_set(struct drm_bridge *bridge,
0490                  const struct drm_display_mode *mode,
0491                  const struct drm_display_mode *adjusted_mode)
0492 {
0493     struct chipone *icn = bridge_to_chipone(bridge);
0494 
0495     drm_mode_copy(&icn->mode, adjusted_mode);
0496 };
0497 
0498 static int chipone_dsi_attach(struct chipone *icn)
0499 {
0500     struct mipi_dsi_device *dsi = icn->dsi;
0501     struct device *dev = icn->dev;
0502     int dsi_lanes, ret;
0503 
0504     dsi_lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);
0505 
0506     /*
0507      * If the 'data-lanes' property does not exist in DT or is invalid,
0508      * default to previously hard-coded behavior, which was 4 data lanes.
0509      */
0510     if (dsi_lanes < 0)
0511         icn->dsi->lanes = 4;
0512     else
0513         icn->dsi->lanes = dsi_lanes;
0514 
0515     dsi->format = MIPI_DSI_FMT_RGB888;
0516     dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
0517               MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;
0518 
0519     ret = mipi_dsi_attach(dsi);
0520     if (ret < 0)
0521         dev_err(icn->dev, "failed to attach dsi\n");
0522 
0523     return ret;
0524 }
0525 
0526 static int chipone_dsi_host_attach(struct chipone *icn)
0527 {
0528     struct device *dev = icn->dev;
0529     struct device_node *host_node;
0530     struct device_node *endpoint;
0531     struct mipi_dsi_device *dsi;
0532     struct mipi_dsi_host *host;
0533     int ret = 0;
0534 
0535     const struct mipi_dsi_device_info info = {
0536         .type = "chipone",
0537         .channel = 0,
0538         .node = NULL,
0539     };
0540 
0541     endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
0542     host_node = of_graph_get_remote_port_parent(endpoint);
0543     of_node_put(endpoint);
0544 
0545     if (!host_node)
0546         return -EINVAL;
0547 
0548     host = of_find_mipi_dsi_host_by_node(host_node);
0549     of_node_put(host_node);
0550     if (!host) {
0551         dev_err(dev, "failed to find dsi host\n");
0552         return -EPROBE_DEFER;
0553     }
0554 
0555     dsi = mipi_dsi_device_register_full(host, &info);
0556     if (IS_ERR(dsi)) {
0557         return dev_err_probe(dev, PTR_ERR(dsi),
0558                      "failed to create dsi device\n");
0559     }
0560 
0561     icn->dsi = dsi;
0562 
0563     ret = chipone_dsi_attach(icn);
0564     if (ret < 0)
0565         mipi_dsi_device_unregister(dsi);
0566 
0567     return ret;
0568 }
0569 
0570 static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
0571 {
0572     struct chipone *icn = bridge_to_chipone(bridge);
0573 
0574     return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);
0575 }
0576 
0577 #define MAX_INPUT_SEL_FORMATS   1
0578 
0579 static u32 *
0580 chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
0581                   struct drm_bridge_state *bridge_state,
0582                   struct drm_crtc_state *crtc_state,
0583                   struct drm_connector_state *conn_state,
0584                   u32 output_fmt,
0585                   unsigned int *num_input_fmts)
0586 {
0587     u32 *input_fmts;
0588 
0589     *num_input_fmts = 0;
0590 
0591     input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
0592                  GFP_KERNEL);
0593     if (!input_fmts)
0594         return NULL;
0595 
0596     /* This is the DSI-end bus format */
0597     input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
0598     *num_input_fmts = 1;
0599 
0600     return input_fmts;
0601 }
0602 
0603 static const struct drm_bridge_funcs chipone_bridge_funcs = {
0604     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
0605     .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
0606     .atomic_reset       = drm_atomic_helper_bridge_reset,
0607     .atomic_pre_enable  = chipone_atomic_pre_enable,
0608     .atomic_enable      = chipone_atomic_enable,
0609     .atomic_post_disable    = chipone_atomic_post_disable,
0610     .mode_set       = chipone_mode_set,
0611     .attach         = chipone_attach,
0612     .atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts,
0613 };
0614 
0615 static int chipone_parse_dt(struct chipone *icn)
0616 {
0617     struct device *dev = icn->dev;
0618     int ret;
0619 
0620     icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
0621     if (IS_ERR(icn->vdd1)) {
0622         ret = PTR_ERR(icn->vdd1);
0623         if (ret == -EPROBE_DEFER)
0624             return -EPROBE_DEFER;
0625         icn->vdd1 = NULL;
0626         DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret);
0627     }
0628 
0629     icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
0630     if (IS_ERR(icn->vdd2)) {
0631         ret = PTR_ERR(icn->vdd2);
0632         if (ret == -EPROBE_DEFER)
0633             return -EPROBE_DEFER;
0634         icn->vdd2 = NULL;
0635         DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret);
0636     }
0637 
0638     icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
0639     if (IS_ERR(icn->vdd3)) {
0640         ret = PTR_ERR(icn->vdd3);
0641         if (ret == -EPROBE_DEFER)
0642             return -EPROBE_DEFER;
0643         icn->vdd3 = NULL;
0644         DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret);
0645     }
0646 
0647     icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
0648     if (IS_ERR(icn->enable_gpio)) {
0649         DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");
0650         return PTR_ERR(icn->enable_gpio);
0651     }
0652 
0653     icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
0654     if (IS_ERR(icn->panel_bridge))
0655         return PTR_ERR(icn->panel_bridge);
0656 
0657     return 0;
0658 }
0659 
0660 static int chipone_common_probe(struct device *dev, struct chipone **icnr)
0661 {
0662     struct chipone *icn;
0663     int ret;
0664 
0665     icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
0666     if (!icn)
0667         return -ENOMEM;
0668 
0669     icn->dev = dev;
0670 
0671     ret = chipone_parse_dt(icn);
0672     if (ret)
0673         return ret;
0674 
0675     icn->bridge.funcs = &chipone_bridge_funcs;
0676     icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
0677     icn->bridge.of_node = dev->of_node;
0678 
0679     *icnr = icn;
0680 
0681     return ret;
0682 }
0683 
0684 static int chipone_dsi_probe(struct mipi_dsi_device *dsi)
0685 {
0686     struct device *dev = &dsi->dev;
0687     struct chipone *icn;
0688     int ret;
0689 
0690     ret = chipone_common_probe(dev, &icn);
0691     if (ret)
0692         return ret;
0693 
0694     icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,
0695                        dsi, &chipone_regmap_config);
0696     if (IS_ERR(icn->regmap))
0697         return PTR_ERR(icn->regmap);
0698 
0699     icn->interface_i2c = false;
0700     icn->dsi = dsi;
0701 
0702     mipi_dsi_set_drvdata(dsi, icn);
0703 
0704     drm_bridge_add(&icn->bridge);
0705 
0706     ret = chipone_dsi_attach(icn);
0707     if (ret)
0708         drm_bridge_remove(&icn->bridge);
0709 
0710     return ret;
0711 }
0712 
0713 static int chipone_i2c_probe(struct i2c_client *client,
0714                  const struct i2c_device_id *id)
0715 {
0716     struct device *dev = &client->dev;
0717     struct chipone *icn;
0718     int ret;
0719 
0720     ret = chipone_common_probe(dev, &icn);
0721     if (ret)
0722         return ret;
0723 
0724     icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);
0725     if (IS_ERR(icn->regmap))
0726         return PTR_ERR(icn->regmap);
0727 
0728     icn->interface_i2c = true;
0729     icn->client = client;
0730     dev_set_drvdata(dev, icn);
0731     i2c_set_clientdata(client, icn);
0732 
0733     drm_bridge_add(&icn->bridge);
0734 
0735     return chipone_dsi_host_attach(icn);
0736 }
0737 
0738 static int chipone_dsi_remove(struct mipi_dsi_device *dsi)
0739 {
0740     struct chipone *icn = mipi_dsi_get_drvdata(dsi);
0741 
0742     mipi_dsi_detach(dsi);
0743     drm_bridge_remove(&icn->bridge);
0744 
0745     return 0;
0746 }
0747 
0748 static const struct of_device_id chipone_of_match[] = {
0749     { .compatible = "chipone,icn6211", },
0750     { /* sentinel */ }
0751 };
0752 MODULE_DEVICE_TABLE(of, chipone_of_match);
0753 
0754 static struct mipi_dsi_driver chipone_dsi_driver = {
0755     .probe = chipone_dsi_probe,
0756     .remove = chipone_dsi_remove,
0757     .driver = {
0758         .name = "chipone-icn6211",
0759         .owner = THIS_MODULE,
0760         .of_match_table = chipone_of_match,
0761     },
0762 };
0763 
0764 static struct i2c_device_id chipone_i2c_id[] = {
0765     { "chipone,icn6211" },
0766     {},
0767 };
0768 MODULE_DEVICE_TABLE(i2c, chipone_i2c_id);
0769 
0770 static struct i2c_driver chipone_i2c_driver = {
0771     .probe = chipone_i2c_probe,
0772     .id_table = chipone_i2c_id,
0773     .driver = {
0774         .name = "chipone-icn6211-i2c",
0775         .of_match_table = chipone_of_match,
0776     },
0777 };
0778 
0779 static int __init chipone_init(void)
0780 {
0781     if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
0782         mipi_dsi_driver_register(&chipone_dsi_driver);
0783 
0784     return i2c_add_driver(&chipone_i2c_driver);
0785 }
0786 module_init(chipone_init);
0787 
0788 static void __exit chipone_exit(void)
0789 {
0790     i2c_del_driver(&chipone_i2c_driver);
0791 
0792     if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
0793         mipi_dsi_driver_unregister(&chipone_dsi_driver);
0794 }
0795 module_exit(chipone_exit);
0796 
0797 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
0798 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");
0799 MODULE_LICENSE("GPL");
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