bridge/cadence/cdns-mhdp8546-j721e.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * TI j721e Cadence MHDP8546 DP wrapper
0004  *
0005  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
0006  * Author: Jyri Sarha <jsarha@ti.com>
0007  */
0008
0009 #include <linux/io.h>
0010 #include <linux/platform_device.h>
0011
0012 #include "cdns-mhdp8546-j721e.h"
0013
0014 #define REVISION            0x00
0015 #define DPTX_IPCFG          0x04
0016 #define ECC_MEM_CFG         0x08
0017 #define DPTX_DSC_CFG            0x0c
0018 #define DPTX_SRC_CFG            0x10
0019 #define DPTX_VIF_SECURE_MODE_CFG    0x14
0020 #define DPTX_VIF_CONN_STATUS        0x18
0021 #define PHY_CLK_STATUS          0x1c
0022
0023 #define DPTX_SRC_AIF_EN         BIT(16)
0024 #define DPTX_SRC_VIF_3_IN30B        BIT(11)
0025 #define DPTX_SRC_VIF_2_IN30B        BIT(10)
0026 #define DPTX_SRC_VIF_1_IN30B        BIT(9)
0027 #define DPTX_SRC_VIF_0_IN30B        BIT(8)
0028 #define DPTX_SRC_VIF_3_SEL_DPI5     BIT(7)
0029 #define DPTX_SRC_VIF_3_SEL_DPI3     0
0030 #define DPTX_SRC_VIF_2_SEL_DPI4     BIT(6)
0031 #define DPTX_SRC_VIF_2_SEL_DPI2     0
0032 #define DPTX_SRC_VIF_1_SEL_DPI3     BIT(5)
0033 #define DPTX_SRC_VIF_1_SEL_DPI1     0
0034 #define DPTX_SRC_VIF_0_SEL_DPI2     BIT(4)
0035 #define DPTX_SRC_VIF_0_SEL_DPI0     0
0036 #define DPTX_SRC_VIF_3_EN       BIT(3)
0037 #define DPTX_SRC_VIF_2_EN       BIT(2)
0038 #define DPTX_SRC_VIF_1_EN       BIT(1)
0039 #define DPTX_SRC_VIF_0_EN       BIT(0)
0040
0041 /* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
0042
0043 static int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
0044 {
0045     struct platform_device *pdev = to_platform_device(mhdp->dev);
0046
0047     mhdp->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
0048     return PTR_ERR_OR_ZERO(mhdp->j721e_regs);
0049 }
0050
0051 static void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
0052 {
0053     /*
0054      * Enable VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
0055      * to eDP DPI2. This is the only supported SST configuration on
0056      * J721E.
0057      */
0058     writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
0059            mhdp->j721e_regs + DPTX_SRC_CFG);
0060 }
0061
0062 static void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
0063 {
0064     /* Put everything to defaults  */
0065     writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
0066 }
0067
0068 const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
0069     .init = cdns_mhdp_j721e_init,
0070     .enable = cdns_mhdp_j721e_enable,
0071     .disable = cdns_mhdp_j721e_disable,
0072 };
0073
0074 const struct drm_bridge_timings mhdp_ti_j721e_bridge_timings = {
0075     .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
0076                DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE |
0077                DRM_BUS_FLAG_DE_HIGH,
0078 };