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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
0004  *
0005  */
0006 #include <linux/gcd.h>
0007 #include <linux/gpio/consumer.h>
0008 #include <linux/i2c.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/mutex.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/slab.h>
0017 #include <linux/types.h>
0018 #include <linux/workqueue.h>
0019 
0020 #include <linux/of_gpio.h>
0021 #include <linux/of_graph.h>
0022 #include <linux/of_platform.h>
0023 
0024 #include <drm/display/drm_dp_aux_bus.h>
0025 #include <drm/display/drm_dp_helper.h>
0026 #include <drm/display/drm_hdcp_helper.h>
0027 #include <drm/drm_atomic_helper.h>
0028 #include <drm/drm_bridge.h>
0029 #include <drm/drm_crtc_helper.h>
0030 #include <drm/drm_edid.h>
0031 #include <drm/drm_mipi_dsi.h>
0032 #include <drm/drm_of.h>
0033 #include <drm/drm_panel.h>
0034 #include <drm/drm_print.h>
0035 #include <drm/drm_probe_helper.h>
0036 
0037 #include <media/v4l2-fwnode.h>
0038 #include <sound/hdmi-codec.h>
0039 #include <video/display_timing.h>
0040 
0041 #include "anx7625.h"
0042 
0043 /*
0044  * There is a sync issue while access I2C register between AP(CPU) and
0045  * internal firmware(OCM), to avoid the race condition, AP should access
0046  * the reserved slave address before slave address occurs changes.
0047  */
0048 static int i2c_access_workaround(struct anx7625_data *ctx,
0049                  struct i2c_client *client)
0050 {
0051     u8 offset;
0052     struct device *dev = &client->dev;
0053     int ret;
0054 
0055     if (client == ctx->last_client)
0056         return 0;
0057 
0058     ctx->last_client = client;
0059 
0060     if (client == ctx->i2c.tcpc_client)
0061         offset = RSVD_00_ADDR;
0062     else if (client == ctx->i2c.tx_p0_client)
0063         offset = RSVD_D1_ADDR;
0064     else if (client == ctx->i2c.tx_p1_client)
0065         offset = RSVD_60_ADDR;
0066     else if (client == ctx->i2c.rx_p0_client)
0067         offset = RSVD_39_ADDR;
0068     else if (client == ctx->i2c.rx_p1_client)
0069         offset = RSVD_7F_ADDR;
0070     else
0071         offset = RSVD_00_ADDR;
0072 
0073     ret = i2c_smbus_write_byte_data(client, offset, 0x00);
0074     if (ret < 0)
0075         DRM_DEV_ERROR(dev,
0076                   "fail to access i2c id=%x\n:%x",
0077                   client->addr, offset);
0078 
0079     return ret;
0080 }
0081 
0082 static int anx7625_reg_read(struct anx7625_data *ctx,
0083                 struct i2c_client *client, u8 reg_addr)
0084 {
0085     int ret;
0086     struct device *dev = &client->dev;
0087 
0088     i2c_access_workaround(ctx, client);
0089 
0090     ret = i2c_smbus_read_byte_data(client, reg_addr);
0091     if (ret < 0)
0092         DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
0093                   client->addr, reg_addr);
0094 
0095     return ret;
0096 }
0097 
0098 static int anx7625_reg_block_read(struct anx7625_data *ctx,
0099                   struct i2c_client *client,
0100                   u8 reg_addr, u8 len, u8 *buf)
0101 {
0102     int ret;
0103     struct device *dev = &client->dev;
0104 
0105     i2c_access_workaround(ctx, client);
0106 
0107     ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf);
0108     if (ret < 0)
0109         DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
0110                   client->addr, reg_addr);
0111 
0112     return ret;
0113 }
0114 
0115 static int anx7625_reg_write(struct anx7625_data *ctx,
0116                  struct i2c_client *client,
0117                  u8 reg_addr, u8 reg_val)
0118 {
0119     int ret;
0120     struct device *dev = &client->dev;
0121 
0122     i2c_access_workaround(ctx, client);
0123 
0124     ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);
0125 
0126     if (ret < 0)
0127         DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
0128                   client->addr, reg_addr);
0129 
0130     return ret;
0131 }
0132 
0133 static int anx7625_reg_block_write(struct anx7625_data *ctx,
0134                    struct i2c_client *client,
0135                    u8 reg_addr, u8 len, u8 *buf)
0136 {
0137     int ret;
0138     struct device *dev = &client->dev;
0139 
0140     i2c_access_workaround(ctx, client);
0141 
0142     ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf);
0143     if (ret < 0)
0144         dev_err(dev, "write i2c block failed id=%x\n:%x",
0145             client->addr, reg_addr);
0146 
0147     return ret;
0148 }
0149 
0150 static int anx7625_write_or(struct anx7625_data *ctx,
0151                 struct i2c_client *client,
0152                 u8 offset, u8 mask)
0153 {
0154     int val;
0155 
0156     val = anx7625_reg_read(ctx, client, offset);
0157     if (val < 0)
0158         return val;
0159 
0160     return anx7625_reg_write(ctx, client, offset, (val | (mask)));
0161 }
0162 
0163 static int anx7625_write_and(struct anx7625_data *ctx,
0164                  struct i2c_client *client,
0165                  u8 offset, u8 mask)
0166 {
0167     int val;
0168 
0169     val = anx7625_reg_read(ctx, client, offset);
0170     if (val < 0)
0171         return val;
0172 
0173     return anx7625_reg_write(ctx, client, offset, (val & (mask)));
0174 }
0175 
0176 static int anx7625_write_and_or(struct anx7625_data *ctx,
0177                 struct i2c_client *client,
0178                 u8 offset, u8 and_mask, u8 or_mask)
0179 {
0180     int val;
0181 
0182     val = anx7625_reg_read(ctx, client, offset);
0183     if (val < 0)
0184         return val;
0185 
0186     return anx7625_reg_write(ctx, client,
0187                  offset, (val & and_mask) | (or_mask));
0188 }
0189 
0190 static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
0191 {
0192     int i, ret;
0193 
0194     ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
0195                    AUDIO_CONTROL_REGISTER, 0x80);
0196     for (i = 0; i < 13; i++)
0197         ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
0198                      VIDEO_BIT_MATRIX_12 + i,
0199                      0x18 + i);
0200 
0201     return ret;
0202 }
0203 
0204 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
0205 {
0206     return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
0207 }
0208 
0209 static int wait_aux_op_finish(struct anx7625_data *ctx)
0210 {
0211     struct device *dev = &ctx->client->dev;
0212     int val;
0213     int ret;
0214 
0215     ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
0216                  ctx, val,
0217                  (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
0218                  2000,
0219                  2000 * 150);
0220     if (ret) {
0221         DRM_DEV_ERROR(dev, "aux operation fail!\n");
0222         return -EIO;
0223     }
0224 
0225     val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
0226                    AP_AUX_CTRL_STATUS);
0227     if (val < 0 || (val & 0x0F)) {
0228         DRM_DEV_ERROR(dev, "aux status %02x\n", val);
0229         return -EIO;
0230     }
0231 
0232     return 0;
0233 }
0234 
0235 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address,
0236                  u8 len, u8 *buf)
0237 {
0238     struct device *dev = &ctx->client->dev;
0239     int ret;
0240     u8 addrh, addrm, addrl;
0241     u8 cmd;
0242     bool is_write = !(op & DP_AUX_I2C_READ);
0243 
0244     if (len > DP_AUX_MAX_PAYLOAD_BYTES) {
0245         dev_err(dev, "exceed aux buffer len.\n");
0246         return -EINVAL;
0247     }
0248 
0249     if (!len)
0250         return len;
0251 
0252     addrl = address & 0xFF;
0253     addrm = (address >> 8) & 0xFF;
0254     addrh = (address >> 16) & 0xFF;
0255 
0256     if (!is_write)
0257         op &= ~DP_AUX_I2C_MOT;
0258     cmd = DPCD_CMD(len, op);
0259 
0260     /* Set command and length */
0261     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0262                 AP_AUX_COMMAND, cmd);
0263 
0264     /* Set aux access address */
0265     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0266                  AP_AUX_ADDR_7_0, addrl);
0267     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0268                  AP_AUX_ADDR_15_8, addrm);
0269     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0270                  AP_AUX_ADDR_19_16, addrh);
0271 
0272     if (is_write)
0273         ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
0274                            AP_AUX_BUFF_START, len, buf);
0275     /* Enable aux access */
0276     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
0277                 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
0278 
0279     if (ret < 0) {
0280         dev_err(dev, "cannot access aux related register.\n");
0281         return -EIO;
0282     }
0283 
0284     ret = wait_aux_op_finish(ctx);
0285     if (ret < 0) {
0286         dev_err(dev, "aux IO error: wait aux op finish.\n");
0287         return ret;
0288     }
0289 
0290     /* Write done */
0291     if (is_write)
0292         return len;
0293 
0294     /* Read done, read out dpcd data */
0295     ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
0296                      AP_AUX_BUFF_START, len, buf);
0297     if (ret < 0) {
0298         dev_err(dev, "read dpcd register failed\n");
0299         return -EIO;
0300     }
0301 
0302     return len;
0303 }
0304 
0305 static int anx7625_video_mute_control(struct anx7625_data *ctx,
0306                       u8 status)
0307 {
0308     int ret;
0309 
0310     if (status) {
0311         /* Set mute on flag */
0312         ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
0313                        AP_AV_STATUS, AP_MIPI_MUTE);
0314         /* Clear mipi RX en */
0315         ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
0316                      AP_AV_STATUS, (u8)~AP_MIPI_RX_EN);
0317     } else {
0318         /* Mute off flag */
0319         ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
0320                     AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
0321         /* Set MIPI RX EN */
0322         ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
0323                     AP_AV_STATUS, AP_MIPI_RX_EN);
0324     }
0325 
0326     return ret;
0327 }
0328 
0329 /* Reduction of fraction a/b */
0330 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
0331 {
0332     unsigned long gcd_num;
0333     unsigned long tmp_a, tmp_b;
0334     u32 i = 1;
0335 
0336     gcd_num = gcd(*a, *b);
0337     *a /= gcd_num;
0338     *b /= gcd_num;
0339 
0340     tmp_a = *a;
0341     tmp_b = *b;
0342 
0343     while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
0344         i++;
0345         *a = tmp_a / i;
0346         *b = tmp_b / i;
0347     }
0348 
0349     /*
0350      * In the end, make a, b larger to have higher ODFC PLL
0351      * output frequency accuracy
0352      */
0353     while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
0354         *a <<= 1;
0355         *b <<= 1;
0356     }
0357 
0358     *a >>= 1;
0359     *b >>= 1;
0360 }
0361 
0362 static int anx7625_calculate_m_n(u32 pixelclock,
0363                  unsigned long *m,
0364                  unsigned long *n,
0365                  u8 *post_divider)
0366 {
0367     if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
0368         /* Pixel clock frequency is too high */
0369         DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
0370               pixelclock,
0371               PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
0372         return -EINVAL;
0373     }
0374 
0375     if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
0376         /* Pixel clock frequency is too low */
0377         DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
0378               pixelclock,
0379               PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
0380         return -EINVAL;
0381     }
0382 
0383     for (*post_divider = 1;
0384         pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
0385         *post_divider += 1;
0386 
0387     if (*post_divider > POST_DIVIDER_MAX) {
0388         for (*post_divider = 1;
0389             (pixelclock <
0390              (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
0391             *post_divider += 1;
0392 
0393         if (*post_divider > POST_DIVIDER_MAX) {
0394             DRM_ERROR("cannot find property post_divider(%d)\n",
0395                   *post_divider);
0396             return -EDOM;
0397         }
0398     }
0399 
0400     /* Patch to improve the accuracy */
0401     if (*post_divider == 7) {
0402         /* 27,000,000 is not divisible by 7 */
0403         *post_divider = 8;
0404     } else if (*post_divider == 11) {
0405         /* 27,000,000 is not divisible by 11 */
0406         *post_divider = 12;
0407     } else if ((*post_divider == 13) || (*post_divider == 14)) {
0408         /* 27,000,000 is not divisible by 13 or 14 */
0409         *post_divider = 15;
0410     }
0411 
0412     if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
0413         DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
0414               pixelclock * (*post_divider),
0415               PLL_OUT_FREQ_ABS_MAX);
0416         return -EDOM;
0417     }
0418 
0419     *m = pixelclock;
0420     *n = XTAL_FRQ / (*post_divider);
0421 
0422     anx7625_reduction_of_a_fraction(m, n);
0423 
0424     return 0;
0425 }
0426 
0427 static int anx7625_odfc_config(struct anx7625_data *ctx,
0428                    u8 post_divider)
0429 {
0430     int ret;
0431     struct device *dev = &ctx->client->dev;
0432 
0433     /* Config input reference clock frequency 27MHz/19.2MHz */
0434     ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
0435                 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
0436     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
0437                 (REF_CLK_27000KHZ << MIPI_FREF_D_IND));
0438     /* Post divider */
0439     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
0440                  MIPI_DIGITAL_PLL_8, 0x0f);
0441     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
0442                 post_divider << 4);
0443 
0444     /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
0445     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
0446                  ~MIPI_PLL_VCO_TUNE_REG_VAL);
0447 
0448     /* Reset ODFC PLL */
0449     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
0450                  ~MIPI_PLL_RESET_N);
0451     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
0452                 MIPI_PLL_RESET_N);
0453 
0454     if (ret < 0)
0455         DRM_DEV_ERROR(dev, "IO error.\n");
0456 
0457     return ret;
0458 }
0459 
0460 /*
0461  * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
0462  * anx7625 defined K ratio for matching MIPI input video clock and
0463  * DP output video clock. Increase K value can match bigger video data
0464  * variation. IVO panel has small variation than DP CTS spec, need
0465  * decrease the K value.
0466  */
0467 static int anx7625_set_k_value(struct anx7625_data *ctx)
0468 {
0469     struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
0470 
0471     if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
0472         return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0473                      MIPI_DIGITAL_ADJ_1, 0x3B);
0474 
0475     return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0476                  MIPI_DIGITAL_ADJ_1, 0x3D);
0477 }
0478 
0479 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
0480 {
0481     struct device *dev = &ctx->client->dev;
0482     unsigned long m, n;
0483     u16 htotal;
0484     int ret;
0485     u8 post_divider = 0;
0486 
0487     ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
0488                     &m, &n, &post_divider);
0489 
0490     if (ret) {
0491         DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
0492         return ret;
0493     }
0494 
0495     DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
0496                  m, n, post_divider);
0497 
0498     /* Configure pixel clock */
0499     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
0500                 (ctx->dt.pixelclock.min / 1000) & 0xFF);
0501     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
0502                  (ctx->dt.pixelclock.min / 1000) >> 8);
0503     /* Lane count */
0504     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
0505             MIPI_LANE_CTRL_0, 0xfc);
0506     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
0507                 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
0508 
0509     /* Htotal */
0510     htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
0511         ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
0512     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0513             HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF);
0514     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0515             HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8);
0516     /* Hactive */
0517     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0518             HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
0519     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0520             HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
0521     /* HFP */
0522     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0523             HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
0524     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0525             HORIZONTAL_FRONT_PORCH_H,
0526             ctx->dt.hfront_porch.min >> 8);
0527     /* HWS */
0528     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0529             HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
0530     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0531             HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
0532     /* HBP */
0533     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0534             HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
0535     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0536             HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
0537     /* Vactive */
0538     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
0539             ctx->dt.vactive.min);
0540     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
0541             ctx->dt.vactive.min >> 8);
0542     /* VFP */
0543     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0544             VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
0545     /* VWS */
0546     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0547             VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
0548     /* VBP */
0549     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
0550             VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
0551     /* M value */
0552     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0553             MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
0554     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0555             MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
0556     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0557             MIPI_PLL_M_NUM_7_0, (m & 0xff));
0558     /* N value */
0559     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0560             MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff);
0561     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0562             MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
0563     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
0564             (n & 0xff));
0565 
0566     anx7625_set_k_value(ctx);
0567 
0568     ret |= anx7625_odfc_config(ctx, post_divider - 1);
0569 
0570     if (ret < 0)
0571         DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
0572 
0573     return ret;
0574 }
0575 
0576 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
0577 {
0578     int val;
0579     struct device *dev = &ctx->client->dev;
0580 
0581     /* Swap MIPI-DSI data lane 3 P and N */
0582     val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
0583     if (val < 0) {
0584         DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
0585         return -EIO;
0586     }
0587 
0588     val |= (1 << MIPI_SWAP_CH3);
0589     return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
0590 }
0591 
0592 static int anx7625_api_dsi_config(struct anx7625_data *ctx)
0593 
0594 {
0595     int val, ret;
0596     struct device *dev = &ctx->client->dev;
0597 
0598     /* Swap MIPI-DSI data lane 3 P and N */
0599     ret = anx7625_swap_dsi_lane3(ctx);
0600     if (ret < 0) {
0601         DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
0602         return ret;
0603     }
0604 
0605     /* DSI clock settings */
0606     val = (0 << MIPI_HS_PWD_CLK)        |
0607         (0 << MIPI_HS_RT_CLK)       |
0608         (0 << MIPI_PD_CLK)      |
0609         (1 << MIPI_CLK_RT_MANUAL_PD_EN) |
0610         (1 << MIPI_CLK_HS_MANUAL_PD_EN) |
0611         (0 << MIPI_CLK_DET_DET_BYPASS)  |
0612         (0 << MIPI_CLK_MISS_CTRL)   |
0613         (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
0614     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0615                 MIPI_PHY_CONTROL_3, val);
0616 
0617     /*
0618      * Decreased HS prepare timing delay from 160ns to 80ns work with
0619      *     a) Dragon board 810 series (Qualcomm AP)
0620      *     b) Moving Pixel DSI source (PG3A pattern generator +
0621      *  P332 D-PHY Probe) default D-PHY timing
0622      *  5ns/step
0623      */
0624     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0625                  MIPI_TIME_HS_PRPR, 0x10);
0626 
0627     /* Enable DSI mode*/
0628     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
0629                 SELECT_DSI << MIPI_DPI_SELECT);
0630 
0631     ret |= anx7625_dsi_video_timing_config(ctx);
0632     if (ret < 0) {
0633         DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
0634         return ret;
0635     }
0636 
0637     /* Toggle m, n ready */
0638     ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
0639                 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
0640     usleep_range(1000, 1100);
0641     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
0642                 MIPI_M_NUM_READY | MIPI_N_NUM_READY);
0643 
0644     /* Configure integer stable register */
0645     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0646                  MIPI_VIDEO_STABLE_CNT, 0x02);
0647     /* Power on MIPI RX */
0648     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0649                  MIPI_LANE_CTRL_10, 0x00);
0650     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0651                  MIPI_LANE_CTRL_10, 0x80);
0652 
0653     if (ret < 0)
0654         DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
0655 
0656     return ret;
0657 }
0658 
0659 static int anx7625_dsi_config(struct anx7625_data *ctx)
0660 {
0661     struct device *dev = &ctx->client->dev;
0662     int ret;
0663 
0664     DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
0665 
0666     /* DSC disable */
0667     ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
0668                 R_DSC_CTRL_0, ~DSC_EN);
0669 
0670     ret |= anx7625_api_dsi_config(ctx);
0671 
0672     if (ret < 0) {
0673         DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
0674         return ret;
0675     }
0676 
0677     /* Set MIPI RX EN */
0678     ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
0679                    AP_AV_STATUS, AP_MIPI_RX_EN);
0680     /* Clear mute flag */
0681     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
0682                  AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
0683     if (ret < 0)
0684         DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
0685     else
0686         DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
0687 
0688     return ret;
0689 }
0690 
0691 static int anx7625_api_dpi_config(struct anx7625_data *ctx)
0692 {
0693     struct device *dev = &ctx->client->dev;
0694     u16 freq = ctx->dt.pixelclock.min / 1000;
0695     int ret;
0696 
0697     /* configure pixel clock */
0698     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0699                 PIXEL_CLOCK_L, freq & 0xFF);
0700     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0701                  PIXEL_CLOCK_H, (freq >> 8));
0702 
0703     /* set DPI mode */
0704     /* set to DPI PLL module sel */
0705     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0706                  MIPI_DIGITAL_PLL_9, 0x20);
0707     /* power down MIPI */
0708     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0709                  MIPI_LANE_CTRL_10, 0x08);
0710     /* enable DPI mode */
0711     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
0712                  MIPI_DIGITAL_PLL_18, 0x1C);
0713     /* set first edge */
0714     ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
0715                  VIDEO_CONTROL_0, 0x06);
0716     if (ret < 0)
0717         DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
0718 
0719     return ret;
0720 }
0721 
0722 static int anx7625_dpi_config(struct anx7625_data *ctx)
0723 {
0724     struct device *dev = &ctx->client->dev;
0725     int ret;
0726 
0727     DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
0728 
0729     /* DSC disable */
0730     ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
0731                 R_DSC_CTRL_0, ~DSC_EN);
0732     if (ret < 0) {
0733         DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
0734         return ret;
0735     }
0736 
0737     ret = anx7625_config_bit_matrix(ctx);
0738     if (ret < 0) {
0739         DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
0740         return ret;
0741     }
0742 
0743     ret = anx7625_api_dpi_config(ctx);
0744     if (ret < 0) {
0745         DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
0746         return ret;
0747     }
0748 
0749     /* set MIPI RX EN */
0750     ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
0751                    AP_AV_STATUS, AP_MIPI_RX_EN);
0752     /* clear mute flag */
0753     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
0754                  AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
0755     if (ret < 0)
0756         DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
0757 
0758     return ret;
0759 }
0760 
0761 static int anx7625_read_flash_status(struct anx7625_data *ctx)
0762 {
0763     return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
0764 }
0765 
0766 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
0767 {
0768     int ret, val;
0769     struct device *dev = &ctx->client->dev;
0770     u8 ident[FLASH_BUF_LEN];
0771 
0772     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0773                 FLASH_ADDR_HIGH, 0x91);
0774     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0775                  FLASH_ADDR_LOW, 0xA0);
0776     if (ret < 0) {
0777         dev_err(dev, "IO error : set key flash address.\n");
0778         return ret;
0779     }
0780 
0781     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0782                 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
0783     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0784                  FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
0785     if (ret < 0) {
0786         dev_err(dev, "IO error : set key flash len.\n");
0787         return ret;
0788     }
0789 
0790     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0791                 R_FLASH_RW_CTRL, FLASH_READ);
0792     ret |= readx_poll_timeout(anx7625_read_flash_status,
0793                   ctx, val,
0794                   ((val & FLASH_DONE) || (val < 0)),
0795                   2000,
0796                   2000 * 150);
0797     if (ret) {
0798         dev_err(dev, "flash read access fail!\n");
0799         return -EIO;
0800     }
0801 
0802     ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
0803                      FLASH_BUF_BASE_ADDR,
0804                      FLASH_BUF_LEN, ident);
0805     if (ret < 0) {
0806         dev_err(dev, "read flash data fail!\n");
0807         return -EIO;
0808     }
0809 
0810     if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
0811         return -EINVAL;
0812 
0813     return 0;
0814 }
0815 
0816 static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
0817 {
0818     int ret;
0819     struct device *dev = &ctx->client->dev;
0820 
0821     /* Select HDCP 1.4 KEY */
0822     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0823                 R_BOOT_RETRY, 0x12);
0824     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0825                  FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
0826     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0827                  FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
0828     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0829                  R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
0830     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0831                  R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
0832 
0833     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0834                  R_RAM_ADDR_H, 0);
0835     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0836                  R_RAM_ADDR_L, 0);
0837     /* Enable HDCP 1.4 KEY load */
0838     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
0839                  R_RAM_CTRL, DECRYPT_EN | LOAD_START);
0840     dev_dbg(dev, "load HDCP 1.4 key done\n");
0841     return ret;
0842 }
0843 
0844 static int anx7625_hdcp_disable(struct anx7625_data *ctx)
0845 {
0846     int ret;
0847     struct device *dev = &ctx->client->dev;
0848 
0849     dev_dbg(dev, "disable HDCP 1.4\n");
0850 
0851     /* Disable HDCP */
0852     ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
0853     /* Try auth flag */
0854     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
0855     /* Interrupt for DRM */
0856     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
0857     if (ret < 0)
0858         dev_err(dev, "fail to disable HDCP\n");
0859 
0860     return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
0861                  TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
0862 }
0863 
0864 static int anx7625_hdcp_enable(struct anx7625_data *ctx)
0865 {
0866     u8 bcap;
0867     int ret;
0868     struct device *dev = &ctx->client->dev;
0869 
0870     ret = anx7625_hdcp_key_probe(ctx);
0871     if (ret) {
0872         dev_dbg(dev, "no key found, not to do hdcp\n");
0873         return ret;
0874     }
0875 
0876     /* Read downstream capability */
0877     ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap);
0878     if (ret < 0)
0879         return ret;
0880 
0881     if (!(bcap & 0x01)) {
0882         pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
0883         return 0;
0884     }
0885 
0886     dev_dbg(dev, "enable HDCP 1.4\n");
0887 
0888     /* First clear HDCP state */
0889     ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
0890                 TX_HDCP_CTRL0,
0891                 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
0892     usleep_range(1000, 1100);
0893     /* Second clear HDCP state */
0894     ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
0895                  TX_HDCP_CTRL0,
0896                  KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
0897 
0898     /* Set time for waiting KSVR */
0899     ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
0900                  SP_TX_WAIT_KSVR_TIME, 0xc8);
0901     /* Set time for waiting R0 */
0902     ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
0903                  SP_TX_WAIT_R0_TIME, 0xb0);
0904     ret |= anx7625_hdcp_key_load(ctx);
0905     if (ret) {
0906         pr_warn("prepare HDCP key failed.\n");
0907         return ret;
0908     }
0909 
0910     ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
0911 
0912     /* Try auth flag */
0913     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
0914     /* Interrupt for DRM */
0915     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
0916     if (ret < 0)
0917         dev_err(dev, "fail to enable HDCP\n");
0918 
0919     return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
0920                 TX_HDCP_CTRL0, HARD_AUTH_EN);
0921 }
0922 
0923 static void anx7625_dp_start(struct anx7625_data *ctx)
0924 {
0925     int ret;
0926     struct device *dev = &ctx->client->dev;
0927     u8 data;
0928 
0929     if (!ctx->display_timing_valid) {
0930         DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
0931         return;
0932     }
0933 
0934     dev_dbg(dev, "set downstream sink into normal\n");
0935     /* Downstream sink enter into normal mode */
0936     data = 1;
0937     ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
0938     if (ret < 0)
0939         dev_err(dev, "IO error : set sink into normal mode fail\n");
0940 
0941     /* Disable HDCP */
0942     anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
0943 
0944     if (ctx->pdata.is_dpi)
0945         ret = anx7625_dpi_config(ctx);
0946     else
0947         ret = anx7625_dsi_config(ctx);
0948 
0949     if (ret < 0)
0950         DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
0951 
0952     ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
0953 
0954     ctx->dp_en = 1;
0955 }
0956 
0957 static void anx7625_dp_stop(struct anx7625_data *ctx)
0958 {
0959     struct device *dev = &ctx->client->dev;
0960     int ret;
0961     u8 data;
0962 
0963     DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
0964 
0965     /*
0966      * Video disable: 0x72:08 bit 7 = 0;
0967      * Audio disable: 0x70:87 bit 0 = 0;
0968      */
0969     ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
0970     ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
0971 
0972     ret |= anx7625_video_mute_control(ctx, 1);
0973 
0974     dev_dbg(dev, "notify downstream enter into standby\n");
0975     /* Downstream monitor enter into standby mode */
0976     data = 2;
0977     ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
0978     if (ret < 0)
0979         DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
0980 
0981     ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
0982 
0983     ctx->dp_en = 0;
0984 }
0985 
0986 static int sp_tx_rst_aux(struct anx7625_data *ctx)
0987 {
0988     int ret;
0989 
0990     ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
0991                    AUX_RST);
0992     ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
0993                  ~AUX_RST);
0994     return ret;
0995 }
0996 
0997 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
0998 {
0999     int ret;
1000 
1001     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1002                 AP_AUX_BUFF_START, offset);
1003     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1004                  AP_AUX_COMMAND, 0x04);
1005     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1006                 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1007     return (ret | wait_aux_op_finish(ctx));
1008 }
1009 
1010 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
1011 {
1012     int ret;
1013 
1014     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1015                 AP_AUX_COMMAND, len_cmd);
1016     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1017                 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1018     return (ret | wait_aux_op_finish(ctx));
1019 }
1020 
1021 static int sp_tx_get_edid_block(struct anx7625_data *ctx)
1022 {
1023     int c = 0;
1024     struct device *dev = &ctx->client->dev;
1025 
1026     sp_tx_aux_wr(ctx, 0x7e);
1027     sp_tx_aux_rd(ctx, 0x01);
1028     c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1029     if (c < 0) {
1030         DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
1031         return -EIO;
1032     }
1033 
1034     DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
1035 
1036     if (c > MAX_EDID_BLOCK)
1037         c = 1;
1038 
1039     return c;
1040 }
1041 
1042 static int edid_read(struct anx7625_data *ctx,
1043              u8 offset, u8 *pblock_buf)
1044 {
1045     int ret, cnt;
1046     struct device *dev = &ctx->client->dev;
1047 
1048     for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1049         sp_tx_aux_wr(ctx, offset);
1050         /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1051         ret = sp_tx_aux_rd(ctx, 0xf1);
1052 
1053         if (ret) {
1054             ret = sp_tx_rst_aux(ctx);
1055             DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
1056         } else {
1057             ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1058                              AP_AUX_BUFF_START,
1059                              MAX_DPCD_BUFFER_SIZE,
1060                              pblock_buf);
1061             if (ret > 0)
1062                 break;
1063         }
1064     }
1065 
1066     if (cnt > EDID_TRY_CNT)
1067         return -EIO;
1068 
1069     return ret;
1070 }
1071 
1072 static int segments_edid_read(struct anx7625_data *ctx,
1073                   u8 segment, u8 *buf, u8 offset)
1074 {
1075     u8 cnt;
1076     int ret;
1077     struct device *dev = &ctx->client->dev;
1078 
1079     /* Write address only */
1080     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1081                 AP_AUX_ADDR_7_0, 0x30);
1082     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1083                  AP_AUX_COMMAND, 0x04);
1084     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1085                  AP_AUX_CTRL_STATUS,
1086                  AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
1087 
1088     ret |= wait_aux_op_finish(ctx);
1089     /* Write segment address */
1090     ret |= sp_tx_aux_wr(ctx, segment);
1091     /* Data read */
1092     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1093                  AP_AUX_ADDR_7_0, 0x50);
1094     if (ret) {
1095         DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
1096         return ret;
1097     }
1098 
1099     for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1100         sp_tx_aux_wr(ctx, offset);
1101         /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1102         ret = sp_tx_aux_rd(ctx, 0xf1);
1103 
1104         if (ret) {
1105             ret = sp_tx_rst_aux(ctx);
1106             DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
1107         } else {
1108             ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1109                              AP_AUX_BUFF_START,
1110                              MAX_DPCD_BUFFER_SIZE, buf);
1111             if (ret > 0)
1112                 break;
1113         }
1114     }
1115 
1116     if (cnt > EDID_TRY_CNT)
1117         return -EIO;
1118 
1119     return ret;
1120 }
1121 
1122 static int sp_tx_edid_read(struct anx7625_data *ctx,
1123                u8 *pedid_blocks_buf)
1124 {
1125     u8 offset;
1126     int edid_pos;
1127     int count, blocks_num;
1128     u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
1129     u8 i, j;
1130     int g_edid_break = 0;
1131     int ret;
1132     struct device *dev = &ctx->client->dev;
1133 
1134     /* Address initial */
1135     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1136                 AP_AUX_ADDR_7_0, 0x50);
1137     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1138                  AP_AUX_ADDR_15_8, 0);
1139     ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
1140                  AP_AUX_ADDR_19_16, 0xf0);
1141     if (ret < 0) {
1142         DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
1143         return -EIO;
1144     }
1145 
1146     blocks_num = sp_tx_get_edid_block(ctx);
1147     if (blocks_num < 0)
1148         return blocks_num;
1149 
1150     count = 0;
1151 
1152     do {
1153         switch (count) {
1154         case 0:
1155         case 1:
1156             for (i = 0; i < 8; i++) {
1157                 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
1158                 g_edid_break = edid_read(ctx, offset,
1159                              pblock_buf);
1160 
1161                 if (g_edid_break < 0)
1162                     break;
1163 
1164                 memcpy(&pedid_blocks_buf[offset],
1165                        pblock_buf,
1166                        MAX_DPCD_BUFFER_SIZE);
1167             }
1168 
1169             break;
1170         case 2:
1171             offset = 0x00;
1172 
1173             for (j = 0; j < 8; j++) {
1174                 edid_pos = (j + count * 8) *
1175                     MAX_DPCD_BUFFER_SIZE;
1176 
1177                 if (g_edid_break == 1)
1178                     break;
1179 
1180                 ret = segments_edid_read(ctx, count / 2,
1181                              pblock_buf, offset);
1182                 if (ret < 0)
1183                     return ret;
1184 
1185                 memcpy(&pedid_blocks_buf[edid_pos],
1186                        pblock_buf,
1187                        MAX_DPCD_BUFFER_SIZE);
1188                 offset = offset + 0x10;
1189             }
1190 
1191             break;
1192         case 3:
1193             offset = 0x80;
1194 
1195             for (j = 0; j < 8; j++) {
1196                 edid_pos = (j + count * 8) *
1197                     MAX_DPCD_BUFFER_SIZE;
1198                 if (g_edid_break == 1)
1199                     break;
1200 
1201                 ret = segments_edid_read(ctx, count / 2,
1202                              pblock_buf, offset);
1203                 if (ret < 0)
1204                     return ret;
1205 
1206                 memcpy(&pedid_blocks_buf[edid_pos],
1207                        pblock_buf,
1208                        MAX_DPCD_BUFFER_SIZE);
1209                 offset = offset + 0x10;
1210             }
1211 
1212             break;
1213         default:
1214             break;
1215         }
1216 
1217         count++;
1218 
1219     } while (blocks_num >= count);
1220 
1221     /* Check edid data */
1222     if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) {
1223         DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n");
1224         return -EINVAL;
1225     }
1226 
1227     /* Reset aux channel */
1228     ret = sp_tx_rst_aux(ctx);
1229     if (ret < 0) {
1230         DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n");
1231         return ret;
1232     }
1233 
1234     return (blocks_num + 1);
1235 }
1236 
1237 static void anx7625_power_on(struct anx7625_data *ctx)
1238 {
1239     struct device *dev = &ctx->client->dev;
1240     int ret, i;
1241 
1242     if (!ctx->pdata.low_power_mode) {
1243         DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1244         return;
1245     }
1246 
1247     for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1248         ret = regulator_enable(ctx->pdata.supplies[i].consumer);
1249         if (ret < 0) {
1250             DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n",
1251                          i, ret);
1252             goto reg_err;
1253         }
1254         usleep_range(2000, 2100);
1255     }
1256 
1257     usleep_range(11000, 12000);
1258 
1259     /* Power on pin enable */
1260     gpiod_set_value(ctx->pdata.gpio_p_on, 1);
1261     usleep_range(10000, 11000);
1262     /* Power reset pin enable */
1263     gpiod_set_value(ctx->pdata.gpio_reset, 1);
1264     usleep_range(10000, 11000);
1265 
1266     DRM_DEV_DEBUG_DRIVER(dev, "power on !\n");
1267     return;
1268 reg_err:
1269     for (--i; i >= 0; i--)
1270         regulator_disable(ctx->pdata.supplies[i].consumer);
1271 }
1272 
1273 static void anx7625_power_standby(struct anx7625_data *ctx)
1274 {
1275     struct device *dev = &ctx->client->dev;
1276     int ret;
1277 
1278     if (!ctx->pdata.low_power_mode) {
1279         DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1280         return;
1281     }
1282 
1283     gpiod_set_value(ctx->pdata.gpio_reset, 0);
1284     usleep_range(1000, 1100);
1285     gpiod_set_value(ctx->pdata.gpio_p_on, 0);
1286     usleep_range(1000, 1100);
1287 
1288     ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1289                      ctx->pdata.supplies);
1290     if (ret < 0)
1291         DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret);
1292 
1293     DRM_DEV_DEBUG_DRIVER(dev, "power down\n");
1294 }
1295 
1296 /* Basic configurations of ANX7625 */
1297 static void anx7625_config(struct anx7625_data *ctx)
1298 {
1299     anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1300               XTAL_FRQ_SEL, XTAL_FRQ_27M);
1301 }
1302 
1303 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
1304 {
1305     struct device *dev = &ctx->client->dev;
1306     int ret;
1307 
1308     /* Reset main ocm */
1309     ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
1310     /* Disable PD */
1311     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1312                  AP_AV_STATUS, AP_DISABLE_PD);
1313     /* Release main ocm */
1314     ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
1315 
1316     if (ret < 0)
1317         DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
1318     else
1319         DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
1320 }
1321 
1322 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
1323 {
1324     int ret;
1325     struct device *dev = &ctx->client->dev;
1326 
1327     /* Check interface workable */
1328     ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1329                    FLASH_LOAD_STA);
1330     if (ret < 0) {
1331         DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
1332         return ret;
1333     }
1334     if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK)
1335         return -ENODEV;
1336 
1337     anx7625_disable_pd_protocol(ctx);
1338 
1339     DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,",
1340                  anx7625_reg_read(ctx,
1341                           ctx->i2c.rx_p0_client,
1342                           OCM_FW_VERSION),
1343                  anx7625_reg_read(ctx,
1344                           ctx->i2c.rx_p0_client,
1345                           OCM_FW_REVERSION));
1346     DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n",
1347                  ANX7625_DRV_VERSION);
1348 
1349     return 0;
1350 }
1351 
1352 static void anx7625_power_on_init(struct anx7625_data *ctx)
1353 {
1354     int retry_count, i;
1355 
1356     for (retry_count = 0; retry_count < 3; retry_count++) {
1357         anx7625_power_on(ctx);
1358         anx7625_config(ctx);
1359 
1360         for (i = 0; i < OCM_LOADING_TIME; i++) {
1361             if (!anx7625_ocm_loading_check(ctx))
1362                 return;
1363             usleep_range(1000, 1100);
1364         }
1365         anx7625_power_standby(ctx);
1366     }
1367 }
1368 
1369 static void anx7625_init_gpio(struct anx7625_data *platform)
1370 {
1371     struct device *dev = &platform->client->dev;
1372 
1373     DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n");
1374 
1375     /* Gpio for chip power enable */
1376     platform->pdata.gpio_p_on =
1377         devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
1378     if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) {
1379         DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n");
1380         platform->pdata.gpio_p_on = NULL;
1381     }
1382 
1383     /* Gpio for chip reset */
1384     platform->pdata.gpio_reset =
1385         devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1386     if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) {
1387         DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n");
1388         platform->pdata.gpio_reset = NULL;
1389     }
1390 
1391     if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1392         platform->pdata.low_power_mode = 1;
1393         DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n",
1394                      desc_to_gpio(platform->pdata.gpio_p_on),
1395                      desc_to_gpio(platform->pdata.gpio_reset));
1396     } else {
1397         platform->pdata.low_power_mode = 0;
1398         DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n");
1399     }
1400 }
1401 
1402 static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1403 {
1404     ctx->hpd_status = 0;
1405     ctx->hpd_high_cnt = 0;
1406     ctx->display_timing_valid = 0;
1407 }
1408 
1409 static void anx7625_start_dp_work(struct anx7625_data *ctx)
1410 {
1411     int ret;
1412     struct device *dev = &ctx->client->dev;
1413 
1414     if (ctx->hpd_high_cnt >= 2) {
1415         DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n");
1416         return;
1417     }
1418 
1419     ctx->hpd_status = 1;
1420     ctx->hpd_high_cnt++;
1421 
1422     /* Not support HDCP */
1423     ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1424 
1425     /* Try auth flag */
1426     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1427     /* Interrupt for DRM */
1428     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1429     if (ret < 0) {
1430         DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n");
1431         return;
1432     }
1433 
1434     ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1435     if (ret < 0)
1436         return;
1437 
1438     DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
1439 }
1440 
1441 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1442 {
1443     return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1444 }
1445 
1446 static int _anx7625_hpd_polling(struct anx7625_data *ctx,
1447                 unsigned long wait_us)
1448 {
1449     int ret, val;
1450     struct device *dev = &ctx->client->dev;
1451 
1452     /* Interrupt mode, no need poll HPD status, just return */
1453     if (ctx->pdata.intp_irq)
1454         return 0;
1455 
1456     ret = readx_poll_timeout(anx7625_read_hpd_status_p0,
1457                  ctx, val,
1458                  ((val & HPD_STATUS) || (val < 0)),
1459                  wait_us / 100,
1460                  wait_us);
1461     if (ret) {
1462         DRM_DEV_ERROR(dev, "no hpd.\n");
1463         return ret;
1464     }
1465 
1466     DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val);
1467     anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1468               INTR_ALERT_1, 0xFF);
1469     anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1470               INTERFACE_CHANGE_INT, 0);
1471 
1472     anx7625_start_dp_work(ctx);
1473 
1474     if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1475         drm_helper_hpd_irq_event(ctx->bridge.dev);
1476 
1477     return 0;
1478 }
1479 
1480 static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux,
1481                      unsigned long wait_us)
1482 {
1483     struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1484     struct device *dev = &ctx->client->dev;
1485     int ret;
1486 
1487     pm_runtime_get_sync(dev);
1488     ret = _anx7625_hpd_polling(ctx, wait_us);
1489     pm_runtime_mark_last_busy(dev);
1490     pm_runtime_put_autosuspend(dev);
1491 
1492     return ret;
1493 }
1494 
1495 static void anx7625_remove_edid(struct anx7625_data *ctx)
1496 {
1497     ctx->slimport_edid_p.edid_block_num = -1;
1498 }
1499 
1500 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
1501 {
1502     int i;
1503 
1504     for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1505         anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1506                   DP_TX_LANE0_SWING_REG0 + i,
1507                   ctx->pdata.lane0_reg_data[i]);
1508 
1509     for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1510         anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1511                   DP_TX_LANE1_SWING_REG0 + i,
1512                   ctx->pdata.lane1_reg_data[i]);
1513 }
1514 
1515 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1516 {
1517     struct device *dev = &ctx->client->dev;
1518 
1519     /* HPD changed */
1520     DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n",
1521                  (u32)on);
1522 
1523     if (on == 0) {
1524         DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n");
1525         anx7625_remove_edid(ctx);
1526         anx7625_stop_dp_work(ctx);
1527     } else {
1528         DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
1529         anx7625_start_dp_work(ctx);
1530         anx7625_dp_adjust_swing(ctx);
1531     }
1532 }
1533 
1534 static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1535 {
1536     int intr_vector, status;
1537     struct device *dev = &ctx->client->dev;
1538 
1539     status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1540                    INTR_ALERT_1, 0xFF);
1541     if (status < 0) {
1542         DRM_DEV_ERROR(dev, "cannot clear alert reg.\n");
1543         return status;
1544     }
1545 
1546     intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1547                        INTERFACE_CHANGE_INT);
1548     if (intr_vector < 0) {
1549         DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n");
1550         return intr_vector;
1551     }
1552     DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
1553     status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1554                    INTERFACE_CHANGE_INT,
1555                    intr_vector & (~intr_vector));
1556     if (status < 0) {
1557         DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
1558         return status;
1559     }
1560 
1561     if (!(intr_vector & HPD_STATUS_CHANGE))
1562         return -ENOENT;
1563 
1564     status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1565                   SYSTEM_STSTUS);
1566     if (status < 0) {
1567         DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n");
1568         return status;
1569     }
1570 
1571     DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status);
1572     dp_hpd_change_handler(ctx, status & HPD_STATUS);
1573 
1574     return 0;
1575 }
1576 
1577 static void anx7625_work_func(struct work_struct *work)
1578 {
1579     int event;
1580     struct anx7625_data *ctx = container_of(work,
1581                         struct anx7625_data, work);
1582 
1583     mutex_lock(&ctx->lock);
1584 
1585     if (pm_runtime_suspended(&ctx->client->dev))
1586         goto unlock;
1587 
1588     event = anx7625_hpd_change_detect(ctx);
1589     if (event < 0)
1590         goto unlock;
1591 
1592     if (ctx->bridge_attached)
1593         drm_helper_hpd_irq_event(ctx->bridge.dev);
1594 
1595 unlock:
1596     mutex_unlock(&ctx->lock);
1597 }
1598 
1599 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
1600 {
1601     struct anx7625_data *ctx = (struct anx7625_data *)data;
1602 
1603     queue_work(ctx->workqueue, &ctx->work);
1604 
1605     return IRQ_HANDLED;
1606 }
1607 
1608 static int anx7625_get_swing_setting(struct device *dev,
1609                      struct anx7625_platform_data *pdata)
1610 {
1611     int num_regs;
1612 
1613     if (of_get_property(dev->of_node,
1614                 "analogix,lane0-swing", &num_regs)) {
1615         if (num_regs > DP_TX_SWING_REG_CNT)
1616             num_regs = DP_TX_SWING_REG_CNT;
1617 
1618         pdata->dp_lane0_swing_reg_cnt = num_regs;
1619         of_property_read_u8_array(dev->of_node, "analogix,lane0-swing",
1620                       pdata->lane0_reg_data, num_regs);
1621     }
1622 
1623     if (of_get_property(dev->of_node,
1624                 "analogix,lane1-swing", &num_regs)) {
1625         if (num_regs > DP_TX_SWING_REG_CNT)
1626             num_regs = DP_TX_SWING_REG_CNT;
1627 
1628         pdata->dp_lane1_swing_reg_cnt = num_regs;
1629         of_property_read_u8_array(dev->of_node, "analogix,lane1-swing",
1630                       pdata->lane1_reg_data, num_regs);
1631     }
1632 
1633     return 0;
1634 }
1635 
1636 static int anx7625_parse_dt(struct device *dev,
1637                 struct anx7625_platform_data *pdata)
1638 {
1639     struct device_node *np = dev->of_node, *ep0;
1640     int bus_type, mipi_lanes;
1641 
1642     anx7625_get_swing_setting(dev, pdata);
1643 
1644     pdata->is_dpi = 0; /* default dsi mode */
1645     pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
1646     if (!pdata->mipi_host_node) {
1647         DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
1648         return -ENODEV;
1649     }
1650 
1651     bus_type = 0;
1652     mipi_lanes = MAX_LANES_SUPPORT;
1653     ep0 = of_graph_get_endpoint_by_regs(np, 0, 0);
1654     if (ep0) {
1655         if (of_property_read_u32(ep0, "bus-type", &bus_type))
1656             bus_type = 0;
1657 
1658         mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT);
1659         of_node_put(ep0);
1660     }
1661 
1662     if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */
1663         pdata->is_dpi = 1;
1664 
1665     pdata->mipi_lanes = MAX_LANES_SUPPORT;
1666     if (mipi_lanes > 0)
1667         pdata->mipi_lanes = mipi_lanes;
1668 
1669     if (pdata->is_dpi)
1670         DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n");
1671     else
1672         DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n");
1673 
1674     if (of_property_read_bool(np, "analogix,audio-enable"))
1675         pdata->audio_en = 1;
1676 
1677     pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
1678     if (IS_ERR(pdata->panel_bridge)) {
1679         if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {
1680             pdata->panel_bridge = NULL;
1681             return 0;
1682         }
1683 
1684         return PTR_ERR(pdata->panel_bridge);
1685     }
1686 
1687     DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n");
1688 
1689     return 0;
1690 }
1691 
1692 static bool anx7625_of_panel_on_aux_bus(struct device *dev)
1693 {
1694     struct device_node *bus, *panel;
1695 
1696     bus = of_get_child_by_name(dev->of_node, "aux-bus");
1697     if (!bus)
1698         return false;
1699 
1700     panel = of_get_child_by_name(bus, "panel");
1701     of_node_put(bus);
1702     if (!panel)
1703         return false;
1704     of_node_put(panel);
1705 
1706     return true;
1707 }
1708 
1709 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge)
1710 {
1711     return container_of(bridge, struct anx7625_data, bridge);
1712 }
1713 
1714 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux,
1715                     struct drm_dp_aux_msg *msg)
1716 {
1717     struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1718     struct device *dev = &ctx->client->dev;
1719     u8 request = msg->request & ~DP_AUX_I2C_MOT;
1720     int ret = 0;
1721 
1722     pm_runtime_get_sync(dev);
1723     msg->reply = 0;
1724     switch (request) {
1725     case DP_AUX_NATIVE_WRITE:
1726     case DP_AUX_I2C_WRITE:
1727     case DP_AUX_NATIVE_READ:
1728     case DP_AUX_I2C_READ:
1729         break;
1730     default:
1731         ret = -EINVAL;
1732     }
1733     if (!ret)
1734         ret = anx7625_aux_trans(ctx, msg->request, msg->address,
1735                     msg->size, msg->buffer);
1736     pm_runtime_mark_last_busy(dev);
1737     pm_runtime_put_autosuspend(dev);
1738 
1739     return ret;
1740 }
1741 
1742 static struct edid *anx7625_get_edid(struct anx7625_data *ctx)
1743 {
1744     struct device *dev = &ctx->client->dev;
1745     struct s_edid_data *p_edid = &ctx->slimport_edid_p;
1746     int edid_num;
1747     u8 *edid;
1748 
1749     edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL);
1750     if (!edid) {
1751         DRM_DEV_ERROR(dev, "Fail to allocate buffer\n");
1752         return NULL;
1753     }
1754 
1755     if (ctx->slimport_edid_p.edid_block_num > 0) {
1756         memcpy(edid, ctx->slimport_edid_p.edid_raw_data,
1757                FOUR_BLOCK_SIZE);
1758         return (struct edid *)edid;
1759     }
1760 
1761     pm_runtime_get_sync(dev);
1762     _anx7625_hpd_polling(ctx, 5000 * 100);
1763     edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data);
1764     pm_runtime_put_sync(dev);
1765 
1766     if (edid_num < 1) {
1767         DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1768         kfree(edid);
1769         return NULL;
1770     }
1771 
1772     p_edid->edid_block_num = edid_num;
1773 
1774     memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE);
1775     return (struct edid *)edid;
1776 }
1777 
1778 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1779 {
1780     struct device *dev = &ctx->client->dev;
1781 
1782     DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n");
1783 
1784     if (ctx->pdata.panel_bridge)
1785         return connector_status_connected;
1786 
1787     return ctx->hpd_status ? connector_status_connected :
1788                      connector_status_disconnected;
1789 }
1790 
1791 static int anx7625_audio_hw_params(struct device *dev, void *data,
1792                    struct hdmi_codec_daifmt *fmt,
1793                    struct hdmi_codec_params *params)
1794 {
1795     struct anx7625_data *ctx = dev_get_drvdata(dev);
1796     int wl, ch, rate;
1797     int ret = 0;
1798 
1799     if (fmt->fmt != HDMI_DSP_A) {
1800         DRM_DEV_ERROR(dev, "only supports DSP_A\n");
1801         return -EINVAL;
1802     }
1803 
1804     DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n",
1805                  params->sample_rate, params->sample_width,
1806                  params->cea.channels);
1807 
1808     ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1809                     AUDIO_CHANNEL_STATUS_6,
1810                     ~I2S_SLAVE_MODE,
1811                     TDM_SLAVE_MODE);
1812 
1813     /* Word length */
1814     switch (params->sample_width) {
1815     case 16:
1816         wl = AUDIO_W_LEN_16_20MAX;
1817         break;
1818     case 18:
1819         wl = AUDIO_W_LEN_18_20MAX;
1820         break;
1821     case 20:
1822         wl = AUDIO_W_LEN_20_20MAX;
1823         break;
1824     case 24:
1825         wl = AUDIO_W_LEN_24_24MAX;
1826         break;
1827     default:
1828         DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
1829                      params->sample_width);
1830         return -EINVAL;
1831     }
1832     ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1833                     AUDIO_CHANNEL_STATUS_5,
1834                     0xf0, wl);
1835 
1836     /* Channel num */
1837     switch (params->cea.channels) {
1838     case 2:
1839         ch = I2S_CH_2;
1840         break;
1841     case 4:
1842         ch = TDM_CH_4;
1843         break;
1844     case 6:
1845         ch = TDM_CH_6;
1846         break;
1847     case 8:
1848         ch = TDM_CH_8;
1849         break;
1850     default:
1851         DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
1852                      params->cea.channels);
1853         return -EINVAL;
1854     }
1855     ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1856                    AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5);
1857     if (ch > I2S_CH_2)
1858         ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
1859                 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT);
1860     else
1861         ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
1862                 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT);
1863 
1864     /* FS */
1865     switch (params->sample_rate) {
1866     case 32000:
1867         rate = AUDIO_FS_32K;
1868         break;
1869     case 44100:
1870         rate = AUDIO_FS_441K;
1871         break;
1872     case 48000:
1873         rate = AUDIO_FS_48K;
1874         break;
1875     case 88200:
1876         rate = AUDIO_FS_882K;
1877         break;
1878     case 96000:
1879         rate = AUDIO_FS_96K;
1880         break;
1881     case 176400:
1882         rate = AUDIO_FS_1764K;
1883         break;
1884     case 192000:
1885         rate = AUDIO_FS_192K;
1886         break;
1887     default:
1888         DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support",
1889                      params->sample_rate);
1890         return -EINVAL;
1891     }
1892     ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1893                     AUDIO_CHANNEL_STATUS_4,
1894                     0xf0, rate);
1895     ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1896                 AP_AV_STATUS, AP_AUDIO_CHG);
1897     if (ret < 0) {
1898         DRM_DEV_ERROR(dev, "IO error : config audio.\n");
1899         return -EIO;
1900     }
1901 
1902     return 0;
1903 }
1904 
1905 static void anx7625_audio_shutdown(struct device *dev, void *data)
1906 {
1907     DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n");
1908 }
1909 
1910 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
1911                        struct device_node *endpoint)
1912 {
1913     struct of_endpoint of_ep;
1914     int ret;
1915 
1916     ret = of_graph_parse_endpoint(endpoint, &of_ep);
1917     if (ret < 0)
1918         return ret;
1919 
1920     /*
1921      * HDMI sound should be located at external DPI port
1922      * Didn't have good way to check where is internal(DSI)
1923      * or external(DPI) bridge
1924      */
1925     return 0;
1926 }
1927 
1928 static void
1929 anx7625_audio_update_connector_status(struct anx7625_data *ctx,
1930                       enum drm_connector_status status)
1931 {
1932     if (ctx->plugged_cb && ctx->codec_dev) {
1933         ctx->plugged_cb(ctx->codec_dev,
1934                 status == connector_status_connected);
1935     }
1936 }
1937 
1938 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data,
1939                      hdmi_codec_plugged_cb fn,
1940                      struct device *codec_dev)
1941 {
1942     struct anx7625_data *ctx = data;
1943 
1944     ctx->plugged_cb = fn;
1945     ctx->codec_dev = codec_dev;
1946     anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx));
1947 
1948     return 0;
1949 }
1950 
1951 static int anx7625_audio_get_eld(struct device *dev, void *data,
1952                  u8 *buf, size_t len)
1953 {
1954     struct anx7625_data *ctx = dev_get_drvdata(dev);
1955 
1956     if (!ctx->connector) {
1957         /* Pass en empty ELD if connector not available */
1958         memset(buf, 0, len);
1959     } else {
1960         dev_dbg(dev, "audio copy eld\n");
1961         memcpy(buf, ctx->connector->eld,
1962                min(sizeof(ctx->connector->eld), len));
1963     }
1964 
1965     return 0;
1966 }
1967 
1968 static const struct hdmi_codec_ops anx7625_codec_ops = {
1969     .hw_params  = anx7625_audio_hw_params,
1970     .audio_shutdown = anx7625_audio_shutdown,
1971     .get_eld    = anx7625_audio_get_eld,
1972     .get_dai_id = anx7625_hdmi_i2s_get_dai_id,
1973     .hook_plugged_cb = anx7625_audio_hook_plugged_cb,
1974 };
1975 
1976 static void anx7625_unregister_audio(struct anx7625_data *ctx)
1977 {
1978     struct device *dev = &ctx->client->dev;
1979 
1980     if (ctx->audio_pdev) {
1981         platform_device_unregister(ctx->audio_pdev);
1982         ctx->audio_pdev = NULL;
1983     }
1984 
1985     DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME);
1986 }
1987 
1988 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx)
1989 {
1990     struct hdmi_codec_pdata codec_data = {
1991         .ops = &anx7625_codec_ops,
1992         .max_i2s_channels = 8,
1993         .i2s = 1,
1994         .data = ctx,
1995     };
1996 
1997     ctx->audio_pdev = platform_device_register_data(dev,
1998                             HDMI_CODEC_DRV_NAME,
1999                             PLATFORM_DEVID_AUTO,
2000                             &codec_data,
2001                             sizeof(codec_data));
2002 
2003     if (IS_ERR(ctx->audio_pdev))
2004         return PTR_ERR(ctx->audio_pdev);
2005 
2006     DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME);
2007 
2008     return 0;
2009 }
2010 
2011 static int anx7625_attach_dsi(struct anx7625_data *ctx)
2012 {
2013     struct mipi_dsi_device *dsi;
2014     struct device *dev = &ctx->client->dev;
2015     struct mipi_dsi_host *host;
2016     const struct mipi_dsi_device_info info = {
2017         .type = "anx7625",
2018         .channel = 0,
2019         .node = NULL,
2020     };
2021     int ret;
2022 
2023     DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2024 
2025     host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2026     if (!host) {
2027         DRM_DEV_ERROR(dev, "fail to find dsi host.\n");
2028         return -EPROBE_DEFER;
2029     }
2030 
2031     dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2032     if (IS_ERR(dsi)) {
2033         DRM_DEV_ERROR(dev, "fail to create dsi device.\n");
2034         return -EINVAL;
2035     }
2036 
2037     dsi->lanes = ctx->pdata.mipi_lanes;
2038     dsi->format = MIPI_DSI_FMT_RGB888;
2039     dsi->mode_flags = MIPI_DSI_MODE_VIDEO   |
2040         MIPI_DSI_MODE_VIDEO_SYNC_PULSE  |
2041         MIPI_DSI_MODE_VIDEO_HSE |
2042         MIPI_DSI_HS_PKT_END_ALIGNED;
2043 
2044     ret = devm_mipi_dsi_attach(dev, dsi);
2045     if (ret) {
2046         DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
2047         return ret;
2048     }
2049 
2050     ctx->dsi = dsi;
2051 
2052     DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
2053 
2054     return 0;
2055 }
2056 
2057 static void hdcp_check_work_func(struct work_struct *work)
2058 {
2059     u8 status;
2060     struct delayed_work *dwork;
2061     struct anx7625_data *ctx;
2062     struct device *dev;
2063     struct drm_device *drm_dev;
2064 
2065     dwork = to_delayed_work(work);
2066     ctx = container_of(dwork, struct anx7625_data, hdcp_work);
2067     dev = &ctx->client->dev;
2068 
2069     if (!ctx->connector) {
2070         dev_err(dev, "HDCP connector is null!");
2071         return;
2072     }
2073 
2074     drm_dev = ctx->connector->dev;
2075     drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2076     mutex_lock(&ctx->hdcp_wq_lock);
2077 
2078     status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
2079     dev_dbg(dev, "sink HDCP status check: %.02x\n", status);
2080     if (status & BIT(1)) {
2081         ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2082         drm_hdcp_update_content_protection(ctx->connector,
2083                            ctx->hdcp_cp);
2084         dev_dbg(dev, "update CP to ENABLE\n");
2085     }
2086 
2087     mutex_unlock(&ctx->hdcp_wq_lock);
2088     drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2089 }
2090 
2091 static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
2092                       struct drm_connector_state *state)
2093 {
2094     struct device *dev = &ctx->client->dev;
2095     int cp;
2096 
2097     dev_dbg(dev, "hdcp state check\n");
2098     cp = state->content_protection;
2099 
2100     if (cp == ctx->hdcp_cp)
2101         return 0;
2102 
2103     if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
2104         if (ctx->dp_en) {
2105             dev_dbg(dev, "enable HDCP\n");
2106             anx7625_hdcp_enable(ctx);
2107 
2108             queue_delayed_work(ctx->hdcp_workqueue,
2109                        &ctx->hdcp_work,
2110                        msecs_to_jiffies(2000));
2111         }
2112     }
2113 
2114     if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
2115         if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2116             dev_err(dev, "current CP is not ENABLED\n");
2117             return -EINVAL;
2118         }
2119         anx7625_hdcp_disable(ctx);
2120         ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2121         drm_hdcp_update_content_protection(ctx->connector,
2122                            ctx->hdcp_cp);
2123         dev_dbg(dev, "update CP to UNDESIRE\n");
2124     }
2125 
2126     if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2127         dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n");
2128         return -EINVAL;
2129     }
2130 
2131     return 0;
2132 }
2133 
2134 static int anx7625_bridge_attach(struct drm_bridge *bridge,
2135                  enum drm_bridge_attach_flags flags)
2136 {
2137     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2138     int err;
2139     struct device *dev = &ctx->client->dev;
2140 
2141     DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n");
2142     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
2143         return -EINVAL;
2144 
2145     if (!bridge->encoder) {
2146         DRM_DEV_ERROR(dev, "Parent encoder object not found");
2147         return -ENODEV;
2148     }
2149 
2150     ctx->aux.drm_dev = bridge->dev;
2151     err = drm_dp_aux_register(&ctx->aux);
2152     if (err) {
2153         dev_err(dev, "failed to register aux channel: %d\n", err);
2154         return err;
2155     }
2156 
2157     if (ctx->pdata.panel_bridge) {
2158         err = drm_bridge_attach(bridge->encoder,
2159                     ctx->pdata.panel_bridge,
2160                     &ctx->bridge, flags);
2161         if (err)
2162             return err;
2163     }
2164 
2165     ctx->bridge_attached = 1;
2166 
2167     return 0;
2168 }
2169 
2170 static void anx7625_bridge_detach(struct drm_bridge *bridge)
2171 {
2172     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2173 
2174     drm_dp_aux_unregister(&ctx->aux);
2175 }
2176 
2177 static enum drm_mode_status
2178 anx7625_bridge_mode_valid(struct drm_bridge *bridge,
2179               const struct drm_display_info *info,
2180               const struct drm_display_mode *mode)
2181 {
2182     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2183     struct device *dev = &ctx->client->dev;
2184 
2185     DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
2186 
2187     /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
2188     if (mode->clock > SUPPORT_PIXEL_CLOCK) {
2189         DRM_DEV_DEBUG_DRIVER(dev,
2190                      "drm mode invalid, pixelclock too high.\n");
2191         return MODE_CLOCK_HIGH;
2192     }
2193 
2194     DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
2195 
2196     return MODE_OK;
2197 }
2198 
2199 static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
2200                     const struct drm_display_mode *old_mode,
2201                     const struct drm_display_mode *mode)
2202 {
2203     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2204     struct device *dev = &ctx->client->dev;
2205 
2206     DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n");
2207 
2208     ctx->dt.pixelclock.min = mode->clock;
2209     ctx->dt.hactive.min = mode->hdisplay;
2210     ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2211     ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2212     ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2213     ctx->dt.vactive.min = mode->vdisplay;
2214     ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2215     ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2216     ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2217 
2218     ctx->display_timing_valid = 1;
2219 
2220     DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2221     DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n",
2222                  ctx->dt.hactive.min,
2223                  ctx->dt.hsync_len.min,
2224                  ctx->dt.hfront_porch.min,
2225                  ctx->dt.hback_porch.min);
2226     DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
2227                  ctx->dt.vactive.min,
2228                  ctx->dt.vsync_len.min,
2229                  ctx->dt.vfront_porch.min,
2230                  ctx->dt.vback_porch.min);
2231     DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n",
2232                  mode->hdisplay,
2233                  mode->hsync_start);
2234     DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n",
2235                  mode->hsync_end,
2236                  mode->htotal);
2237     DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n",
2238                  mode->vdisplay,
2239                  mode->vsync_start);
2240     DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
2241                  mode->vsync_end,
2242                  mode->vtotal);
2243 }
2244 
2245 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
2246                       const struct drm_display_mode *mode,
2247                       struct drm_display_mode *adj)
2248 {
2249     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2250     struct device *dev = &ctx->client->dev;
2251     u32 hsync, hfp, hbp, hblanking;
2252     u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj;
2253     u32 vref, adj_clock;
2254 
2255     DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
2256 
2257     /* No need fixup for external monitor */
2258     if (!ctx->pdata.panel_bridge)
2259         return true;
2260 
2261     hsync = mode->hsync_end - mode->hsync_start;
2262     hfp = mode->hsync_start - mode->hdisplay;
2263     hbp = mode->htotal - mode->hsync_end;
2264     hblanking = mode->htotal - mode->hdisplay;
2265 
2266     DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n");
2267     DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2268                  hsync, hfp, hbp, adj->clock);
2269     DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2270                  adj->hsync_start, adj->hsync_end, adj->htotal);
2271 
2272     adj_hfp = hfp;
2273     adj_hsync = hsync;
2274     adj_hbp = hbp;
2275     adj_hblanking = hblanking;
2276 
2277     /* HFP needs to be even */
2278     if (hfp & 0x1) {
2279         adj_hfp += 1;
2280         adj_hblanking += 1;
2281     }
2282 
2283     /* HBP needs to be even */
2284     if (hbp & 0x1) {
2285         adj_hbp -= 1;
2286         adj_hblanking -= 1;
2287     }
2288 
2289     /* HSYNC needs to be even */
2290     if (hsync & 0x1) {
2291         if (adj_hblanking < hblanking)
2292             adj_hsync += 1;
2293         else
2294             adj_hsync -= 1;
2295     }
2296 
2297     /*
2298      * Once illegal timing detected, use default HFP, HSYNC, HBP
2299      * This adjusting made for built-in eDP panel, for the externel
2300      * DP monitor, may need return false.
2301      */
2302     if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) {
2303         adj_hsync = SYNC_LEN_DEF;
2304         adj_hfp = HFP_HBP_DEF;
2305         adj_hbp = HFP_HBP_DEF;
2306         vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
2307         if (hblanking < HBLANKING_MIN) {
2308             delta_adj = HBLANKING_MIN - hblanking;
2309             adj_clock = vref * delta_adj * adj->vtotal;
2310             adj->clock += DIV_ROUND_UP(adj_clock, 1000);
2311         } else {
2312             delta_adj = hblanking - HBLANKING_MIN;
2313             adj_clock = vref * delta_adj * adj->vtotal;
2314             adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
2315         }
2316 
2317         DRM_WARN("illegal hblanking timing, use default.\n");
2318         DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync);
2319     } else if (adj_hfp < HP_MIN) {
2320         /* Adjust hfp if hfp less than HP_MIN */
2321         delta_adj = HP_MIN - adj_hfp;
2322         adj_hfp = HP_MIN;
2323 
2324         /*
2325          * Balance total HBlanking pixel, if HBP does not have enough
2326          * space, adjust HSYNC length, otherwise adjust HBP
2327          */
2328         if ((adj_hbp - delta_adj) < HP_MIN)
2329             /* HBP not enough space */
2330             adj_hsync -= delta_adj;
2331         else
2332             adj_hbp -= delta_adj;
2333     } else if (adj_hbp < HP_MIN) {
2334         delta_adj = HP_MIN - adj_hbp;
2335         adj_hbp = HP_MIN;
2336 
2337         /*
2338          * Balance total HBlanking pixel, if HBP hasn't enough space,
2339          * adjust HSYNC length, otherwize adjust HBP
2340          */
2341         if ((adj_hfp - delta_adj) < HP_MIN)
2342             /* HFP not enough space */
2343             adj_hsync -= delta_adj;
2344         else
2345             adj_hfp -= delta_adj;
2346     }
2347 
2348     DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
2349     DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2350                  adj_hsync, adj_hfp, adj_hbp, adj->clock);
2351 
2352     /* Reconstruct timing */
2353     adj->hsync_start = adj->hdisplay + adj_hfp;
2354     adj->hsync_end = adj->hsync_start + adj_hsync;
2355     adj->htotal = adj->hsync_end + adj_hbp;
2356     DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2357                  adj->hsync_start, adj->hsync_end, adj->htotal);
2358 
2359     return true;
2360 }
2361 
2362 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
2363                        struct drm_bridge_state *bridge_state,
2364                        struct drm_crtc_state *crtc_state,
2365                        struct drm_connector_state *conn_state)
2366 {
2367     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2368     struct device *dev = &ctx->client->dev;
2369 
2370     dev_dbg(dev, "drm bridge atomic check\n");
2371 
2372     anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
2373                   &crtc_state->adjusted_mode);
2374 
2375     return anx7625_connector_atomic_check(ctx, conn_state);
2376 }
2377 
2378 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
2379                      struct drm_bridge_state *state)
2380 {
2381     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2382     struct device *dev = &ctx->client->dev;
2383     struct drm_connector *connector;
2384 
2385     dev_dbg(dev, "drm atomic enable\n");
2386 
2387     if (!bridge->encoder) {
2388         dev_err(dev, "Parent encoder object not found");
2389         return;
2390     }
2391 
2392     connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
2393                                  bridge->encoder);
2394     if (!connector)
2395         return;
2396 
2397     ctx->connector = connector;
2398 
2399     pm_runtime_get_sync(dev);
2400     _anx7625_hpd_polling(ctx, 5000 * 100);
2401 
2402     anx7625_dp_start(ctx);
2403 }
2404 
2405 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
2406                       struct drm_bridge_state *old)
2407 {
2408     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2409     struct device *dev = &ctx->client->dev;
2410 
2411     dev_dbg(dev, "drm atomic disable\n");
2412 
2413     ctx->connector = NULL;
2414     anx7625_dp_stop(ctx);
2415 
2416     pm_runtime_put_sync(dev);
2417 }
2418 
2419 static enum drm_connector_status
2420 anx7625_bridge_detect(struct drm_bridge *bridge)
2421 {
2422     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2423     struct device *dev = &ctx->client->dev;
2424 
2425     DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n");
2426 
2427     return anx7625_sink_detect(ctx);
2428 }
2429 
2430 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge,
2431                         struct drm_connector *connector)
2432 {
2433     struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2434     struct device *dev = &ctx->client->dev;
2435 
2436     DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n");
2437 
2438     return anx7625_get_edid(ctx);
2439 }
2440 
2441 static const struct drm_bridge_funcs anx7625_bridge_funcs = {
2442     .attach = anx7625_bridge_attach,
2443     .detach = anx7625_bridge_detach,
2444     .mode_valid = anx7625_bridge_mode_valid,
2445     .mode_set = anx7625_bridge_mode_set,
2446     .atomic_check = anx7625_bridge_atomic_check,
2447     .atomic_enable = anx7625_bridge_atomic_enable,
2448     .atomic_disable = anx7625_bridge_atomic_disable,
2449     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2450     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2451     .atomic_reset = drm_atomic_helper_bridge_reset,
2452     .detect = anx7625_bridge_detect,
2453     .get_edid = anx7625_bridge_get_edid,
2454 };
2455 
2456 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
2457                           struct i2c_client *client)
2458 {
2459     struct device *dev = &ctx->client->dev;
2460 
2461     ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2462                               TX_P0_ADDR >> 1);
2463     if (IS_ERR(ctx->i2c.tx_p0_client))
2464         return PTR_ERR(ctx->i2c.tx_p0_client);
2465 
2466     ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2467                               TX_P1_ADDR >> 1);
2468     if (IS_ERR(ctx->i2c.tx_p1_client))
2469         return PTR_ERR(ctx->i2c.tx_p1_client);
2470 
2471     ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2472                               TX_P2_ADDR >> 1);
2473     if (IS_ERR(ctx->i2c.tx_p2_client))
2474         return PTR_ERR(ctx->i2c.tx_p2_client);
2475 
2476     ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2477                               RX_P0_ADDR >> 1);
2478     if (IS_ERR(ctx->i2c.rx_p0_client))
2479         return PTR_ERR(ctx->i2c.rx_p0_client);
2480 
2481     ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2482                               RX_P1_ADDR >> 1);
2483     if (IS_ERR(ctx->i2c.rx_p1_client))
2484         return PTR_ERR(ctx->i2c.rx_p1_client);
2485 
2486     ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2487                               RX_P2_ADDR >> 1);
2488     if (IS_ERR(ctx->i2c.rx_p2_client))
2489         return PTR_ERR(ctx->i2c.rx_p2_client);
2490 
2491     ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter,
2492                              TCPC_INTERFACE_ADDR >> 1);
2493     if (IS_ERR(ctx->i2c.tcpc_client))
2494         return PTR_ERR(ctx->i2c.tcpc_client);
2495 
2496     return 0;
2497 }
2498 
2499 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev)
2500 {
2501     struct anx7625_data *ctx = dev_get_drvdata(dev);
2502 
2503     mutex_lock(&ctx->lock);
2504 
2505     anx7625_stop_dp_work(ctx);
2506     anx7625_power_standby(ctx);
2507 
2508     mutex_unlock(&ctx->lock);
2509 
2510     return 0;
2511 }
2512 
2513 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
2514 {
2515     struct anx7625_data *ctx = dev_get_drvdata(dev);
2516 
2517     mutex_lock(&ctx->lock);
2518 
2519     anx7625_power_on_init(ctx);
2520 
2521     mutex_unlock(&ctx->lock);
2522 
2523     return 0;
2524 }
2525 
2526 static const struct dev_pm_ops anx7625_pm_ops = {
2527     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2528                 pm_runtime_force_resume)
2529     SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
2530                anx7625_runtime_pm_resume, NULL)
2531 };
2532 
2533 static void anx7625_runtime_disable(void *data)
2534 {
2535     pm_runtime_dont_use_autosuspend(data);
2536     pm_runtime_disable(data);
2537 }
2538 
2539 static int anx7625_i2c_probe(struct i2c_client *client,
2540                  const struct i2c_device_id *id)
2541 {
2542     struct anx7625_data *platform;
2543     struct anx7625_platform_data *pdata;
2544     int ret = 0;
2545     struct device *dev = &client->dev;
2546 
2547     if (!i2c_check_functionality(client->adapter,
2548                      I2C_FUNC_SMBUS_I2C_BLOCK)) {
2549         DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n");
2550         return -ENODEV;
2551     }
2552 
2553     platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL);
2554     if (!platform) {
2555         DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
2556         return -ENOMEM;
2557     }
2558 
2559     pdata = &platform->pdata;
2560 
2561     platform->client = client;
2562     i2c_set_clientdata(client, platform);
2563 
2564     pdata->supplies[0].supply = "vdd10";
2565     pdata->supplies[1].supply = "vdd18";
2566     pdata->supplies[2].supply = "vdd33";
2567     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
2568                       pdata->supplies);
2569     if (ret) {
2570         DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret);
2571         return ret;
2572     }
2573     anx7625_init_gpio(platform);
2574 
2575     mutex_init(&platform->lock);
2576     mutex_init(&platform->hdcp_wq_lock);
2577 
2578     INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
2579     platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
2580     if (!platform->hdcp_workqueue) {
2581         dev_err(dev, "fail to create work queue\n");
2582         ret = -ENOMEM;
2583         return ret;
2584     }
2585 
2586     platform->pdata.intp_irq = client->irq;
2587     if (platform->pdata.intp_irq) {
2588         INIT_WORK(&platform->work, anx7625_work_func);
2589         platform->workqueue = alloc_workqueue("anx7625_work",
2590                               WQ_FREEZABLE | WQ_MEM_RECLAIM, 1);
2591         if (!platform->workqueue) {
2592             DRM_DEV_ERROR(dev, "fail to create work queue\n");
2593             ret = -ENOMEM;
2594             goto free_hdcp_wq;
2595         }
2596 
2597         ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
2598                         NULL, anx7625_intr_hpd_isr,
2599                         IRQF_TRIGGER_FALLING |
2600                         IRQF_ONESHOT,
2601                         "anx7625-intp", platform);
2602         if (ret) {
2603             DRM_DEV_ERROR(dev, "fail to request irq\n");
2604             goto free_wq;
2605         }
2606     }
2607 
2608     platform->aux.name = "anx7625-aux";
2609     platform->aux.dev = dev;
2610     platform->aux.transfer = anx7625_aux_transfer;
2611     platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
2612     drm_dp_aux_init(&platform->aux);
2613 
2614     if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
2615         ret = -ENOMEM;
2616         DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
2617         goto free_wq;
2618     }
2619 
2620     pm_runtime_enable(dev);
2621     pm_runtime_set_autosuspend_delay(dev, 1000);
2622     pm_runtime_use_autosuspend(dev);
2623     pm_suspend_ignore_children(dev, true);
2624     ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev);
2625     if (ret)
2626         goto free_wq;
2627 
2628     devm_of_dp_aux_populate_ep_devices(&platform->aux);
2629 
2630     ret = anx7625_parse_dt(dev, pdata);
2631     if (ret) {
2632         if (ret != -EPROBE_DEFER)
2633             DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2634         goto free_wq;
2635     }
2636 
2637     if (!platform->pdata.low_power_mode) {
2638         anx7625_disable_pd_protocol(platform);
2639         pm_runtime_get_sync(dev);
2640         _anx7625_hpd_polling(platform, 5000 * 100);
2641     }
2642 
2643     /* Add work function */
2644     if (platform->pdata.intp_irq)
2645         queue_work(platform->workqueue, &platform->work);
2646 
2647     platform->bridge.funcs = &anx7625_bridge_funcs;
2648     platform->bridge.of_node = client->dev.of_node;
2649     if (!anx7625_of_panel_on_aux_bus(&client->dev))
2650         platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2651     if (!platform->pdata.panel_bridge)
2652         platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2653                     DRM_BRIDGE_OP_DETECT;
2654     platform->bridge.type = platform->pdata.panel_bridge ?
2655                     DRM_MODE_CONNECTOR_eDP :
2656                     DRM_MODE_CONNECTOR_DisplayPort;
2657 
2658     drm_bridge_add(&platform->bridge);
2659 
2660     if (!platform->pdata.is_dpi) {
2661         ret = anx7625_attach_dsi(platform);
2662         if (ret) {
2663             DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret);
2664             goto unregister_bridge;
2665         }
2666     }
2667 
2668     if (platform->pdata.audio_en)
2669         anx7625_register_audio(dev, platform);
2670 
2671     DRM_DEV_DEBUG_DRIVER(dev, "probe done\n");
2672 
2673     return 0;
2674 
2675 unregister_bridge:
2676     drm_bridge_remove(&platform->bridge);
2677 
2678     if (!platform->pdata.low_power_mode)
2679         pm_runtime_put_sync_suspend(&client->dev);
2680 
2681 free_wq:
2682     if (platform->workqueue)
2683         destroy_workqueue(platform->workqueue);
2684 
2685 free_hdcp_wq:
2686     if (platform->hdcp_workqueue)
2687         destroy_workqueue(platform->hdcp_workqueue);
2688 
2689     return ret;
2690 }
2691 
2692 static int anx7625_i2c_remove(struct i2c_client *client)
2693 {
2694     struct anx7625_data *platform = i2c_get_clientdata(client);
2695 
2696     drm_bridge_remove(&platform->bridge);
2697 
2698     if (platform->pdata.intp_irq)
2699         destroy_workqueue(platform->workqueue);
2700 
2701     if (platform->hdcp_workqueue) {
2702         cancel_delayed_work(&platform->hdcp_work);
2703         flush_workqueue(platform->hdcp_workqueue);
2704         destroy_workqueue(platform->hdcp_workqueue);
2705     }
2706 
2707     if (!platform->pdata.low_power_mode)
2708         pm_runtime_put_sync_suspend(&client->dev);
2709 
2710     if (platform->pdata.audio_en)
2711         anx7625_unregister_audio(platform);
2712 
2713     return 0;
2714 }
2715 
2716 static const struct i2c_device_id anx7625_id[] = {
2717     {"anx7625", 0},
2718     {}
2719 };
2720 
2721 MODULE_DEVICE_TABLE(i2c, anx7625_id);
2722 
2723 static const struct of_device_id anx_match_table[] = {
2724     {.compatible = "analogix,anx7625",},
2725     {},
2726 };
2727 MODULE_DEVICE_TABLE(of, anx_match_table);
2728 
2729 static struct i2c_driver anx7625_driver = {
2730     .driver = {
2731         .name = "anx7625",
2732         .of_match_table = anx_match_table,
2733         .pm = &anx7625_pm_ops,
2734     },
2735     .probe = anx7625_i2c_probe,
2736     .remove = anx7625_i2c_remove,
2737 
2738     .id_table = anx7625_id,
2739 };
2740 
2741 module_i2c_driver(anx7625_driver);
2742 
2743 MODULE_DESCRIPTION("MIPI2DP anx7625 driver");
2744 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>");
2745 MODULE_LICENSE("GPL v2");
2746 MODULE_VERSION(ANX7625_DRV_VERSION);
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