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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Analogix DP (Display Port) core interface driver.
0004 *
0005 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
0006 * Author: Jingoo Han <jg1.han@samsung.com>
0007 */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/component.h>
0011 #include <linux/err.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/phy/phy.h>
0019 #include <linux/platform_device.h>
0020 
0021 #include <drm/bridge/analogix_dp.h>
0022 #include <drm/drm_atomic.h>
0023 #include <drm/drm_atomic_helper.h>
0024 #include <drm/drm_bridge.h>
0025 #include <drm/drm_crtc.h>
0026 #include <drm/drm_device.h>
0027 #include <drm/drm_edid.h>
0028 #include <drm/drm_panel.h>
0029 #include <drm/drm_print.h>
0030 #include <drm/drm_probe_helper.h>
0031 
0032 #include "analogix_dp_core.h"
0033 #include "analogix_dp_reg.h"
0034 
0035 #define to_dp(nm)   container_of(nm, struct analogix_dp_device, nm)
0036 
0037 static const bool verify_fast_training;
0038 
0039 struct bridge_init {
0040     struct i2c_client *client;
0041     struct device_node *node;
0042 };
0043 
0044 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
0045 {
0046     int ret;
0047 
0048     analogix_dp_reset(dp);
0049 
0050     analogix_dp_swreset(dp);
0051 
0052     analogix_dp_init_analog_param(dp);
0053     analogix_dp_init_interrupt(dp);
0054 
0055     /* SW defined function Normal operation */
0056     analogix_dp_enable_sw_function(dp);
0057 
0058     analogix_dp_config_interrupt(dp);
0059     ret = analogix_dp_init_analog_func(dp);
0060     if (ret)
0061         return ret;
0062 
0063     analogix_dp_init_hpd(dp);
0064     analogix_dp_init_aux(dp);
0065     return 0;
0066 }
0067 
0068 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
0069 {
0070     int timeout_loop = 0;
0071 
0072     while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
0073         if (analogix_dp_get_plug_in_status(dp) == 0)
0074             return 0;
0075 
0076         timeout_loop++;
0077         usleep_range(1000, 1100);
0078     }
0079 
0080     /*
0081      * Some edp screen do not have hpd signal, so we can't just
0082      * return failed when hpd plug in detect failed, DT property
0083      * "force-hpd" would indicate whether driver need this.
0084      */
0085     if (!dp->force_hpd)
0086         return -ETIMEDOUT;
0087 
0088     /*
0089      * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
0090      * will not work, so we need to give a force hpd action to
0091      * set HPD_STATUS manually.
0092      */
0093     dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
0094 
0095     analogix_dp_force_hpd(dp);
0096 
0097     if (analogix_dp_get_plug_in_status(dp) != 0) {
0098         dev_err(dp->dev, "failed to get hpd plug in status\n");
0099         return -EINVAL;
0100     }
0101 
0102     dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
0103 
0104     return 0;
0105 }
0106 
0107 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
0108 {
0109     unsigned char psr_version;
0110     int ret;
0111 
0112     ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
0113     if (ret != 1) {
0114         dev_err(dp->dev, "failed to get PSR version, disable it\n");
0115         return false;
0116     }
0117 
0118     dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
0119     return psr_version & DP_PSR_IS_SUPPORTED;
0120 }
0121 
0122 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
0123 {
0124     unsigned char psr_en;
0125     int ret;
0126 
0127     /* Disable psr function */
0128     ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
0129     if (ret != 1) {
0130         dev_err(dp->dev, "failed to get psr config\n");
0131         goto end;
0132     }
0133 
0134     psr_en &= ~DP_PSR_ENABLE;
0135     ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
0136     if (ret != 1) {
0137         dev_err(dp->dev, "failed to disable panel psr\n");
0138         goto end;
0139     }
0140 
0141     /* Main-Link transmitter remains active during PSR active states */
0142     psr_en = DP_PSR_CRC_VERIFICATION;
0143     ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
0144     if (ret != 1) {
0145         dev_err(dp->dev, "failed to set panel psr\n");
0146         goto end;
0147     }
0148 
0149     /* Enable psr function */
0150     psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
0151     ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
0152     if (ret != 1) {
0153         dev_err(dp->dev, "failed to set panel psr\n");
0154         goto end;
0155     }
0156 
0157     analogix_dp_enable_psr_crc(dp);
0158 
0159     dp->psr_supported = true;
0160 
0161     return 0;
0162 end:
0163     dev_err(dp->dev, "enable psr fail, force to disable psr\n");
0164 
0165     return ret;
0166 }
0167 
0168 static int
0169 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
0170                        bool enable)
0171 {
0172     u8 data;
0173     int ret;
0174 
0175     ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
0176     if (ret != 1)
0177         return ret;
0178 
0179     if (enable)
0180         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
0181                      DP_LANE_COUNT_ENHANCED_FRAME_EN |
0182                      DPCD_LANE_COUNT_SET(data));
0183     else
0184         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
0185                      DPCD_LANE_COUNT_SET(data));
0186 
0187     return ret < 0 ? ret : 0;
0188 }
0189 
0190 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
0191                           u8 *enhanced_mode_support)
0192 {
0193     u8 data;
0194     int ret;
0195 
0196     ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
0197     if (ret != 1) {
0198         *enhanced_mode_support = 0;
0199         return ret;
0200     }
0201 
0202     *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
0203 
0204     return 0;
0205 }
0206 
0207 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
0208 {
0209     u8 data;
0210     int ret;
0211 
0212     ret = analogix_dp_is_enhanced_mode_available(dp, &data);
0213     if (ret < 0)
0214         return ret;
0215 
0216     ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
0217     if (ret < 0)
0218         return ret;
0219 
0220     analogix_dp_enable_enhanced_mode(dp, data);
0221 
0222     return 0;
0223 }
0224 
0225 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
0226 {
0227     int ret;
0228 
0229     analogix_dp_set_training_pattern(dp, DP_NONE);
0230 
0231     ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
0232                  DP_TRAINING_PATTERN_DISABLE);
0233 
0234     return ret < 0 ? ret : 0;
0235 }
0236 
0237 static void
0238 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
0239                        int pre_emphasis, int lane)
0240 {
0241     switch (lane) {
0242     case 0:
0243         analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
0244         break;
0245     case 1:
0246         analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
0247         break;
0248 
0249     case 2:
0250         analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
0251         break;
0252 
0253     case 3:
0254         analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
0255         break;
0256     }
0257 }
0258 
0259 static int analogix_dp_link_start(struct analogix_dp_device *dp)
0260 {
0261     u8 buf[4];
0262     int lane, lane_count, pll_tries, retval;
0263 
0264     lane_count = dp->link_train.lane_count;
0265 
0266     dp->link_train.lt_state = CLOCK_RECOVERY;
0267     dp->link_train.eq_loop = 0;
0268 
0269     for (lane = 0; lane < lane_count; lane++)
0270         dp->link_train.cr_loop[lane] = 0;
0271 
0272     /* Set link rate and count as you want to establish*/
0273     analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
0274     analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
0275 
0276     /* Setup RX configuration */
0277     buf[0] = dp->link_train.link_rate;
0278     buf[1] = dp->link_train.lane_count;
0279     retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
0280     if (retval < 0)
0281         return retval;
0282     /* set enhanced mode if available */
0283     retval = analogix_dp_set_enhanced_mode(dp);
0284     if (retval < 0) {
0285         dev_err(dp->dev, "failed to set enhance mode\n");
0286         return retval;
0287     }
0288 
0289     /* Set TX pre-emphasis to minimum */
0290     for (lane = 0; lane < lane_count; lane++)
0291         analogix_dp_set_lane_lane_pre_emphasis(dp,
0292             PRE_EMPHASIS_LEVEL_0, lane);
0293 
0294     /* Wait for PLL lock */
0295     pll_tries = 0;
0296     while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
0297         if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
0298             dev_err(dp->dev, "Wait for PLL lock timed out\n");
0299             return -ETIMEDOUT;
0300         }
0301 
0302         pll_tries++;
0303         usleep_range(90, 120);
0304     }
0305 
0306     /* Set training pattern 1 */
0307     analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
0308 
0309     /* Set RX training pattern */
0310     retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
0311                     DP_LINK_SCRAMBLING_DISABLE |
0312                     DP_TRAINING_PATTERN_1);
0313     if (retval < 0)
0314         return retval;
0315 
0316     for (lane = 0; lane < lane_count; lane++)
0317         buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
0318                 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
0319 
0320     retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
0321                    lane_count);
0322     if (retval < 0)
0323         return retval;
0324 
0325     return 0;
0326 }
0327 
0328 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
0329 {
0330     int shift = (lane & 1) * 4;
0331     u8 link_value = link_status[lane >> 1];
0332 
0333     return (link_value >> shift) & 0xf;
0334 }
0335 
0336 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
0337 {
0338     int lane;
0339     u8 lane_status;
0340 
0341     for (lane = 0; lane < lane_count; lane++) {
0342         lane_status = analogix_dp_get_lane_status(link_status, lane);
0343         if ((lane_status & DP_LANE_CR_DONE) == 0)
0344             return -EINVAL;
0345     }
0346     return 0;
0347 }
0348 
0349 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
0350                      int lane_count)
0351 {
0352     int lane;
0353     u8 lane_status;
0354 
0355     if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
0356         return -EINVAL;
0357 
0358     for (lane = 0; lane < lane_count; lane++) {
0359         lane_status = analogix_dp_get_lane_status(link_status, lane);
0360         lane_status &= DP_CHANNEL_EQ_BITS;
0361         if (lane_status != DP_CHANNEL_EQ_BITS)
0362             return -EINVAL;
0363     }
0364 
0365     return 0;
0366 }
0367 
0368 static unsigned char
0369 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
0370 {
0371     int shift = (lane & 1) * 4;
0372     u8 link_value = adjust_request[lane >> 1];
0373 
0374     return (link_value >> shift) & 0x3;
0375 }
0376 
0377 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
0378                     u8 adjust_request[2],
0379                     int lane)
0380 {
0381     int shift = (lane & 1) * 4;
0382     u8 link_value = adjust_request[lane >> 1];
0383 
0384     return ((link_value >> shift) & 0xc) >> 2;
0385 }
0386 
0387 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
0388                            u8 training_lane_set, int lane)
0389 {
0390     switch (lane) {
0391     case 0:
0392         analogix_dp_set_lane0_link_training(dp, training_lane_set);
0393         break;
0394     case 1:
0395         analogix_dp_set_lane1_link_training(dp, training_lane_set);
0396         break;
0397 
0398     case 2:
0399         analogix_dp_set_lane2_link_training(dp, training_lane_set);
0400         break;
0401 
0402     case 3:
0403         analogix_dp_set_lane3_link_training(dp, training_lane_set);
0404         break;
0405     }
0406 }
0407 
0408 static unsigned int
0409 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
0410                    int lane)
0411 {
0412     u32 reg;
0413 
0414     switch (lane) {
0415     case 0:
0416         reg = analogix_dp_get_lane0_link_training(dp);
0417         break;
0418     case 1:
0419         reg = analogix_dp_get_lane1_link_training(dp);
0420         break;
0421     case 2:
0422         reg = analogix_dp_get_lane2_link_training(dp);
0423         break;
0424     case 3:
0425         reg = analogix_dp_get_lane3_link_training(dp);
0426         break;
0427     default:
0428         WARN_ON(1);
0429         return 0;
0430     }
0431 
0432     return reg;
0433 }
0434 
0435 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
0436 {
0437     analogix_dp_training_pattern_dis(dp);
0438     analogix_dp_set_enhanced_mode(dp);
0439 
0440     dp->link_train.lt_state = FAILED;
0441 }
0442 
0443 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
0444                          u8 adjust_request[2])
0445 {
0446     int lane, lane_count;
0447     u8 voltage_swing, pre_emphasis, training_lane;
0448 
0449     lane_count = dp->link_train.lane_count;
0450     for (lane = 0; lane < lane_count; lane++) {
0451         voltage_swing = analogix_dp_get_adjust_request_voltage(
0452                         adjust_request, lane);
0453         pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
0454                         adjust_request, lane);
0455         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
0456                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
0457 
0458         if (voltage_swing == VOLTAGE_LEVEL_3)
0459             training_lane |= DP_TRAIN_MAX_SWING_REACHED;
0460         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
0461             training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
0462 
0463         dp->link_train.training_lane[lane] = training_lane;
0464     }
0465 }
0466 
0467 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
0468 {
0469     int lane, lane_count, retval;
0470     u8 voltage_swing, pre_emphasis, training_lane;
0471     u8 link_status[2], adjust_request[2];
0472 
0473     usleep_range(100, 101);
0474 
0475     lane_count = dp->link_train.lane_count;
0476 
0477     retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
0478     if (retval < 0)
0479         return retval;
0480 
0481     retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
0482                   adjust_request, 2);
0483     if (retval < 0)
0484         return retval;
0485 
0486     if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
0487         /* set training pattern 2 for EQ */
0488         analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
0489 
0490         retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
0491                         DP_LINK_SCRAMBLING_DISABLE |
0492                         DP_TRAINING_PATTERN_2);
0493         if (retval < 0)
0494             return retval;
0495 
0496         dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
0497         dp->link_train.lt_state = EQUALIZER_TRAINING;
0498     } else {
0499         for (lane = 0; lane < lane_count; lane++) {
0500             training_lane = analogix_dp_get_lane_link_training(
0501                             dp, lane);
0502             voltage_swing = analogix_dp_get_adjust_request_voltage(
0503                             adjust_request, lane);
0504             pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
0505                             adjust_request, lane);
0506 
0507             if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
0508                     voltage_swing &&
0509                 DPCD_PRE_EMPHASIS_GET(training_lane) ==
0510                     pre_emphasis)
0511                 dp->link_train.cr_loop[lane]++;
0512 
0513             if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
0514                 voltage_swing == VOLTAGE_LEVEL_3 ||
0515                 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
0516                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
0517                     dp->link_train.cr_loop[lane],
0518                     voltage_swing, pre_emphasis);
0519                 analogix_dp_reduce_link_rate(dp);
0520                 return -EIO;
0521             }
0522         }
0523     }
0524 
0525     analogix_dp_get_adjust_training_lane(dp, adjust_request);
0526 
0527     for (lane = 0; lane < lane_count; lane++)
0528         analogix_dp_set_lane_link_training(dp,
0529             dp->link_train.training_lane[lane], lane);
0530 
0531     retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
0532                    dp->link_train.training_lane, lane_count);
0533     if (retval < 0)
0534         return retval;
0535 
0536     return 0;
0537 }
0538 
0539 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
0540 {
0541     int lane, lane_count, retval;
0542     u32 reg;
0543     u8 link_align, link_status[2], adjust_request[2];
0544 
0545     usleep_range(400, 401);
0546 
0547     lane_count = dp->link_train.lane_count;
0548 
0549     retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
0550     if (retval < 0)
0551         return retval;
0552 
0553     if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
0554         analogix_dp_reduce_link_rate(dp);
0555         return -EIO;
0556     }
0557 
0558     retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
0559                   adjust_request, 2);
0560     if (retval < 0)
0561         return retval;
0562 
0563     retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
0564                    &link_align);
0565     if (retval < 0)
0566         return retval;
0567 
0568     analogix_dp_get_adjust_training_lane(dp, adjust_request);
0569 
0570     if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
0571         /* traing pattern Set to Normal */
0572         retval = analogix_dp_training_pattern_dis(dp);
0573         if (retval < 0)
0574             return retval;
0575 
0576         dev_dbg(dp->dev, "Link Training success!\n");
0577         analogix_dp_get_link_bandwidth(dp, &reg);
0578         dp->link_train.link_rate = reg;
0579         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
0580             dp->link_train.link_rate);
0581 
0582         analogix_dp_get_lane_count(dp, &reg);
0583         dp->link_train.lane_count = reg;
0584         dev_dbg(dp->dev, "final lane count = %.2x\n",
0585             dp->link_train.lane_count);
0586 
0587         dp->link_train.lt_state = FINISHED;
0588 
0589         return 0;
0590     }
0591 
0592     /* not all locked */
0593     dp->link_train.eq_loop++;
0594 
0595     if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
0596         dev_err(dp->dev, "EQ Max loop\n");
0597         analogix_dp_reduce_link_rate(dp);
0598         return -EIO;
0599     }
0600 
0601     for (lane = 0; lane < lane_count; lane++)
0602         analogix_dp_set_lane_link_training(dp,
0603             dp->link_train.training_lane[lane], lane);
0604 
0605     retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
0606                    dp->link_train.training_lane, lane_count);
0607     if (retval < 0)
0608         return retval;
0609 
0610     return 0;
0611 }
0612 
0613 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
0614                          u8 *bandwidth)
0615 {
0616     u8 data;
0617 
0618     /*
0619      * For DP rev.1.1, Maximum link rate of Main Link lanes
0620      * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
0621      * For DP rev.1.2, Maximum link rate of Main Link lanes
0622      * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
0623      */
0624     drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
0625     *bandwidth = data;
0626 }
0627 
0628 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
0629                           u8 *lane_count)
0630 {
0631     u8 data;
0632 
0633     /*
0634      * For DP rev.1.1, Maximum number of Main Link lanes
0635      * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
0636      */
0637     drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
0638     *lane_count = DPCD_MAX_LANE_COUNT(data);
0639 }
0640 
0641 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
0642                        u32 max_lanes, u32 max_rate)
0643 {
0644     int retval = 0;
0645     bool training_finished = false;
0646 
0647     /*
0648      * MACRO_RST must be applied after the PLL_LOCK to avoid
0649      * the DP inter pair skew issue for at least 10 us
0650      */
0651     analogix_dp_reset_macro(dp);
0652 
0653     /* Initialize by reading RX's DPCD */
0654     analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
0655     analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
0656 
0657     if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
0658         (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
0659         (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
0660         dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
0661             dp->link_train.link_rate);
0662         dp->link_train.link_rate = DP_LINK_BW_1_62;
0663     }
0664 
0665     if (dp->link_train.lane_count == 0) {
0666         dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
0667             dp->link_train.lane_count);
0668         dp->link_train.lane_count = (u8)LANE_COUNT1;
0669     }
0670 
0671     /* Setup TX lane count & rate */
0672     if (dp->link_train.lane_count > max_lanes)
0673         dp->link_train.lane_count = max_lanes;
0674     if (dp->link_train.link_rate > max_rate)
0675         dp->link_train.link_rate = max_rate;
0676 
0677     /* All DP analog module power up */
0678     analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
0679 
0680     dp->link_train.lt_state = START;
0681 
0682     /* Process here */
0683     while (!retval && !training_finished) {
0684         switch (dp->link_train.lt_state) {
0685         case START:
0686             retval = analogix_dp_link_start(dp);
0687             if (retval)
0688                 dev_err(dp->dev, "LT link start failed!\n");
0689             break;
0690         case CLOCK_RECOVERY:
0691             retval = analogix_dp_process_clock_recovery(dp);
0692             if (retval)
0693                 dev_err(dp->dev, "LT CR failed!\n");
0694             break;
0695         case EQUALIZER_TRAINING:
0696             retval = analogix_dp_process_equalizer_training(dp);
0697             if (retval)
0698                 dev_err(dp->dev, "LT EQ failed!\n");
0699             break;
0700         case FINISHED:
0701             training_finished = 1;
0702             break;
0703         case FAILED:
0704             return -EREMOTEIO;
0705         }
0706     }
0707     if (retval)
0708         dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
0709 
0710     return retval;
0711 }
0712 
0713 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
0714 {
0715     int i, ret;
0716     u8 link_align, link_status[2];
0717     enum pll_status status;
0718 
0719     analogix_dp_reset_macro(dp);
0720 
0721     analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
0722     analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
0723 
0724     for (i = 0; i < dp->link_train.lane_count; i++) {
0725         analogix_dp_set_lane_link_training(dp,
0726             dp->link_train.training_lane[i], i);
0727     }
0728 
0729     ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
0730                  status != PLL_UNLOCKED, 120,
0731                  120 * DP_TIMEOUT_LOOP_COUNT);
0732     if (ret) {
0733         DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
0734         return ret;
0735     }
0736 
0737     /* source Set training pattern 1 */
0738     analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
0739     /* From DP spec, pattern must be on-screen for a minimum 500us */
0740     usleep_range(500, 600);
0741 
0742     analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
0743     /* From DP spec, pattern must be on-screen for a minimum 500us */
0744     usleep_range(500, 600);
0745 
0746     /* TODO: enhanced_mode?*/
0747     analogix_dp_set_training_pattern(dp, DP_NONE);
0748 
0749     /*
0750      * Useful for debugging issues with fast link training, disable for more
0751      * speed
0752      */
0753     if (verify_fast_training) {
0754         ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
0755                     &link_align);
0756         if (ret < 0) {
0757             DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
0758                       ret);
0759             return ret;
0760         }
0761 
0762         ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
0763                        2);
0764         if (ret < 0) {
0765             DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
0766                       ret);
0767             return ret;
0768         }
0769 
0770         if (analogix_dp_clock_recovery_ok(link_status,
0771                           dp->link_train.lane_count)) {
0772             DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
0773             analogix_dp_reduce_link_rate(dp);
0774             return -EIO;
0775         }
0776 
0777         if (analogix_dp_channel_eq_ok(link_status, link_align,
0778                           dp->link_train.lane_count)) {
0779             DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
0780             analogix_dp_reduce_link_rate(dp);
0781             return -EIO;
0782         }
0783     }
0784 
0785     return 0;
0786 }
0787 
0788 static int analogix_dp_train_link(struct analogix_dp_device *dp)
0789 {
0790     if (dp->fast_train_enable)
0791         return analogix_dp_fast_link_train(dp);
0792 
0793     return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
0794                        dp->video_info.max_link_rate);
0795 }
0796 
0797 static int analogix_dp_config_video(struct analogix_dp_device *dp)
0798 {
0799     int timeout_loop = 0;
0800     int done_count = 0;
0801 
0802     analogix_dp_config_video_slave_mode(dp);
0803 
0804     analogix_dp_set_video_color_format(dp);
0805 
0806     if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
0807         dev_err(dp->dev, "PLL is not locked yet.\n");
0808         return -EINVAL;
0809     }
0810 
0811     for (;;) {
0812         timeout_loop++;
0813         if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
0814             break;
0815         if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
0816             dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
0817             return -ETIMEDOUT;
0818         }
0819         usleep_range(1000, 1001);
0820     }
0821 
0822     /* Set to use the register calculated M/N video */
0823     analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
0824 
0825     /* For video bist, Video timing must be generated by register */
0826     analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
0827 
0828     /* Disable video mute */
0829     analogix_dp_enable_video_mute(dp, 0);
0830 
0831     /* Configure video slave mode */
0832     analogix_dp_enable_video_master(dp, 0);
0833 
0834     /* Enable video */
0835     analogix_dp_start_video(dp);
0836 
0837     timeout_loop = 0;
0838 
0839     for (;;) {
0840         timeout_loop++;
0841         if (analogix_dp_is_video_stream_on(dp) == 0) {
0842             done_count++;
0843             if (done_count > 10)
0844                 break;
0845         } else if (done_count) {
0846             done_count = 0;
0847         }
0848         if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
0849             dev_warn(dp->dev,
0850                  "Ignoring timeout of video streamclk ok\n");
0851             break;
0852         }
0853 
0854         usleep_range(1000, 1001);
0855     }
0856 
0857     return 0;
0858 }
0859 
0860 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
0861                        bool enable)
0862 {
0863     u8 data;
0864     int ret;
0865 
0866     if (enable) {
0867         analogix_dp_enable_scrambling(dp);
0868 
0869         ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
0870                     &data);
0871         if (ret != 1)
0872             return ret;
0873         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
0874                    (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
0875     } else {
0876         analogix_dp_disable_scrambling(dp);
0877 
0878         ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
0879                     &data);
0880         if (ret != 1)
0881             return ret;
0882         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
0883                    (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
0884     }
0885     return ret < 0 ? ret : 0;
0886 }
0887 
0888 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
0889 {
0890     struct analogix_dp_device *dp = arg;
0891     irqreturn_t ret = IRQ_NONE;
0892     enum dp_irq_type irq_type;
0893 
0894     irq_type = analogix_dp_get_irq_type(dp);
0895     if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
0896         analogix_dp_mute_hpd_interrupt(dp);
0897         ret = IRQ_WAKE_THREAD;
0898     }
0899 
0900     return ret;
0901 }
0902 
0903 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
0904 {
0905     struct analogix_dp_device *dp = arg;
0906     enum dp_irq_type irq_type;
0907 
0908     irq_type = analogix_dp_get_irq_type(dp);
0909     if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
0910         irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
0911         dev_dbg(dp->dev, "Detected cable status changed!\n");
0912         if (dp->drm_dev)
0913             drm_helper_hpd_irq_event(dp->drm_dev);
0914     }
0915 
0916     if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
0917         analogix_dp_clear_hotplug_interrupts(dp);
0918         analogix_dp_unmute_hpd_interrupt(dp);
0919     }
0920 
0921     return IRQ_HANDLED;
0922 }
0923 
0924 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
0925 {
0926     int ret;
0927     u8 spread;
0928 
0929     ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
0930     if (ret != 1) {
0931         dev_err(dp->dev, "failed to read downspread %d\n", ret);
0932         return ret;
0933     }
0934     dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
0935     dev_dbg(dp->dev, "fast link training %s\n",
0936         dp->fast_train_enable ? "supported" : "unsupported");
0937     return 0;
0938 }
0939 
0940 static int analogix_dp_commit(struct analogix_dp_device *dp)
0941 {
0942     int ret;
0943 
0944     /* Keep the panel disabled while we configure video */
0945     if (dp->plat_data->panel) {
0946         if (drm_panel_disable(dp->plat_data->panel))
0947             DRM_ERROR("failed to disable the panel\n");
0948     }
0949 
0950     ret = analogix_dp_train_link(dp);
0951     if (ret) {
0952         dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
0953         return ret;
0954     }
0955 
0956     ret = analogix_dp_enable_scramble(dp, 1);
0957     if (ret < 0) {
0958         dev_err(dp->dev, "can not enable scramble\n");
0959         return ret;
0960     }
0961 
0962     analogix_dp_init_video(dp);
0963     ret = analogix_dp_config_video(dp);
0964     if (ret) {
0965         dev_err(dp->dev, "unable to config video\n");
0966         return ret;
0967     }
0968 
0969     /* Safe to enable the panel now */
0970     if (dp->plat_data->panel) {
0971         ret = drm_panel_enable(dp->plat_data->panel);
0972         if (ret) {
0973             DRM_ERROR("failed to enable the panel\n");
0974             return ret;
0975         }
0976     }
0977 
0978     /* Check whether panel supports fast training */
0979     ret = analogix_dp_fast_link_train_detection(dp);
0980     if (ret)
0981         return ret;
0982 
0983     if (analogix_dp_detect_sink_psr(dp)) {
0984         ret = analogix_dp_enable_sink_psr(dp);
0985         if (ret)
0986             return ret;
0987     }
0988 
0989     return ret;
0990 }
0991 
0992 static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
0993 {
0994     struct dp_sdp psr_vsc;
0995     int ret;
0996     u8 sink;
0997 
0998     ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
0999     if (ret != 1)
1000         DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1001     else if (sink == DP_PSR_SINK_ACTIVE_RFB)
1002         return 0;
1003 
1004     /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1005     memset(&psr_vsc, 0, sizeof(psr_vsc));
1006     psr_vsc.sdp_header.HB0 = 0;
1007     psr_vsc.sdp_header.HB1 = 0x7;
1008     psr_vsc.sdp_header.HB2 = 0x2;
1009     psr_vsc.sdp_header.HB3 = 0x8;
1010     psr_vsc.db[0] = 0;
1011     psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
1012 
1013     ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1014     if (!ret)
1015         analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
1016 
1017     return ret;
1018 }
1019 
1020 static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
1021 {
1022     struct dp_sdp psr_vsc;
1023     int ret;
1024     u8 sink;
1025 
1026     analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
1027 
1028     ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1029     if (ret != 1) {
1030         DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
1031         return ret;
1032     }
1033 
1034     ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1035     if (ret != 1) {
1036         DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1037         return ret;
1038     } else if (sink == DP_PSR_SINK_INACTIVE) {
1039         DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
1040         return 0;
1041     }
1042 
1043     ret = analogix_dp_train_link(dp);
1044     if (ret) {
1045         DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
1046         return ret;
1047     }
1048 
1049     /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1050     memset(&psr_vsc, 0, sizeof(psr_vsc));
1051     psr_vsc.sdp_header.HB0 = 0;
1052     psr_vsc.sdp_header.HB1 = 0x7;
1053     psr_vsc.sdp_header.HB2 = 0x2;
1054     psr_vsc.sdp_header.HB3 = 0x8;
1055 
1056     psr_vsc.db[0] = 0;
1057     psr_vsc.db[1] = 0;
1058 
1059     return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1060 }
1061 
1062 /*
1063  * This function is a bit of a catch-all for panel preparation, hopefully
1064  * simplifying the logic of functions that need to prepare/unprepare the panel
1065  * below.
1066  *
1067  * If @prepare is true, this function will prepare the panel. Conversely, if it
1068  * is false, the panel will be unprepared.
1069  *
1070  * If @is_modeset_prepare is true, the function will disregard the current state
1071  * of the panel and either prepare/unprepare the panel based on @prepare. Once
1072  * it finishes, it will update dp->panel_is_modeset to reflect the current state
1073  * of the panel.
1074  */
1075 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1076                      bool prepare, bool is_modeset_prepare)
1077 {
1078     int ret = 0;
1079 
1080     if (!dp->plat_data->panel)
1081         return 0;
1082 
1083     mutex_lock(&dp->panel_lock);
1084 
1085     /*
1086      * Exit early if this is a temporary prepare/unprepare and we're already
1087      * modeset (since we neither want to prepare twice or unprepare early).
1088      */
1089     if (dp->panel_is_modeset && !is_modeset_prepare)
1090         goto out;
1091 
1092     if (prepare)
1093         ret = drm_panel_prepare(dp->plat_data->panel);
1094     else
1095         ret = drm_panel_unprepare(dp->plat_data->panel);
1096 
1097     if (ret)
1098         goto out;
1099 
1100     if (is_modeset_prepare)
1101         dp->panel_is_modeset = prepare;
1102 
1103 out:
1104     mutex_unlock(&dp->panel_lock);
1105     return ret;
1106 }
1107 
1108 static int analogix_dp_get_modes(struct drm_connector *connector)
1109 {
1110     struct analogix_dp_device *dp = to_dp(connector);
1111     struct edid *edid;
1112     int ret, num_modes = 0;
1113 
1114     if (dp->plat_data->panel) {
1115         num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
1116     } else {
1117         ret = analogix_dp_prepare_panel(dp, true, false);
1118         if (ret) {
1119             DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1120             return 0;
1121         }
1122 
1123         edid = drm_get_edid(connector, &dp->aux.ddc);
1124         if (edid) {
1125             drm_connector_update_edid_property(&dp->connector,
1126                                edid);
1127             num_modes += drm_add_edid_modes(&dp->connector, edid);
1128             kfree(edid);
1129         }
1130 
1131         ret = analogix_dp_prepare_panel(dp, false, false);
1132         if (ret)
1133             DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1134     }
1135 
1136     if (dp->plat_data->get_modes)
1137         num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1138 
1139     return num_modes;
1140 }
1141 
1142 static struct drm_encoder *
1143 analogix_dp_best_encoder(struct drm_connector *connector)
1144 {
1145     struct analogix_dp_device *dp = to_dp(connector);
1146 
1147     return dp->encoder;
1148 }
1149 
1150 
1151 static int analogix_dp_atomic_check(struct drm_connector *connector,
1152                     struct drm_atomic_state *state)
1153 {
1154     struct analogix_dp_device *dp = to_dp(connector);
1155     struct drm_connector_state *conn_state;
1156     struct drm_crtc_state *crtc_state;
1157 
1158     conn_state = drm_atomic_get_new_connector_state(state, connector);
1159     if (WARN_ON(!conn_state))
1160         return -ENODEV;
1161 
1162     conn_state->self_refresh_aware = true;
1163 
1164     if (!conn_state->crtc)
1165         return 0;
1166 
1167     crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1168     if (!crtc_state)
1169         return 0;
1170 
1171     if (crtc_state->self_refresh_active && !dp->psr_supported)
1172         return -EINVAL;
1173 
1174     return 0;
1175 }
1176 
1177 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1178     .get_modes = analogix_dp_get_modes,
1179     .best_encoder = analogix_dp_best_encoder,
1180     .atomic_check = analogix_dp_atomic_check,
1181 };
1182 
1183 static enum drm_connector_status
1184 analogix_dp_detect(struct drm_connector *connector, bool force)
1185 {
1186     struct analogix_dp_device *dp = to_dp(connector);
1187     enum drm_connector_status status = connector_status_disconnected;
1188     int ret;
1189 
1190     if (dp->plat_data->panel)
1191         return connector_status_connected;
1192 
1193     ret = analogix_dp_prepare_panel(dp, true, false);
1194     if (ret) {
1195         DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1196         return connector_status_disconnected;
1197     }
1198 
1199     if (!analogix_dp_detect_hpd(dp))
1200         status = connector_status_connected;
1201 
1202     ret = analogix_dp_prepare_panel(dp, false, false);
1203     if (ret)
1204         DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1205 
1206     return status;
1207 }
1208 
1209 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1210     .fill_modes = drm_helper_probe_single_connector_modes,
1211     .detect = analogix_dp_detect,
1212     .destroy = drm_connector_cleanup,
1213     .reset = drm_atomic_helper_connector_reset,
1214     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1215     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1216 };
1217 
1218 static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
1219                      enum drm_bridge_attach_flags flags)
1220 {
1221     struct analogix_dp_device *dp = bridge->driver_private;
1222     struct drm_encoder *encoder = dp->encoder;
1223     struct drm_connector *connector = NULL;
1224     int ret = 0;
1225 
1226     if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1227         DRM_ERROR("Fix bridge driver to make connector optional!");
1228         return -EINVAL;
1229     }
1230 
1231     if (!bridge->encoder) {
1232         DRM_ERROR("Parent encoder object not found");
1233         return -ENODEV;
1234     }
1235 
1236     if (!dp->plat_data->skip_connector) {
1237         connector = &dp->connector;
1238         connector->polled = DRM_CONNECTOR_POLL_HPD;
1239 
1240         ret = drm_connector_init(dp->drm_dev, connector,
1241                      &analogix_dp_connector_funcs,
1242                      DRM_MODE_CONNECTOR_eDP);
1243         if (ret) {
1244             DRM_ERROR("Failed to initialize connector with drm\n");
1245             return ret;
1246         }
1247 
1248         drm_connector_helper_add(connector,
1249                      &analogix_dp_connector_helper_funcs);
1250         drm_connector_attach_encoder(connector, encoder);
1251     }
1252 
1253     /*
1254      * NOTE: the connector registration is implemented in analogix
1255      * platform driver, that to say connector would be exist after
1256      * plat_data->attch return, that's why we record the connector
1257      * point after plat attached.
1258      */
1259     if (dp->plat_data->attach) {
1260         ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1261         if (ret) {
1262             DRM_ERROR("Failed at platform attach func\n");
1263             return ret;
1264         }
1265     }
1266 
1267     return 0;
1268 }
1269 
1270 static
1271 struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp,
1272                       struct drm_atomic_state *state)
1273 {
1274     struct drm_encoder *encoder = dp->encoder;
1275     struct drm_connector *connector;
1276     struct drm_connector_state *conn_state;
1277 
1278     connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
1279     if (!connector)
1280         return NULL;
1281 
1282     conn_state = drm_atomic_get_old_connector_state(state, connector);
1283     if (!conn_state)
1284         return NULL;
1285 
1286     return conn_state->crtc;
1287 }
1288 
1289 static
1290 struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1291                       struct drm_atomic_state *state)
1292 {
1293     struct drm_encoder *encoder = dp->encoder;
1294     struct drm_connector *connector;
1295     struct drm_connector_state *conn_state;
1296 
1297     connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1298     if (!connector)
1299         return NULL;
1300 
1301     conn_state = drm_atomic_get_new_connector_state(state, connector);
1302     if (!conn_state)
1303         return NULL;
1304 
1305     return conn_state->crtc;
1306 }
1307 
1308 static void
1309 analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1310                      struct drm_bridge_state *old_bridge_state)
1311 {
1312     struct drm_atomic_state *old_state = old_bridge_state->base.state;
1313     struct analogix_dp_device *dp = bridge->driver_private;
1314     struct drm_crtc *crtc;
1315     struct drm_crtc_state *old_crtc_state;
1316     int ret;
1317 
1318     crtc = analogix_dp_get_new_crtc(dp, old_state);
1319     if (!crtc)
1320         return;
1321 
1322     old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1323     /* Don't touch the panel if we're coming back from PSR */
1324     if (old_crtc_state && old_crtc_state->self_refresh_active)
1325         return;
1326 
1327     ret = analogix_dp_prepare_panel(dp, true, true);
1328     if (ret)
1329         DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1330 }
1331 
1332 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1333 {
1334     int ret;
1335 
1336     pm_runtime_get_sync(dp->dev);
1337 
1338     ret = clk_prepare_enable(dp->clock);
1339     if (ret < 0) {
1340         DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1341         goto out_dp_clk_pre;
1342     }
1343 
1344     if (dp->plat_data->power_on_start)
1345         dp->plat_data->power_on_start(dp->plat_data);
1346 
1347     phy_power_on(dp->phy);
1348 
1349     ret = analogix_dp_init_dp(dp);
1350     if (ret)
1351         goto out_dp_init;
1352 
1353     /*
1354      * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1355      * We should first make sure the HPD signal is asserted high by device
1356      * when we want to establish a link with it.
1357      */
1358     ret = analogix_dp_detect_hpd(dp);
1359     if (ret) {
1360         DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1361         goto out_dp_init;
1362     }
1363 
1364     ret = analogix_dp_commit(dp);
1365     if (ret) {
1366         DRM_ERROR("dp commit error, ret = %d\n", ret);
1367         goto out_dp_init;
1368     }
1369 
1370     if (dp->plat_data->power_on_end)
1371         dp->plat_data->power_on_end(dp->plat_data);
1372 
1373     enable_irq(dp->irq);
1374     return 0;
1375 
1376 out_dp_init:
1377     phy_power_off(dp->phy);
1378     if (dp->plat_data->power_off)
1379         dp->plat_data->power_off(dp->plat_data);
1380     clk_disable_unprepare(dp->clock);
1381 out_dp_clk_pre:
1382     pm_runtime_put_sync(dp->dev);
1383 
1384     return ret;
1385 }
1386 
1387 static void
1388 analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1389                  struct drm_bridge_state *old_bridge_state)
1390 {
1391     struct drm_atomic_state *old_state = old_bridge_state->base.state;
1392     struct analogix_dp_device *dp = bridge->driver_private;
1393     struct drm_crtc *crtc;
1394     struct drm_crtc_state *old_crtc_state;
1395     int timeout_loop = 0;
1396     int ret;
1397 
1398     crtc = analogix_dp_get_new_crtc(dp, old_state);
1399     if (!crtc)
1400         return;
1401 
1402     old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1403     /* Not a full enable, just disable PSR and continue */
1404     if (old_crtc_state && old_crtc_state->self_refresh_active) {
1405         ret = analogix_dp_disable_psr(dp);
1406         if (ret)
1407             DRM_ERROR("Failed to disable psr %d\n", ret);
1408         return;
1409     }
1410 
1411     if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1412         return;
1413 
1414     while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1415         if (analogix_dp_set_bridge(dp) == 0) {
1416             dp->dpms_mode = DRM_MODE_DPMS_ON;
1417             return;
1418         }
1419         dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1420             timeout_loop);
1421         timeout_loop++;
1422         usleep_range(10, 11);
1423     }
1424     dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1425 }
1426 
1427 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1428 {
1429     struct analogix_dp_device *dp = bridge->driver_private;
1430     int ret;
1431 
1432     if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1433         return;
1434 
1435     if (dp->plat_data->panel) {
1436         if (drm_panel_disable(dp->plat_data->panel)) {
1437             DRM_ERROR("failed to disable the panel\n");
1438             return;
1439         }
1440     }
1441 
1442     disable_irq(dp->irq);
1443 
1444     if (dp->plat_data->power_off)
1445         dp->plat_data->power_off(dp->plat_data);
1446 
1447     analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1448     phy_power_off(dp->phy);
1449 
1450     clk_disable_unprepare(dp->clock);
1451 
1452     pm_runtime_put_sync(dp->dev);
1453 
1454     ret = analogix_dp_prepare_panel(dp, false, true);
1455     if (ret)
1456         DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1457 
1458     dp->fast_train_enable = false;
1459     dp->psr_supported = false;
1460     dp->dpms_mode = DRM_MODE_DPMS_OFF;
1461 }
1462 
1463 static void
1464 analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1465                   struct drm_bridge_state *old_bridge_state)
1466 {
1467     struct drm_atomic_state *old_state = old_bridge_state->base.state;
1468     struct analogix_dp_device *dp = bridge->driver_private;
1469     struct drm_crtc *old_crtc, *new_crtc;
1470     struct drm_crtc_state *old_crtc_state = NULL;
1471     struct drm_crtc_state *new_crtc_state = NULL;
1472     int ret;
1473 
1474     new_crtc = analogix_dp_get_new_crtc(dp, old_state);
1475     if (!new_crtc)
1476         goto out;
1477 
1478     new_crtc_state = drm_atomic_get_new_crtc_state(old_state, new_crtc);
1479     if (!new_crtc_state)
1480         goto out;
1481 
1482     /* Don't do a full disable on PSR transitions */
1483     if (new_crtc_state->self_refresh_active)
1484         return;
1485 
1486 out:
1487     old_crtc = analogix_dp_get_old_crtc(dp, old_state);
1488     if (old_crtc) {
1489         old_crtc_state = drm_atomic_get_old_crtc_state(old_state,
1490                                    old_crtc);
1491 
1492         /* When moving from PSR to fully disabled, exit PSR first. */
1493         if (old_crtc_state && old_crtc_state->self_refresh_active) {
1494             ret = analogix_dp_disable_psr(dp);
1495             if (ret)
1496                 DRM_ERROR("Failed to disable psr (%d)\n", ret);
1497         }
1498     }
1499 
1500     analogix_dp_bridge_disable(bridge);
1501 }
1502 
1503 static void
1504 analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1505                 struct drm_bridge_state *old_bridge_state)
1506 {
1507     struct drm_atomic_state *old_state = old_bridge_state->base.state;
1508     struct analogix_dp_device *dp = bridge->driver_private;
1509     struct drm_crtc *crtc;
1510     struct drm_crtc_state *new_crtc_state;
1511     int ret;
1512 
1513     crtc = analogix_dp_get_new_crtc(dp, old_state);
1514     if (!crtc)
1515         return;
1516 
1517     new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1518     if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1519         return;
1520 
1521     ret = analogix_dp_enable_psr(dp);
1522     if (ret)
1523         DRM_ERROR("Failed to enable psr (%d)\n", ret);
1524 }
1525 
1526 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1527                 const struct drm_display_mode *orig_mode,
1528                 const struct drm_display_mode *mode)
1529 {
1530     struct analogix_dp_device *dp = bridge->driver_private;
1531     struct drm_display_info *display_info = &dp->connector.display_info;
1532     struct video_info *video = &dp->video_info;
1533     struct device_node *dp_node = dp->dev->of_node;
1534     int vic;
1535 
1536     /* Input video interlaces & hsync pol & vsync pol */
1537     video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1538     video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1539     video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1540 
1541     /* Input video dynamic_range & colorimetry */
1542     vic = drm_match_cea_mode(mode);
1543     if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1544         (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1545         video->dynamic_range = CEA;
1546         video->ycbcr_coeff = COLOR_YCBCR601;
1547     } else if (vic) {
1548         video->dynamic_range = CEA;
1549         video->ycbcr_coeff = COLOR_YCBCR709;
1550     } else {
1551         video->dynamic_range = VESA;
1552         video->ycbcr_coeff = COLOR_YCBCR709;
1553     }
1554 
1555     /* Input vide bpc and color_formats */
1556     switch (display_info->bpc) {
1557     case 12:
1558         video->color_depth = COLOR_12;
1559         break;
1560     case 10:
1561         video->color_depth = COLOR_10;
1562         break;
1563     case 8:
1564         video->color_depth = COLOR_8;
1565         break;
1566     case 6:
1567         video->color_depth = COLOR_6;
1568         break;
1569     default:
1570         video->color_depth = COLOR_8;
1571         break;
1572     }
1573     if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
1574         video->color_space = COLOR_YCBCR444;
1575     else if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
1576         video->color_space = COLOR_YCBCR422;
1577     else
1578         video->color_space = COLOR_RGB;
1579 
1580     /*
1581      * NOTE: those property parsing code is used for providing backward
1582      * compatibility for samsung platform.
1583      * Due to we used the "of_property_read_u32" interfaces, when this
1584      * property isn't present, the "video_info" can keep the original
1585      * values and wouldn't be modified.
1586      */
1587     of_property_read_u32(dp_node, "samsung,color-space",
1588                  &video->color_space);
1589     of_property_read_u32(dp_node, "samsung,dynamic-range",
1590                  &video->dynamic_range);
1591     of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1592                  &video->ycbcr_coeff);
1593     of_property_read_u32(dp_node, "samsung,color-depth",
1594                  &video->color_depth);
1595     if (of_property_read_bool(dp_node, "hsync-active-high"))
1596         video->h_sync_polarity = true;
1597     if (of_property_read_bool(dp_node, "vsync-active-high"))
1598         video->v_sync_polarity = true;
1599     if (of_property_read_bool(dp_node, "interlaced"))
1600         video->interlaced = true;
1601 }
1602 
1603 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1604     .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1605     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1606     .atomic_reset = drm_atomic_helper_bridge_reset,
1607     .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1608     .atomic_enable = analogix_dp_bridge_atomic_enable,
1609     .atomic_disable = analogix_dp_bridge_atomic_disable,
1610     .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1611     .mode_set = analogix_dp_bridge_mode_set,
1612     .attach = analogix_dp_bridge_attach,
1613 };
1614 
1615 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1616                      struct analogix_dp_device *dp)
1617 {
1618     struct drm_bridge *bridge;
1619 
1620     bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1621     if (!bridge) {
1622         DRM_ERROR("failed to allocate for drm bridge\n");
1623         return -ENOMEM;
1624     }
1625 
1626     dp->bridge = bridge;
1627 
1628     bridge->driver_private = dp;
1629     bridge->funcs = &analogix_dp_bridge_funcs;
1630 
1631     return drm_bridge_attach(dp->encoder, bridge, NULL, 0);
1632 }
1633 
1634 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1635 {
1636     struct device_node *dp_node = dp->dev->of_node;
1637     struct video_info *video_info = &dp->video_info;
1638 
1639     switch (dp->plat_data->dev_type) {
1640     case RK3288_DP:
1641     case RK3399_EDP:
1642         /*
1643          * Like Rk3288 DisplayPort TRM indicate that "Main link
1644          * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1645          */
1646         video_info->max_link_rate = 0x0A;
1647         video_info->max_lane_count = 0x04;
1648         break;
1649     case EXYNOS_DP:
1650         /*
1651          * NOTE: those property parseing code is used for
1652          * providing backward compatibility for samsung platform.
1653          */
1654         of_property_read_u32(dp_node, "samsung,link-rate",
1655                      &video_info->max_link_rate);
1656         of_property_read_u32(dp_node, "samsung,lane-count",
1657                      &video_info->max_lane_count);
1658         break;
1659     }
1660 
1661     return 0;
1662 }
1663 
1664 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1665                        struct drm_dp_aux_msg *msg)
1666 {
1667     struct analogix_dp_device *dp = to_dp(aux);
1668     int ret;
1669 
1670     pm_runtime_get_sync(dp->dev);
1671 
1672     ret = analogix_dp_detect_hpd(dp);
1673     if (ret)
1674         goto out;
1675 
1676     ret = analogix_dp_transfer(dp, msg);
1677 out:
1678     pm_runtime_mark_last_busy(dp->dev);
1679     pm_runtime_put_autosuspend(dp->dev);
1680 
1681     return ret;
1682 }
1683 
1684 struct analogix_dp_device *
1685 analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
1686 {
1687     struct platform_device *pdev = to_platform_device(dev);
1688     struct analogix_dp_device *dp;
1689     struct resource *res;
1690     unsigned int irq_flags;
1691     int ret;
1692 
1693     if (!plat_data) {
1694         dev_err(dev, "Invalided input plat_data\n");
1695         return ERR_PTR(-EINVAL);
1696     }
1697 
1698     dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1699     if (!dp)
1700         return ERR_PTR(-ENOMEM);
1701 
1702     dp->dev = &pdev->dev;
1703     dp->dpms_mode = DRM_MODE_DPMS_OFF;
1704 
1705     mutex_init(&dp->panel_lock);
1706     dp->panel_is_modeset = false;
1707 
1708     /*
1709      * platform dp driver need containor_of the plat_data to get
1710      * the driver private data, so we need to store the point of
1711      * plat_data, not the context of plat_data.
1712      */
1713     dp->plat_data = plat_data;
1714 
1715     ret = analogix_dp_dt_parse_pdata(dp);
1716     if (ret)
1717         return ERR_PTR(ret);
1718 
1719     dp->phy = devm_phy_get(dp->dev, "dp");
1720     if (IS_ERR(dp->phy)) {
1721         dev_err(dp->dev, "no DP phy configured\n");
1722         ret = PTR_ERR(dp->phy);
1723         if (ret) {
1724             /*
1725              * phy itself is not enabled, so we can move forward
1726              * assigning NULL to phy pointer.
1727              */
1728             if (ret == -ENOSYS || ret == -ENODEV)
1729                 dp->phy = NULL;
1730             else
1731                 return ERR_PTR(ret);
1732         }
1733     }
1734 
1735     dp->clock = devm_clk_get(&pdev->dev, "dp");
1736     if (IS_ERR(dp->clock)) {
1737         dev_err(&pdev->dev, "failed to get clock\n");
1738         return ERR_CAST(dp->clock);
1739     }
1740 
1741     clk_prepare_enable(dp->clock);
1742 
1743     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1744 
1745     dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1746     if (IS_ERR(dp->reg_base)) {
1747         ret = PTR_ERR(dp->reg_base);
1748         goto err_disable_clk;
1749     }
1750 
1751     dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1752 
1753     /* Try two different names */
1754     dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1755     if (!dp->hpd_gpiod)
1756         dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1757                             GPIOD_IN);
1758     if (IS_ERR(dp->hpd_gpiod)) {
1759         dev_err(dev, "error getting HDP GPIO: %ld\n",
1760             PTR_ERR(dp->hpd_gpiod));
1761         ret = PTR_ERR(dp->hpd_gpiod);
1762         goto err_disable_clk;
1763     }
1764 
1765     if (dp->hpd_gpiod) {
1766         /*
1767          * Set up the hotplug GPIO from the device tree as an interrupt.
1768          * Simply specifying a different interrupt in the device tree
1769          * doesn't work since we handle hotplug rather differently when
1770          * using a GPIO.  We also need the actual GPIO specifier so
1771          * that we can get the current state of the GPIO.
1772          */
1773         dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1774         irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1775     } else {
1776         dp->irq = platform_get_irq(pdev, 0);
1777         irq_flags = 0;
1778     }
1779 
1780     if (dp->irq == -ENXIO) {
1781         dev_err(&pdev->dev, "failed to get irq\n");
1782         ret = -ENODEV;
1783         goto err_disable_clk;
1784     }
1785 
1786     ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1787                     analogix_dp_hardirq,
1788                     analogix_dp_irq_thread,
1789                     irq_flags, "analogix-dp", dp);
1790     if (ret) {
1791         dev_err(&pdev->dev, "failed to request irq\n");
1792         goto err_disable_clk;
1793     }
1794     disable_irq(dp->irq);
1795 
1796     return dp;
1797 
1798 err_disable_clk:
1799     clk_disable_unprepare(dp->clock);
1800     return ERR_PTR(ret);
1801 }
1802 EXPORT_SYMBOL_GPL(analogix_dp_probe);
1803 
1804 int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
1805 {
1806     int ret;
1807 
1808     dp->drm_dev = drm_dev;
1809     dp->encoder = dp->plat_data->encoder;
1810 
1811     dp->aux.name = "DP-AUX";
1812     dp->aux.transfer = analogix_dpaux_transfer;
1813     dp->aux.dev = dp->dev;
1814     dp->aux.drm_dev = drm_dev;
1815 
1816     ret = drm_dp_aux_register(&dp->aux);
1817     if (ret)
1818         return ret;
1819 
1820     pm_runtime_use_autosuspend(dp->dev);
1821     pm_runtime_set_autosuspend_delay(dp->dev, 100);
1822     pm_runtime_enable(dp->dev);
1823 
1824     ret = analogix_dp_create_bridge(drm_dev, dp);
1825     if (ret) {
1826         DRM_ERROR("failed to create bridge (%d)\n", ret);
1827         goto err_disable_pm_runtime;
1828     }
1829 
1830     return 0;
1831 
1832 err_disable_pm_runtime:
1833     pm_runtime_dont_use_autosuspend(dp->dev);
1834     pm_runtime_disable(dp->dev);
1835     drm_dp_aux_unregister(&dp->aux);
1836 
1837     return ret;
1838 }
1839 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1840 
1841 void analogix_dp_unbind(struct analogix_dp_device *dp)
1842 {
1843     analogix_dp_bridge_disable(dp->bridge);
1844     dp->connector.funcs->destroy(&dp->connector);
1845 
1846     if (dp->plat_data->panel) {
1847         if (drm_panel_unprepare(dp->plat_data->panel))
1848             DRM_ERROR("failed to turnoff the panel\n");
1849     }
1850 
1851     drm_dp_aux_unregister(&dp->aux);
1852     pm_runtime_dont_use_autosuspend(dp->dev);
1853     pm_runtime_disable(dp->dev);
1854 }
1855 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1856 
1857 void analogix_dp_remove(struct analogix_dp_device *dp)
1858 {
1859     clk_disable_unprepare(dp->clock);
1860 }
1861 EXPORT_SYMBOL_GPL(analogix_dp_remove);
1862 
1863 #ifdef CONFIG_PM
1864 int analogix_dp_suspend(struct analogix_dp_device *dp)
1865 {
1866     clk_disable_unprepare(dp->clock);
1867     return 0;
1868 }
1869 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1870 
1871 int analogix_dp_resume(struct analogix_dp_device *dp)
1872 {
1873     int ret;
1874 
1875     ret = clk_prepare_enable(dp->clock);
1876     if (ret < 0) {
1877         DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1878         return ret;
1879     }
1880 
1881     return 0;
1882 }
1883 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1884 #endif
1885 
1886 int analogix_dp_start_crc(struct drm_connector *connector)
1887 {
1888     struct analogix_dp_device *dp = to_dp(connector);
1889 
1890     if (!connector->state->crtc) {
1891         DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1892               connector->name);
1893         return -EINVAL;
1894     }
1895 
1896     return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1897 }
1898 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1899 
1900 int analogix_dp_stop_crc(struct drm_connector *connector)
1901 {
1902     struct analogix_dp_device *dp = to_dp(connector);
1903 
1904     return drm_dp_stop_crc(&dp->aux);
1905 }
1906 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1907 
1908 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1909 MODULE_DESCRIPTION("Analogix DP Core Driver");
1910 MODULE_LICENSE("GPL v2");
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