bridge/analogix/analogix-i2c-dptx.c

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright(c) 2016, Analogix Semiconductor.
0004  *
0005  * Based on anx7808 driver obtained from chromeos with copyright:
0006  * Copyright(c) 2013, Google Inc.
0007  */
0008 #include <linux/regmap.h>
0009
0010 #include <drm/display/drm_dp_helper.h>
0011 #include <drm/drm.h>
0012 #include <drm/drm_print.h>
0013
0014 #include "analogix-i2c-dptx.h"
0015
0016 #define AUX_WAIT_TIMEOUT_MS 15
0017 #define AUX_CH_BUFFER_SIZE  16
0018
0019 static int anx_i2c_dp_clear_bits(struct regmap *map, u8 reg, u8 mask)
0020 {
0021     return regmap_update_bits(map, reg, mask, 0);
0022 }
0023
0024 static bool anx_dp_aux_op_finished(struct regmap *map_dptx)
0025 {
0026     unsigned int value;
0027     int err;
0028
0029     err = regmap_read(map_dptx, SP_DP_AUX_CH_CTRL2_REG, &value);
0030     if (err < 0)
0031         return false;
0032
0033     return (value & SP_AUX_EN) == 0;
0034 }
0035
0036 static int anx_dp_aux_wait(struct regmap *map_dptx)
0037 {
0038     unsigned long timeout;
0039     unsigned int status;
0040     int err;
0041
0042     timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
0043
0044     while (!anx_dp_aux_op_finished(map_dptx)) {
0045         if (time_after(jiffies, timeout)) {
0046             if (!anx_dp_aux_op_finished(map_dptx)) {
0047                 DRM_ERROR("Timed out waiting AUX to finish\n");
0048                 return -ETIMEDOUT;
0049             }
0050
0051             break;
0052         }
0053
0054         usleep_range(1000, 2000);
0055     }
0056
0057     /* Read the AUX channel access status */
0058     err = regmap_read(map_dptx, SP_AUX_CH_STATUS_REG, &status);
0059     if (err < 0) {
0060         DRM_ERROR("Failed to read from AUX channel: %d\n", err);
0061         return err;
0062     }
0063
0064     if (status & SP_AUX_STATUS) {
0065         DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
0066               status);
0067         return -ETIMEDOUT;
0068     }
0069
0070     return 0;
0071 }
0072
0073 static int anx_dp_aux_address(struct regmap *map_dptx, unsigned int addr)
0074 {
0075     int err;
0076
0077     err = regmap_write(map_dptx, SP_AUX_ADDR_7_0_REG, addr & 0xff);
0078     if (err)
0079         return err;
0080
0081     err = regmap_write(map_dptx, SP_AUX_ADDR_15_8_REG,
0082                (addr & 0xff00) >> 8);
0083     if (err)
0084         return err;
0085
0086     /*
0087      * DP AUX CH Address Register #2, only update bits[3:0]
0088      * [7:4] RESERVED
0089      * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
0090      */
0091     err = regmap_update_bits(map_dptx, SP_AUX_ADDR_19_16_REG,
0092                  SP_AUX_ADDR_19_16_MASK,
0093                  (addr & 0xf0000) >> 16);
0094
0095     if (err)
0096         return err;
0097
0098     return 0;
0099 }
0100
0101 ssize_t anx_dp_aux_transfer(struct regmap *map_dptx,
0102                 struct drm_dp_aux_msg *msg)
0103 {
0104     u8 ctrl1 = msg->request;
0105     u8 ctrl2 = SP_AUX_EN;
0106     u8 *buffer = msg->buffer;
0107     int err;
0108
0109     /* The DP AUX transmit and receive buffer has 16 bytes. */
0110     if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
0111         return -E2BIG;
0112
0113     /* Zero-sized messages specify address-only transactions. */
0114     if (msg->size < 1)
0115         ctrl2 |= SP_ADDR_ONLY;
0116     else    /* For non-zero-sized set the length field. */
0117         ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
0118
0119     if ((msg->size > 0) && ((msg->request & DP_AUX_I2C_READ) == 0)) {
0120         /* When WRITE | MOT write values to data buffer */
0121         err = regmap_bulk_write(map_dptx,
0122                     SP_DP_BUF_DATA0_REG, buffer,
0123                     msg->size);
0124         if (err)
0125             return err;
0126     }
0127
0128     /* Write address and request */
0129     err = anx_dp_aux_address(map_dptx, msg->address);
0130     if (err)
0131         return err;
0132
0133     err = regmap_write(map_dptx, SP_DP_AUX_CH_CTRL1_REG, ctrl1);
0134     if (err)
0135         return err;
0136
0137     /* Start transaction */
0138     err = regmap_update_bits(map_dptx, SP_DP_AUX_CH_CTRL2_REG,
0139                  SP_ADDR_ONLY | SP_AUX_EN, ctrl2);
0140     if (err)
0141         return err;
0142
0143     err = anx_dp_aux_wait(map_dptx);
0144     if (err)
0145         return err;
0146
0147     msg->reply = DP_AUX_I2C_REPLY_ACK;
0148
0149     if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
0150         /* Read values from data buffer */
0151         err = regmap_bulk_read(map_dptx,
0152                        SP_DP_BUF_DATA0_REG, buffer,
0153                        msg->size);
0154         if (err)
0155             return err;
0156     }
0157
0158     err = anx_i2c_dp_clear_bits(map_dptx, SP_DP_AUX_CH_CTRL2_REG,
0159                     SP_ADDR_ONLY);
0160     if (err)
0161         return err;
0162
0163     return msg->size;
0164 }
0165 EXPORT_SYMBOL_GPL(anx_dp_aux_transfer);