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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright(c) 2016, Analogix Semiconductor.
0004  *
0005  * Based on anx7808 driver obtained from chromeos with copyright:
0006  * Copyright(c) 2013, Google Inc.
0007  */
0008 #include <linux/delay.h>
0009 #include <linux/err.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/i2c.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/regmap.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/types.h>
0020 
0021 #include <drm/display/drm_dp_helper.h>
0022 #include <drm/drm_atomic_helper.h>
0023 #include <drm/drm_bridge.h>
0024 #include <drm/drm_crtc.h>
0025 #include <drm/drm_edid.h>
0026 #include <drm/drm_print.h>
0027 #include <drm/drm_probe_helper.h>
0028 
0029 #include "analogix-anx78xx.h"
0030 
0031 #define I2C_NUM_ADDRESSES   5
0032 #define I2C_IDX_TX_P0       0
0033 #define I2C_IDX_TX_P1       1
0034 #define I2C_IDX_TX_P2       2
0035 #define I2C_IDX_RX_P0       3
0036 #define I2C_IDX_RX_P1       4
0037 
0038 #define XTAL_CLK        270 /* 27M */
0039 
0040 static const u8 anx7808_i2c_addresses[] = {
0041     [I2C_IDX_TX_P0] = 0x78,
0042     [I2C_IDX_TX_P1] = 0x7a,
0043     [I2C_IDX_TX_P2] = 0x72,
0044     [I2C_IDX_RX_P0] = 0x7e,
0045     [I2C_IDX_RX_P1] = 0x80,
0046 };
0047 
0048 static const u8 anx781x_i2c_addresses[] = {
0049     [I2C_IDX_TX_P0] = 0x70,
0050     [I2C_IDX_TX_P1] = 0x7a,
0051     [I2C_IDX_TX_P2] = 0x72,
0052     [I2C_IDX_RX_P0] = 0x7e,
0053     [I2C_IDX_RX_P1] = 0x80,
0054 };
0055 
0056 struct anx78xx_platform_data {
0057     struct regulator *dvdd10;
0058     struct gpio_desc *gpiod_hpd;
0059     struct gpio_desc *gpiod_pd;
0060     struct gpio_desc *gpiod_reset;
0061 
0062     int hpd_irq;
0063     int intp_irq;
0064 };
0065 
0066 struct anx78xx {
0067     struct drm_dp_aux aux;
0068     struct drm_bridge bridge;
0069     struct i2c_client *client;
0070     struct edid *edid;
0071     struct drm_connector connector;
0072     struct anx78xx_platform_data pdata;
0073     struct mutex lock;
0074 
0075     /*
0076      * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
0077      * RX_P0 and RX_P1.
0078      */
0079     struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
0080     struct regmap *map[I2C_NUM_ADDRESSES];
0081 
0082     u16 chipid;
0083     u8 dpcd[DP_RECEIVER_CAP_SIZE];
0084 
0085     bool powered;
0086 };
0087 
0088 static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
0089 {
0090     return container_of(c, struct anx78xx, connector);
0091 }
0092 
0093 static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
0094 {
0095     return container_of(bridge, struct anx78xx, bridge);
0096 }
0097 
0098 static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
0099 {
0100     return regmap_update_bits(map, reg, mask, mask);
0101 }
0102 
0103 static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
0104 {
0105     return regmap_update_bits(map, reg, mask, 0);
0106 }
0107 
0108 static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
0109                     struct drm_dp_aux_msg *msg)
0110 {
0111     struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
0112     return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg);
0113 }
0114 
0115 static int anx78xx_set_hpd(struct anx78xx *anx78xx)
0116 {
0117     int err;
0118 
0119     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
0120                  SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
0121     if (err)
0122         return err;
0123 
0124     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
0125                    SP_HPD_OUT);
0126     if (err)
0127         return err;
0128 
0129     return 0;
0130 }
0131 
0132 static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
0133 {
0134     int err;
0135 
0136     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
0137                  SP_HPD_OUT);
0138     if (err)
0139         return err;
0140 
0141     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
0142                    SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
0143     if (err)
0144         return err;
0145 
0146     return 0;
0147 }
0148 
0149 static const struct reg_sequence tmds_phy_initialization[] = {
0150     { SP_TMDS_CTRL_BASE +  1, 0x90 },
0151     { SP_TMDS_CTRL_BASE +  2, 0xa9 },
0152     { SP_TMDS_CTRL_BASE +  6, 0x92 },
0153     { SP_TMDS_CTRL_BASE +  7, 0x80 },
0154     { SP_TMDS_CTRL_BASE + 20, 0xf2 },
0155     { SP_TMDS_CTRL_BASE + 22, 0xc4 },
0156     { SP_TMDS_CTRL_BASE + 23, 0x18 },
0157 };
0158 
0159 static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
0160 {
0161     int err;
0162 
0163     err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
0164                SP_AUD_MUTE | SP_VID_MUTE);
0165     if (err)
0166         return err;
0167 
0168     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
0169                    SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
0170                    SP_DIGITAL_CKDT_EN);
0171     if (err)
0172         return err;
0173 
0174     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
0175                    SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
0176                    SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
0177     if (err)
0178         return err;
0179 
0180     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
0181                  SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
0182                  SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
0183     if (err)
0184         return err;
0185 
0186     /* Sync detect change, GP set mute */
0187     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
0188                    SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
0189                    BIT(6));
0190     if (err)
0191         return err;
0192 
0193     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
0194                    SP_AUD_EXCEPTION_ENABLE_BASE + 3,
0195                    SP_AEC_EN21);
0196     if (err)
0197         return err;
0198 
0199     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
0200                    SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
0201     if (err)
0202         return err;
0203 
0204     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
0205                  SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
0206     if (err)
0207         return err;
0208 
0209     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
0210                    SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
0211     if (err)
0212         return err;
0213 
0214     /* Enable DDC stretch */
0215     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0216                SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
0217     if (err)
0218         return err;
0219 
0220     /* TMDS phy initialization */
0221     err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
0222                      tmds_phy_initialization,
0223                      ARRAY_SIZE(tmds_phy_initialization));
0224     if (err)
0225         return err;
0226 
0227     err = anx78xx_clear_hpd(anx78xx);
0228     if (err)
0229         return err;
0230 
0231     return 0;
0232 }
0233 
0234 static const u8 dp_tx_output_precise_tune_bits[20] = {
0235     0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
0236     0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
0237     0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
0238 };
0239 
0240 static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
0241 {
0242     int err;
0243 
0244     /*
0245      * REVISIT : It is writing to a RESERVED bits in Analog Control 0
0246      * register.
0247      */
0248     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
0249                0x02);
0250     if (err)
0251         return err;
0252 
0253     /*
0254      * Write DP TX output emphasis precise tune bits.
0255      */
0256     err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
0257                 SP_DP_TX_LT_CTRL0_REG,
0258                 dp_tx_output_precise_tune_bits,
0259                 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
0260 
0261     if (err)
0262         return err;
0263 
0264     return 0;
0265 }
0266 
0267 static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
0268 {
0269     unsigned int value;
0270     int err;
0271 
0272     err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
0273                  SP_ANALOG_DEBUG2_REG,
0274                  SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
0275                  SP_XTAL_FRQ_27M);
0276     if (err)
0277         return err;
0278 
0279     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
0280                XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
0281     if (err)
0282         return err;
0283 
0284     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
0285                ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
0286     if (err)
0287         return err;
0288 
0289     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0290                SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
0291     if (err)
0292         return err;
0293 
0294     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0295                SP_I2C_GEN_10US_TIMER1_REG,
0296                (XTAL_CLK & 0xff00) >> 8);
0297     if (err)
0298         return err;
0299 
0300     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
0301                XTAL_CLK / 10 - 1);
0302     if (err)
0303         return err;
0304 
0305     err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
0306               SP_HDMI_US_TIMER_CTRL_REG,
0307               &value);
0308     if (err)
0309         return err;
0310 
0311     err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
0312                SP_HDMI_US_TIMER_CTRL_REG,
0313                (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
0314                ((((XTAL_CLK / 10) >> 1) - 2) << 3));
0315     if (err)
0316         return err;
0317 
0318     return 0;
0319 }
0320 
0321 static const struct reg_sequence otp_key_protect[] = {
0322     { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
0323     { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
0324     { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
0325 };
0326 
0327 static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
0328 {
0329     int err;
0330 
0331     /* Set terminal resistor to 50 ohm */
0332     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
0333                0x30);
0334     if (err)
0335         return err;
0336 
0337     /* Enable aux double diff output */
0338     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0339                    SP_DP_AUX_CH_CTRL2_REG, 0x08);
0340     if (err)
0341         return err;
0342 
0343     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
0344                  SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
0345                  SP_AUTO_START);
0346     if (err)
0347         return err;
0348 
0349     err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
0350                      otp_key_protect,
0351                      ARRAY_SIZE(otp_key_protect));
0352     if (err)
0353         return err;
0354 
0355     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0356                    SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
0357     if (err)
0358         return err;
0359 
0360     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
0361                SP_VID_VRES_TH);
0362     if (err)
0363         return err;
0364 
0365     /*
0366      * DP HDCP auto authentication wait timer (when downstream starts to
0367      * auth, DP side will wait for this period then do auth automatically)
0368      */
0369     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
0370                0x00);
0371     if (err)
0372         return err;
0373 
0374     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0375                    SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
0376     if (err)
0377         return err;
0378 
0379     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0380                    SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
0381     if (err)
0382         return err;
0383 
0384     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
0385                    SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
0386     if (err)
0387         return err;
0388 
0389     err = anx78xx_xtal_clk_sel(anx78xx);
0390     if (err)
0391         return err;
0392 
0393     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
0394                SP_DEFER_CTRL_EN | 0x0c);
0395     if (err)
0396         return err;
0397 
0398     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0399                    SP_DP_POLLING_CTRL_REG,
0400                    SP_AUTO_POLLING_DISABLE);
0401     if (err)
0402         return err;
0403 
0404     /*
0405      * Short the link integrity check timer to speed up bstatus
0406      * polling for HDCP CTS item 1A-07
0407      */
0408     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0409                SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
0410     if (err)
0411         return err;
0412 
0413     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0414                    SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
0415     if (err)
0416         return err;
0417 
0418     /* Power down the main link by default */
0419     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0420                    SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
0421     if (err)
0422         return err;
0423 
0424     err = anx78xx_link_phy_initialization(anx78xx);
0425     if (err)
0426         return err;
0427 
0428     /* Gen m_clk with downspreading */
0429     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0430                    SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
0431     if (err)
0432         return err;
0433 
0434     return 0;
0435 }
0436 
0437 static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
0438 {
0439     int err;
0440 
0441     /*
0442      * BIT0: INT pin assertion polarity: 1 = assert high
0443      * BIT1: INT pin output type: 0 = push/pull
0444      */
0445     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
0446     if (err)
0447         return err;
0448 
0449     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
0450                SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
0451     if (err)
0452         return err;
0453 
0454     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
0455                SP_TRAINING_FINISH);
0456     if (err)
0457         return err;
0458 
0459     err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
0460                SP_CKDT_CHG | SP_SCDT_CHG);
0461     if (err)
0462         return err;
0463 
0464     return 0;
0465 }
0466 
0467 static void anx78xx_poweron(struct anx78xx *anx78xx)
0468 {
0469     struct anx78xx_platform_data *pdata = &anx78xx->pdata;
0470     int err;
0471 
0472     if (WARN_ON(anx78xx->powered))
0473         return;
0474 
0475     if (pdata->dvdd10) {
0476         err = regulator_enable(pdata->dvdd10);
0477         if (err) {
0478             DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
0479                   err);
0480             return;
0481         }
0482 
0483         usleep_range(1000, 2000);
0484     }
0485 
0486     gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
0487     usleep_range(1000, 2000);
0488 
0489     gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
0490     usleep_range(1000, 2000);
0491 
0492     gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
0493 
0494     /* Power on registers module */
0495     anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
0496              SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
0497     anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
0498                SP_REGISTER_PD | SP_TOTAL_PD);
0499 
0500     anx78xx->powered = true;
0501 }
0502 
0503 static void anx78xx_poweroff(struct anx78xx *anx78xx)
0504 {
0505     struct anx78xx_platform_data *pdata = &anx78xx->pdata;
0506     int err;
0507 
0508     if (WARN_ON(!anx78xx->powered))
0509         return;
0510 
0511     gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
0512     usleep_range(1000, 2000);
0513 
0514     gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
0515     usleep_range(1000, 2000);
0516 
0517     if (pdata->dvdd10) {
0518         err = regulator_disable(pdata->dvdd10);
0519         if (err) {
0520             DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
0521                   err);
0522             return;
0523         }
0524 
0525         usleep_range(1000, 2000);
0526     }
0527 
0528     anx78xx->powered = false;
0529 }
0530 
0531 static int anx78xx_start(struct anx78xx *anx78xx)
0532 {
0533     int err;
0534 
0535     /* Power on all modules */
0536     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
0537                  SP_POWERDOWN_CTRL_REG,
0538                  SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
0539                  SP_LINK_PD);
0540 
0541     err = anx78xx_enable_interrupts(anx78xx);
0542     if (err) {
0543         DRM_ERROR("Failed to enable interrupts: %d\n", err);
0544         goto err_poweroff;
0545     }
0546 
0547     err = anx78xx_rx_initialization(anx78xx);
0548     if (err) {
0549         DRM_ERROR("Failed receiver initialization: %d\n", err);
0550         goto err_poweroff;
0551     }
0552 
0553     err = anx78xx_tx_initialization(anx78xx);
0554     if (err) {
0555         DRM_ERROR("Failed transmitter initialization: %d\n", err);
0556         goto err_poweroff;
0557     }
0558 
0559     /*
0560      * This delay seems to help keep the hardware in a good state. Without
0561      * it, there are times where it fails silently.
0562      */
0563     usleep_range(10000, 15000);
0564 
0565     return 0;
0566 
0567 err_poweroff:
0568     DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
0569     anx78xx_poweroff(anx78xx);
0570 
0571     return err;
0572 }
0573 
0574 static int anx78xx_init_pdata(struct anx78xx *anx78xx)
0575 {
0576     struct anx78xx_platform_data *pdata = &anx78xx->pdata;
0577     struct device *dev = &anx78xx->client->dev;
0578 
0579     /* 1.0V digital core power regulator  */
0580     pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
0581     if (IS_ERR(pdata->dvdd10)) {
0582         if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)
0583             DRM_ERROR("DVDD10 regulator not found\n");
0584 
0585         return PTR_ERR(pdata->dvdd10);
0586     }
0587 
0588     /* GPIO for HPD */
0589     pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
0590     if (IS_ERR(pdata->gpiod_hpd))
0591         return PTR_ERR(pdata->gpiod_hpd);
0592 
0593     /* GPIO for chip power down */
0594     pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
0595     if (IS_ERR(pdata->gpiod_pd))
0596         return PTR_ERR(pdata->gpiod_pd);
0597 
0598     /* GPIO for chip reset */
0599     pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
0600 
0601     return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
0602 }
0603 
0604 static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
0605 {
0606     u8 dp_bw, dpcd[2];
0607     int err;
0608 
0609     err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
0610                0x0);
0611     if (err)
0612         return err;
0613 
0614     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
0615                  SP_POWERDOWN_CTRL_REG,
0616                  SP_TOTAL_PD);
0617     if (err)
0618         return err;
0619 
0620     err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
0621     if (err < 0)
0622         return err;
0623 
0624     switch (dp_bw) {
0625     case DP_LINK_BW_1_62:
0626     case DP_LINK_BW_2_7:
0627     case DP_LINK_BW_5_4:
0628         break;
0629 
0630     default:
0631         DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
0632         return -EINVAL;
0633     }
0634 
0635     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
0636                    SP_VIDEO_MUTE);
0637     if (err)
0638         return err;
0639 
0640     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
0641                  SP_VID_CTRL1_REG, SP_VIDEO_EN);
0642     if (err)
0643         return err;
0644 
0645     /* Get DPCD info */
0646     err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
0647                    &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
0648     if (err < 0) {
0649         DRM_ERROR("Failed to read DPCD: %d\n", err);
0650         return err;
0651     }
0652 
0653     /* Clear channel x SERDES power down */
0654     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
0655                  SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
0656     if (err)
0657         return err;
0658 
0659     /*
0660      * Power up the sink (DP_SET_POWER register is only available on DPCD
0661      * v1.1 and later).
0662      */
0663     if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) {
0664         err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]);
0665         if (err < 0) {
0666             DRM_ERROR("Failed to read DP_SET_POWER register: %d\n",
0667                   err);
0668             return err;
0669         }
0670 
0671         dpcd[0] &= ~DP_SET_POWER_MASK;
0672         dpcd[0] |= DP_SET_POWER_D0;
0673 
0674         err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]);
0675         if (err < 0) {
0676             DRM_ERROR("Failed to power up DisplayPort link: %d\n",
0677                   err);
0678             return err;
0679         }
0680 
0681         /*
0682          * According to the DP 1.1 specification, a "Sink Device must
0683          * exit the power saving state within 1 ms" (Section 2.5.3.1,
0684          * Table 5-52, "Sink Control Field" (register 0x600).
0685          */
0686         usleep_range(1000, 2000);
0687     }
0688 
0689     /* Possibly enable downspread on the sink */
0690     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0691                SP_DP_DOWNSPREAD_CTRL1_REG, 0);
0692     if (err)
0693         return err;
0694 
0695     if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
0696         DRM_DEBUG("Enable downspread on the sink\n");
0697         /* 4000PPM */
0698         err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0699                    SP_DP_DOWNSPREAD_CTRL1_REG, 8);
0700         if (err)
0701             return err;
0702 
0703         err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
0704                      DP_SPREAD_AMP_0_5);
0705         if (err < 0)
0706             return err;
0707     } else {
0708         err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
0709         if (err < 0)
0710             return err;
0711     }
0712 
0713     /* Set the lane count and the link rate on the sink */
0714     if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
0715         err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0716                        SP_DP_SYSTEM_CTRL_BASE + 4,
0717                        SP_ENHANCED_MODE);
0718     else
0719         err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
0720                      SP_DP_SYSTEM_CTRL_BASE + 4,
0721                      SP_ENHANCED_MODE);
0722     if (err)
0723         return err;
0724 
0725     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
0726                SP_DP_MAIN_LINK_BW_SET_REG,
0727                anx78xx->dpcd[DP_MAX_LINK_RATE]);
0728     if (err)
0729         return err;
0730 
0731     dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd);
0732 
0733     if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
0734         dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
0735 
0736     err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,
0737                 sizeof(dpcd));
0738     if (err < 0) {
0739         DRM_ERROR("Failed to configure link: %d\n", err);
0740         return err;
0741     }
0742 
0743     /* Start training on the source */
0744     err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
0745                SP_LT_EN);
0746     if (err)
0747         return err;
0748 
0749     return 0;
0750 }
0751 
0752 static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
0753 {
0754     int err;
0755 
0756     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
0757                  SP_VIDEO_MUTE);
0758     if (err)
0759         return err;
0760 
0761     /* Enable DP output */
0762     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
0763                    SP_VIDEO_EN);
0764     if (err)
0765         return err;
0766 
0767     return 0;
0768 }
0769 
0770 static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
0771                     struct hdmi_avi_infoframe *frame)
0772 {
0773     u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
0774     int err;
0775 
0776     err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
0777     if (err < 0) {
0778         DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
0779         return err;
0780     }
0781 
0782     err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
0783                  SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
0784     if (err)
0785         return err;
0786 
0787     err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
0788                 SP_INFOFRAME_AVI_DB1_REG, buffer,
0789                 frame->length);
0790     if (err)
0791         return err;
0792 
0793     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0794                    SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
0795     if (err)
0796         return err;
0797 
0798     err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
0799                    SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
0800     if (err)
0801         return err;
0802 
0803     return 0;
0804 }
0805 
0806 static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
0807 {
0808     u8 value;
0809     int err;
0810 
0811     err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
0812     if (err < 0) {
0813         DRM_ERROR("Get sink count failed %d\n", err);
0814         return err;
0815     }
0816 
0817     if (!DP_GET_SINK_COUNT(value)) {
0818         DRM_ERROR("Downstream disconnected\n");
0819         return -EIO;
0820     }
0821 
0822     return 0;
0823 }
0824 
0825 static int anx78xx_get_modes(struct drm_connector *connector)
0826 {
0827     struct anx78xx *anx78xx = connector_to_anx78xx(connector);
0828     int err, num_modes = 0;
0829 
0830     if (WARN_ON(!anx78xx->powered))
0831         return 0;
0832 
0833     if (anx78xx->edid)
0834         return drm_add_edid_modes(connector, anx78xx->edid);
0835 
0836     mutex_lock(&anx78xx->lock);
0837 
0838     err = anx78xx_get_downstream_info(anx78xx);
0839     if (err) {
0840         DRM_ERROR("Failed to get downstream info: %d\n", err);
0841         goto unlock;
0842     }
0843 
0844     anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
0845     if (!anx78xx->edid) {
0846         DRM_ERROR("Failed to read EDID\n");
0847         goto unlock;
0848     }
0849 
0850     err = drm_connector_update_edid_property(connector,
0851                          anx78xx->edid);
0852     if (err) {
0853         DRM_ERROR("Failed to update EDID property: %d\n", err);
0854         goto unlock;
0855     }
0856 
0857     num_modes = drm_add_edid_modes(connector, anx78xx->edid);
0858 
0859 unlock:
0860     mutex_unlock(&anx78xx->lock);
0861 
0862     return num_modes;
0863 }
0864 
0865 static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
0866     .get_modes = anx78xx_get_modes,
0867 };
0868 
0869 static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
0870                         bool force)
0871 {
0872     struct anx78xx *anx78xx = connector_to_anx78xx(connector);
0873 
0874     if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
0875         return connector_status_disconnected;
0876 
0877     return connector_status_connected;
0878 }
0879 
0880 static const struct drm_connector_funcs anx78xx_connector_funcs = {
0881     .fill_modes = drm_helper_probe_single_connector_modes,
0882     .detect = anx78xx_detect,
0883     .destroy = drm_connector_cleanup,
0884     .reset = drm_atomic_helper_connector_reset,
0885     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0886     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0887 };
0888 
0889 static int anx78xx_bridge_attach(struct drm_bridge *bridge,
0890                  enum drm_bridge_attach_flags flags)
0891 {
0892     struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
0893     int err;
0894 
0895     if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
0896         DRM_ERROR("Fix bridge driver to make connector optional!");
0897         return -EINVAL;
0898     }
0899 
0900     if (!bridge->encoder) {
0901         DRM_ERROR("Parent encoder object not found");
0902         return -ENODEV;
0903     }
0904 
0905     /* Register aux channel */
0906     anx78xx->aux.name = "DP-AUX";
0907     anx78xx->aux.dev = &anx78xx->client->dev;
0908     anx78xx->aux.drm_dev = bridge->dev;
0909     anx78xx->aux.transfer = anx78xx_aux_transfer;
0910 
0911     err = drm_dp_aux_register(&anx78xx->aux);
0912     if (err < 0) {
0913         DRM_ERROR("Failed to register aux channel: %d\n", err);
0914         return err;
0915     }
0916 
0917     err = drm_connector_init(bridge->dev, &anx78xx->connector,
0918                  &anx78xx_connector_funcs,
0919                  DRM_MODE_CONNECTOR_DisplayPort);
0920     if (err) {
0921         DRM_ERROR("Failed to initialize connector: %d\n", err);
0922         goto aux_unregister;
0923     }
0924 
0925     drm_connector_helper_add(&anx78xx->connector,
0926                  &anx78xx_connector_helper_funcs);
0927 
0928     anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
0929 
0930     err = drm_connector_attach_encoder(&anx78xx->connector,
0931                        bridge->encoder);
0932     if (err) {
0933         DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
0934         goto connector_cleanup;
0935     }
0936 
0937     err = drm_connector_register(&anx78xx->connector);
0938     if (err) {
0939         DRM_ERROR("Failed to register connector: %d\n", err);
0940         goto connector_cleanup;
0941     }
0942 
0943     return 0;
0944 connector_cleanup:
0945     drm_connector_cleanup(&anx78xx->connector);
0946 aux_unregister:
0947     drm_dp_aux_unregister(&anx78xx->aux);
0948     return err;
0949 }
0950 
0951 static void anx78xx_bridge_detach(struct drm_bridge *bridge)
0952 {
0953     drm_dp_aux_unregister(&bridge_to_anx78xx(bridge)->aux);
0954 }
0955 
0956 static enum drm_mode_status
0957 anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
0958               const struct drm_display_info *info,
0959               const struct drm_display_mode *mode)
0960 {
0961     if (mode->flags & DRM_MODE_FLAG_INTERLACE)
0962         return MODE_NO_INTERLACE;
0963 
0964     /* Max 1200p at 5.4 Ghz, one lane */
0965     if (mode->clock > 154000)
0966         return MODE_CLOCK_HIGH;
0967 
0968     return MODE_OK;
0969 }
0970 
0971 static void anx78xx_bridge_disable(struct drm_bridge *bridge)
0972 {
0973     struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
0974 
0975     /* Power off all modules except configuration registers access */
0976     anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
0977              SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
0978 }
0979 
0980 static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
0981                 const struct drm_display_mode *mode,
0982                 const struct drm_display_mode *adjusted_mode)
0983 {
0984     struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
0985     struct hdmi_avi_infoframe frame;
0986     int err;
0987 
0988     if (WARN_ON(!anx78xx->powered))
0989         return;
0990 
0991     mutex_lock(&anx78xx->lock);
0992 
0993     err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
0994                                &anx78xx->connector,
0995                                adjusted_mode);
0996     if (err) {
0997         DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
0998         goto unlock;
0999     }
1000 
1001     err = anx78xx_send_video_infoframe(anx78xx, &frame);
1002     if (err)
1003         DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1004 
1005 unlock:
1006     mutex_unlock(&anx78xx->lock);
1007 }
1008 
1009 static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1010 {
1011     struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1012     int err;
1013 
1014     err = anx78xx_start(anx78xx);
1015     if (err) {
1016         DRM_ERROR("Failed to initialize: %d\n", err);
1017         return;
1018     }
1019 
1020     err = anx78xx_set_hpd(anx78xx);
1021     if (err)
1022         DRM_ERROR("Failed to set HPD: %d\n", err);
1023 }
1024 
1025 static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1026     .attach = anx78xx_bridge_attach,
1027     .detach = anx78xx_bridge_detach,
1028     .mode_valid = anx78xx_bridge_mode_valid,
1029     .disable = anx78xx_bridge_disable,
1030     .mode_set = anx78xx_bridge_mode_set,
1031     .enable = anx78xx_bridge_enable,
1032 };
1033 
1034 static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1035 {
1036     struct anx78xx *anx78xx = data;
1037     int err;
1038 
1039     if (anx78xx->powered)
1040         return IRQ_HANDLED;
1041 
1042     mutex_lock(&anx78xx->lock);
1043 
1044     /* Cable is pulled, power on the chip */
1045     anx78xx_poweron(anx78xx);
1046 
1047     err = anx78xx_enable_interrupts(anx78xx);
1048     if (err)
1049         DRM_ERROR("Failed to enable interrupts: %d\n", err);
1050 
1051     mutex_unlock(&anx78xx->lock);
1052 
1053     return IRQ_HANDLED;
1054 }
1055 
1056 static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1057 {
1058     int err;
1059 
1060     DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1061 
1062     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1063                irq);
1064     if (err)
1065         return err;
1066 
1067     if (irq & SP_TRAINING_FINISH) {
1068         DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1069         err = anx78xx_config_dp_output(anx78xx);
1070     }
1071 
1072     return err;
1073 }
1074 
1075 static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1076 {
1077     bool event = false;
1078     int err;
1079 
1080     DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1081 
1082     err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1083                SP_COMMON_INT_STATUS4_REG, irq);
1084     if (err) {
1085         DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1086         return event;
1087     }
1088 
1089     if (irq & SP_HPD_LOST) {
1090         DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1091         event = true;
1092         anx78xx_poweroff(anx78xx);
1093         /* Free cached EDID */
1094         kfree(anx78xx->edid);
1095         anx78xx->edid = NULL;
1096     } else if (irq & SP_HPD_PLUG) {
1097         DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1098         event = true;
1099     }
1100 
1101     return event;
1102 }
1103 
1104 static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1105 {
1106     unsigned int value;
1107     int err;
1108 
1109     DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1110 
1111     err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1112                irq);
1113     if (err) {
1114         DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1115         return;
1116     }
1117 
1118     if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1119         DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1120 
1121         err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1122                   SP_SYSTEM_STATUS_REG, &value);
1123         if (err) {
1124             DRM_ERROR("Read system status reg failed: %d\n", err);
1125             return;
1126         }
1127 
1128         if (!(value & SP_TMDS_CLOCK_DET)) {
1129             DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1130             return;
1131         }
1132 
1133         if (!(value & SP_TMDS_DE_DET)) {
1134             DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1135             return;
1136         }
1137 
1138         err = anx78xx_dp_link_training(anx78xx);
1139         if (err)
1140             DRM_ERROR("Failed to start link training: %d\n", err);
1141     }
1142 }
1143 
1144 static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1145 {
1146     struct anx78xx *anx78xx = data;
1147     bool event = false;
1148     unsigned int irq;
1149     int err;
1150 
1151     mutex_lock(&anx78xx->lock);
1152 
1153     err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1154               &irq);
1155     if (err) {
1156         DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1157         goto unlock;
1158     }
1159 
1160     if (irq)
1161         anx78xx_handle_dp_int_1(anx78xx, irq);
1162 
1163     err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1164               SP_COMMON_INT_STATUS4_REG, &irq);
1165     if (err) {
1166         DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1167               err);
1168         goto unlock;
1169     }
1170 
1171     if (irq)
1172         event = anx78xx_handle_common_int_4(anx78xx, irq);
1173 
1174     /* Make sure we are still powered after handle HPD events */
1175     if (!anx78xx->powered)
1176         goto unlock;
1177 
1178     err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1179               &irq);
1180     if (err) {
1181         DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1182         goto unlock;
1183     }
1184 
1185     if (irq)
1186         anx78xx_handle_hdmi_int_1(anx78xx, irq);
1187 
1188 unlock:
1189     mutex_unlock(&anx78xx->lock);
1190 
1191     if (event)
1192         drm_helper_hpd_irq_event(anx78xx->connector.dev);
1193 
1194     return IRQ_HANDLED;
1195 }
1196 
1197 static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1198 {
1199     unsigned int i;
1200 
1201     for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1202         i2c_unregister_device(anx78xx->i2c_dummy[i]);
1203 }
1204 
1205 static const struct regmap_config anx78xx_regmap_config = {
1206     .reg_bits = 8,
1207     .val_bits = 8,
1208 };
1209 
1210 static const u16 anx78xx_chipid_list[] = {
1211     0x7808,
1212     0x7812,
1213     0x7814,
1214     0x7818,
1215 };
1216 
1217 static int anx78xx_i2c_probe(struct i2c_client *client,
1218                  const struct i2c_device_id *id)
1219 {
1220     struct anx78xx *anx78xx;
1221     struct anx78xx_platform_data *pdata;
1222     unsigned int i, idl, idh, version;
1223     const u8 *i2c_addresses;
1224     bool found = false;
1225     int err;
1226 
1227     anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1228     if (!anx78xx)
1229         return -ENOMEM;
1230 
1231     pdata = &anx78xx->pdata;
1232 
1233     mutex_init(&anx78xx->lock);
1234 
1235 #if IS_ENABLED(CONFIG_OF)
1236     anx78xx->bridge.of_node = client->dev.of_node;
1237 #endif
1238 
1239     anx78xx->client = client;
1240     i2c_set_clientdata(client, anx78xx);
1241 
1242     err = anx78xx_init_pdata(anx78xx);
1243     if (err) {
1244         if (err != -EPROBE_DEFER)
1245             DRM_ERROR("Failed to initialize pdata: %d\n", err);
1246 
1247         return err;
1248     }
1249 
1250     pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1251     if (pdata->hpd_irq < 0) {
1252         DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1253         return -ENODEV;
1254     }
1255 
1256     pdata->intp_irq = client->irq;
1257     if (!pdata->intp_irq) {
1258         DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1259         return -ENODEV;
1260     }
1261 
1262     /* Map slave addresses of ANX7814 */
1263     i2c_addresses = device_get_match_data(&client->dev);
1264     for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1265         struct i2c_client *i2c_dummy;
1266 
1267         i2c_dummy = i2c_new_dummy_device(client->adapter,
1268                          i2c_addresses[i] >> 1);
1269         if (IS_ERR(i2c_dummy)) {
1270             err = PTR_ERR(i2c_dummy);
1271             DRM_ERROR("Failed to reserve I2C bus %02x: %d\n",
1272                   i2c_addresses[i], err);
1273             goto err_unregister_i2c;
1274         }
1275 
1276         anx78xx->i2c_dummy[i] = i2c_dummy;
1277         anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1278                                &anx78xx_regmap_config);
1279         if (IS_ERR(anx78xx->map[i])) {
1280             err = PTR_ERR(anx78xx->map[i]);
1281             DRM_ERROR("Failed regmap initialization %02x\n",
1282                   i2c_addresses[i]);
1283             goto err_unregister_i2c;
1284         }
1285     }
1286 
1287     /* Look for supported chip ID */
1288     anx78xx_poweron(anx78xx);
1289 
1290     err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1291               &idl);
1292     if (err)
1293         goto err_poweroff;
1294 
1295     err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1296               &idh);
1297     if (err)
1298         goto err_poweroff;
1299 
1300     anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1301 
1302     err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1303               &version);
1304     if (err)
1305         goto err_poweroff;
1306 
1307     for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1308         if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1309             DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1310                  anx78xx->chipid, version);
1311             found = true;
1312             break;
1313         }
1314     }
1315 
1316     if (!found) {
1317         DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1318               anx78xx->chipid, version);
1319         err = -ENODEV;
1320         goto err_poweroff;
1321     }
1322 
1323     err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1324                     anx78xx_hpd_threaded_handler,
1325                     IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1326                     "anx78xx-hpd", anx78xx);
1327     if (err) {
1328         DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1329               err);
1330         goto err_poweroff;
1331     }
1332 
1333     err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1334                     anx78xx_intp_threaded_handler,
1335                     IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1336                     "anx78xx-intp", anx78xx);
1337     if (err) {
1338         DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1339         goto err_poweroff;
1340     }
1341 
1342     anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1343 
1344     drm_bridge_add(&anx78xx->bridge);
1345 
1346     /* If cable is pulled out, just poweroff and wait for HPD event */
1347     if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1348         anx78xx_poweroff(anx78xx);
1349 
1350     return 0;
1351 
1352 err_poweroff:
1353     anx78xx_poweroff(anx78xx);
1354 
1355 err_unregister_i2c:
1356     unregister_i2c_dummy_clients(anx78xx);
1357     return err;
1358 }
1359 
1360 static int anx78xx_i2c_remove(struct i2c_client *client)
1361 {
1362     struct anx78xx *anx78xx = i2c_get_clientdata(client);
1363 
1364     drm_bridge_remove(&anx78xx->bridge);
1365 
1366     unregister_i2c_dummy_clients(anx78xx);
1367 
1368     kfree(anx78xx->edid);
1369 
1370     return 0;
1371 }
1372 
1373 static const struct i2c_device_id anx78xx_id[] = {
1374     { "anx7814", 0 },
1375     { /* sentinel */ }
1376 };
1377 MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1378 
1379 #if IS_ENABLED(CONFIG_OF)
1380 static const struct of_device_id anx78xx_match_table[] = {
1381     { .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses },
1382     { .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses },
1383     { .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses },
1384     { .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses },
1385     { /* sentinel */ },
1386 };
1387 MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1388 #endif
1389 
1390 static struct i2c_driver anx78xx_driver = {
1391     .driver = {
1392            .name = "anx7814",
1393            .of_match_table = of_match_ptr(anx78xx_match_table),
1394           },
1395     .probe = anx78xx_i2c_probe,
1396     .remove = anx78xx_i2c_remove,
1397     .id_table = anx78xx_id,
1398 };
1399 module_i2c_driver(anx78xx_driver);
1400 
1401 MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1402 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1403 MODULE_LICENSE("GPL v2");
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