bridge/adv7511/adv7533.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/of_graph.h>
0007
0008 #include "adv7511.h"
0009
0010 static const struct reg_sequence adv7533_fixed_registers[] = {
0011     { 0x16, 0x20 },
0012     { 0x9a, 0xe0 },
0013     { 0xba, 0x70 },
0014     { 0xde, 0x82 },
0015     { 0xe4, 0x40 },
0016     { 0xe5, 0x80 },
0017 };
0018
0019 static const struct reg_sequence adv7533_cec_fixed_registers[] = {
0020     { 0x15, 0xd0 },
0021     { 0x17, 0xd0 },
0022     { 0x24, 0x20 },
0023     { 0x57, 0x11 },
0024     { 0x05, 0xc8 },
0025 };
0026
0027 static void adv7511_dsi_config_timing_gen(struct adv7511 *adv)
0028 {
0029     struct mipi_dsi_device *dsi = adv->dsi;
0030     struct drm_display_mode *mode = &adv->curr_mode;
0031     unsigned int hsw, hfp, hbp, vsw, vfp, vbp;
0032     static const u8 clock_div_by_lanes[] = { 6, 4, 3 }; /* 2, 3, 4 lanes */
0033
0034     hsw = mode->hsync_end - mode->hsync_start;
0035     hfp = mode->hsync_start - mode->hdisplay;
0036     hbp = mode->htotal - mode->hsync_end;
0037     vsw = mode->vsync_end - mode->vsync_start;
0038     vfp = mode->vsync_start - mode->vdisplay;
0039     vbp = mode->vtotal - mode->vsync_end;
0040
0041     /* set pixel clock divider mode */
0042     regmap_write(adv->regmap_cec, 0x16,
0043              clock_div_by_lanes[dsi->lanes - 2] << 3);
0044
0045     /* horizontal porch params */
0046     regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4);
0047     regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff);
0048     regmap_write(adv->regmap_cec, 0x2a, hsw >> 4);
0049     regmap_write(adv->regmap_cec, 0x2b, (hsw << 4) & 0xff);
0050     regmap_write(adv->regmap_cec, 0x2c, hfp >> 4);
0051     regmap_write(adv->regmap_cec, 0x2d, (hfp << 4) & 0xff);
0052     regmap_write(adv->regmap_cec, 0x2e, hbp >> 4);
0053     regmap_write(adv->regmap_cec, 0x2f, (hbp << 4) & 0xff);
0054
0055     /* vertical porch params */
0056     regmap_write(adv->regmap_cec, 0x30, mode->vtotal >> 4);
0057     regmap_write(adv->regmap_cec, 0x31, (mode->vtotal << 4) & 0xff);
0058     regmap_write(adv->regmap_cec, 0x32, vsw >> 4);
0059     regmap_write(adv->regmap_cec, 0x33, (vsw << 4) & 0xff);
0060     regmap_write(adv->regmap_cec, 0x34, vfp >> 4);
0061     regmap_write(adv->regmap_cec, 0x35, (vfp << 4) & 0xff);
0062     regmap_write(adv->regmap_cec, 0x36, vbp >> 4);
0063     regmap_write(adv->regmap_cec, 0x37, (vbp << 4) & 0xff);
0064 }
0065
0066 void adv7533_dsi_power_on(struct adv7511 *adv)
0067 {
0068     struct mipi_dsi_device *dsi = adv->dsi;
0069
0070     if (adv->use_timing_gen)
0071         adv7511_dsi_config_timing_gen(adv);
0072
0073     /* set number of dsi lanes */
0074     regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4);
0075
0076     if (adv->use_timing_gen) {
0077         /* reset internal timing generator */
0078         regmap_write(adv->regmap_cec, 0x27, 0xcb);
0079         regmap_write(adv->regmap_cec, 0x27, 0x8b);
0080         regmap_write(adv->regmap_cec, 0x27, 0xcb);
0081     } else {
0082         /* disable internal timing generator */
0083         regmap_write(adv->regmap_cec, 0x27, 0x0b);
0084     }
0085
0086     /* enable hdmi */
0087     regmap_write(adv->regmap_cec, 0x03, 0x89);
0088     /* disable test mode */
0089     regmap_write(adv->regmap_cec, 0x55, 0x00);
0090
0091     regmap_register_patch(adv->regmap_cec, adv7533_cec_fixed_registers,
0092                   ARRAY_SIZE(adv7533_cec_fixed_registers));
0093 }
0094
0095 void adv7533_dsi_power_off(struct adv7511 *adv)
0096 {
0097     /* disable hdmi */
0098     regmap_write(adv->regmap_cec, 0x03, 0x0b);
0099     /* disable internal timing generator */
0100     regmap_write(adv->regmap_cec, 0x27, 0x0b);
0101 }
0102
0103 void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode)
0104 {
0105     struct mipi_dsi_device *dsi = adv->dsi;
0106     int lanes, ret;
0107
0108     if (adv->num_dsi_lanes != 4)
0109         return;
0110
0111     if (mode->clock > 80000)
0112         lanes = 4;
0113     else
0114         lanes = 3;
0115
0116     if (lanes != dsi->lanes) {
0117         mipi_dsi_detach(dsi);
0118         dsi->lanes = lanes;
0119         ret = mipi_dsi_attach(dsi);
0120         if (ret)
0121             dev_err(&dsi->dev, "failed to change host lanes\n");
0122     }
0123 }
0124
0125 int adv7533_patch_registers(struct adv7511 *adv)
0126 {
0127     return regmap_register_patch(adv->regmap,
0128                      adv7533_fixed_registers,
0129                      ARRAY_SIZE(adv7533_fixed_registers));
0130 }
0131
0132 int adv7533_patch_cec_registers(struct adv7511 *adv)
0133 {
0134     return regmap_register_patch(adv->regmap_cec,
0135                     adv7533_cec_fixed_registers,
0136                     ARRAY_SIZE(adv7533_cec_fixed_registers));
0137 }
0138
0139 int adv7533_attach_dsi(struct adv7511 *adv)
0140 {
0141     struct device *dev = &adv->i2c_main->dev;
0142     struct mipi_dsi_host *host;
0143     struct mipi_dsi_device *dsi;
0144     int ret = 0;
0145     const struct mipi_dsi_device_info info = { .type = "adv7533",
0146                            .channel = 0,
0147                            .node = NULL,
0148                          };
0149
0150     host = of_find_mipi_dsi_host_by_node(adv->host_node);
0151     if (!host) {
0152         dev_err(dev, "failed to find dsi host\n");
0153         return -EPROBE_DEFER;
0154     }
0155
0156     dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
0157     if (IS_ERR(dsi)) {
0158         dev_err(dev, "failed to create dsi device\n");
0159         return PTR_ERR(dsi);
0160     }
0161
0162     adv->dsi = dsi;
0163
0164     dsi->lanes = adv->num_dsi_lanes;
0165     dsi->format = MIPI_DSI_FMT_RGB888;
0166     dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
0167               MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
0168
0169     ret = devm_mipi_dsi_attach(dev, dsi);
0170     if (ret < 0) {
0171         dev_err(dev, "failed to attach dsi to host\n");
0172         return ret;
0173     }
0174
0175     return 0;
0176 }
0177
0178 int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv)
0179 {
0180     u32 num_lanes;
0181
0182     of_property_read_u32(np, "adi,dsi-lanes", &num_lanes);
0183
0184     if (num_lanes < 1 || num_lanes > 4)
0185         return -EINVAL;
0186
0187     adv->num_dsi_lanes = num_lanes;
0188
0189     adv->host_node = of_graph_get_remote_node(np, 0, 0);
0190     if (!adv->host_node)
0191         return -ENODEV;
0192
0193     of_node_put(adv->host_node);
0194
0195     adv->use_timing_gen = !of_property_read_bool(np,
0196                         "adi,disable-timing-generator");
0197
0198     /* TODO: Check if these need to be parsed by DT or not */
0199     adv->rgb = true;
0200     adv->embedded_sync = false;
0201
0202     return 0;
0203 }