bridge/adv7511/adv7511.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Analog Devices ADV7511 HDMI transmitter driver
0004  *
0005  * Copyright 2012 Analog Devices Inc.
0006  */
0007
0008 #ifndef __DRM_I2C_ADV7511_H__
0009 #define __DRM_I2C_ADV7511_H__
0010
0011 #include <linux/hdmi.h>
0012 #include <linux/i2c.h>
0013 #include <linux/regmap.h>
0014 #include <linux/regulator/consumer.h>
0015
0016 #include <drm/drm_bridge.h>
0017 #include <drm/drm_connector.h>
0018 #include <drm/drm_mipi_dsi.h>
0019 #include <drm/drm_modes.h>
0020
0021 #define ADV7511_REG_CHIP_REVISION       0x00
0022 #define ADV7511_REG_N0              0x01
0023 #define ADV7511_REG_N1              0x02
0024 #define ADV7511_REG_N2              0x03
0025 #define ADV7511_REG_SPDIF_FREQ          0x04
0026 #define ADV7511_REG_CTS_AUTOMATIC1      0x05
0027 #define ADV7511_REG_CTS_AUTOMATIC2      0x06
0028 #define ADV7511_REG_CTS_MANUAL0         0x07
0029 #define ADV7511_REG_CTS_MANUAL1         0x08
0030 #define ADV7511_REG_CTS_MANUAL2         0x09
0031 #define ADV7511_REG_AUDIO_SOURCE        0x0a
0032 #define ADV7511_REG_AUDIO_CONFIG        0x0b
0033 #define ADV7511_REG_I2S_CONFIG          0x0c
0034 #define ADV7511_REG_I2S_WIDTH           0x0d
0035 #define ADV7511_REG_AUDIO_SUB_SRC0      0x0e
0036 #define ADV7511_REG_AUDIO_SUB_SRC1      0x0f
0037 #define ADV7511_REG_AUDIO_SUB_SRC2      0x10
0038 #define ADV7511_REG_AUDIO_SUB_SRC3      0x11
0039 #define ADV7511_REG_AUDIO_CFG1          0x12
0040 #define ADV7511_REG_AUDIO_CFG2          0x13
0041 #define ADV7511_REG_AUDIO_CFG3          0x14
0042 #define ADV7511_REG_I2C_FREQ_ID_CFG     0x15
0043 #define ADV7511_REG_VIDEO_INPUT_CFG1        0x16
0044 #define ADV7511_REG_CSC_UPPER(x)        (0x18 + (x) * 2)
0045 #define ADV7511_REG_CSC_LOWER(x)        (0x19 + (x) * 2)
0046 #define ADV7511_REG_SYNC_DECODER(x)     (0x30 + (x))
0047 #define ADV7511_REG_DE_GENERATOR        (0x35 + (x))
0048 #define ADV7511_REG_PIXEL_REPETITION        0x3b
0049 #define ADV7511_REG_VIC_MANUAL          0x3c
0050 #define ADV7511_REG_VIC_SEND            0x3d
0051 #define ADV7511_REG_VIC_DETECTED        0x3e
0052 #define ADV7511_REG_AUX_VIC_DETECTED        0x3f
0053 #define ADV7511_REG_PACKET_ENABLE0      0x40
0054 #define ADV7511_REG_POWER           0x41
0055 #define ADV7511_REG_STATUS          0x42
0056 #define ADV7511_REG_EDID_I2C_ADDR       0x43
0057 #define ADV7511_REG_PACKET_ENABLE1      0x44
0058 #define ADV7511_REG_PACKET_I2C_ADDR     0x45
0059 #define ADV7511_REG_DSD_ENABLE          0x46
0060 #define ADV7511_REG_VIDEO_INPUT_CFG2        0x48
0061 #define ADV7511_REG_INFOFRAME_UPDATE        0x4a
0062 #define ADV7511_REG_GC(x)           (0x4b + (x)) /* 0x4b - 0x51 */
0063 #define ADV7511_REG_AVI_INFOFRAME_VERSION   0x52
0064 #define ADV7511_REG_AVI_INFOFRAME_LENGTH    0x53
0065 #define ADV7511_REG_AVI_INFOFRAME_CHECKSUM  0x54
0066 #define ADV7511_REG_AVI_INFOFRAME(x)        (0x55 + (x)) /* 0x55 - 0x6f */
0067 #define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x70
0068 #define ADV7511_REG_AUDIO_INFOFRAME_LENGTH  0x71
0069 #define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM    0x72
0070 #define ADV7511_REG_AUDIO_INFOFRAME(x)      (0x73 + (x)) /* 0x73 - 0x7c */
0071 #define ADV7511_REG_INT_ENABLE(x)       (0x94 + (x))
0072 #define ADV7511_REG_INT(x)          (0x96 + (x))
0073 #define ADV7511_REG_INPUT_CLK_DIV       0x9d
0074 #define ADV7511_REG_PLL_STATUS          0x9e
0075 #define ADV7511_REG_HDMI_POWER          0xa1
0076 #define ADV7511_REG_HDCP_HDMI_CFG       0xaf
0077 #define ADV7511_REG_AN(x)           (0xb0 + (x)) /* 0xb0 - 0xb7 */
0078 #define ADV7511_REG_HDCP_STATUS         0xb8
0079 #define ADV7511_REG_BCAPS           0xbe
0080 #define ADV7511_REG_BKSV(x)         (0xc0 + (x)) /* 0xc0 - 0xc3 */
0081 #define ADV7511_REG_EDID_SEGMENT        0xc4
0082 #define ADV7511_REG_DDC_STATUS          0xc8
0083 #define ADV7511_REG_EDID_READ_CTRL      0xc9
0084 #define ADV7511_REG_BSTATUS(x)          (0xca + (x)) /* 0xca - 0xcb */
0085 #define ADV7511_REG_TIMING_GEN_SEQ      0xd0
0086 #define ADV7511_REG_POWER2          0xd6
0087 #define ADV7511_REG_HSYNC_PLACEMENT_MSB     0xfa
0088
0089 #define ADV7511_REG_SYNC_ADJUSTMENT(x)      (0xd7 + (x)) /* 0xd7 - 0xdc */
0090 #define ADV7511_REG_TMDS_CLOCK_INV      0xde
0091 #define ADV7511_REG_ARC_CTRL            0xdf
0092 #define ADV7511_REG_CEC_I2C_ADDR        0xe1
0093 #define ADV7511_REG_CEC_CTRL            0xe2
0094 #define ADV7511_REG_CHIP_ID_HIGH        0xf5
0095 #define ADV7511_REG_CHIP_ID_LOW         0xf6
0096
0097 /* Hardware defined default addresses for I2C register maps */
0098 #define ADV7511_CEC_I2C_ADDR_DEFAULT        0x3c
0099 #define ADV7511_EDID_I2C_ADDR_DEFAULT       0x3f
0100 #define ADV7511_PACKET_I2C_ADDR_DEFAULT     0x38
0101
0102 #define ADV7511_CSC_ENABLE          BIT(7)
0103 #define ADV7511_CSC_UPDATE_MODE         BIT(5)
0104
0105 #define ADV7511_INT0_HPD            BIT(7)
0106 #define ADV7511_INT0_VSYNC          BIT(5)
0107 #define ADV7511_INT0_AUDIO_FIFO_FULL        BIT(4)
0108 #define ADV7511_INT0_EDID_READY         BIT(2)
0109 #define ADV7511_INT0_HDCP_AUTHENTICATED     BIT(1)
0110
0111 #define ADV7511_INT1_DDC_ERROR          BIT(7)
0112 #define ADV7511_INT1_BKSV           BIT(6)
0113 #define ADV7511_INT1_CEC_TX_READY       BIT(5)
0114 #define ADV7511_INT1_CEC_TX_ARBIT_LOST      BIT(4)
0115 #define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT   BIT(3)
0116 #define ADV7511_INT1_CEC_RX_READY3      BIT(2)
0117 #define ADV7511_INT1_CEC_RX_READY2      BIT(1)
0118 #define ADV7511_INT1_CEC_RX_READY1      BIT(0)
0119
0120 #define ADV7511_ARC_CTRL_POWER_DOWN     BIT(0)
0121
0122 #define ADV7511_CEC_CTRL_POWER_DOWN     BIT(0)
0123
0124 #define ADV7511_POWER_POWER_DOWN        BIT(6)
0125
0126 #define ADV7511_HDMI_CFG_MODE_MASK      0x2
0127 #define ADV7511_HDMI_CFG_MODE_DVI       0x0
0128 #define ADV7511_HDMI_CFG_MODE_HDMI      0x2
0129
0130 #define ADV7511_AUDIO_SELECT_I2C        0x0
0131 #define ADV7511_AUDIO_SELECT_SPDIF      0x1
0132 #define ADV7511_AUDIO_SELECT_DSD        0x2
0133 #define ADV7511_AUDIO_SELECT_HBR        0x3
0134 #define ADV7511_AUDIO_SELECT_DST        0x4
0135
0136 #define ADV7511_I2S_SAMPLE_LEN_16       0x2
0137 #define ADV7511_I2S_SAMPLE_LEN_20       0x3
0138 #define ADV7511_I2S_SAMPLE_LEN_18       0x4
0139 #define ADV7511_I2S_SAMPLE_LEN_22       0x5
0140 #define ADV7511_I2S_SAMPLE_LEN_19       0x8
0141 #define ADV7511_I2S_SAMPLE_LEN_23       0x9
0142 #define ADV7511_I2S_SAMPLE_LEN_24       0xb
0143 #define ADV7511_I2S_SAMPLE_LEN_17       0xc
0144 #define ADV7511_I2S_SAMPLE_LEN_21       0xd
0145
0146 #define ADV7511_SAMPLE_FREQ_44100       0x0
0147 #define ADV7511_SAMPLE_FREQ_48000       0x2
0148 #define ADV7511_SAMPLE_FREQ_32000       0x3
0149 #define ADV7511_SAMPLE_FREQ_88200       0x8
0150 #define ADV7511_SAMPLE_FREQ_96000       0xa
0151 #define ADV7511_SAMPLE_FREQ_176400      0xc
0152 #define ADV7511_SAMPLE_FREQ_192000      0xe
0153
0154 #define ADV7511_STATUS_POWER_DOWN_POLARITY  BIT(7)
0155 #define ADV7511_STATUS_HPD          BIT(6)
0156 #define ADV7511_STATUS_MONITOR_SENSE        BIT(5)
0157 #define ADV7511_STATUS_I2S_32BIT_MODE       BIT(3)
0158
0159 #define ADV7511_PACKET_ENABLE_N_CTS     BIT(8+6)
0160 #define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE  BIT(8+5)
0161 #define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
0162 #define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME   BIT(8+3)
0163 #define ADV7511_PACKET_ENABLE_GC        BIT(7)
0164 #define ADV7511_PACKET_ENABLE_SPD       BIT(6)
0165 #define ADV7511_PACKET_ENABLE_MPEG      BIT(5)
0166 #define ADV7511_PACKET_ENABLE_ACP       BIT(4)
0167 #define ADV7511_PACKET_ENABLE_ISRC      BIT(3)
0168 #define ADV7511_PACKET_ENABLE_GM        BIT(2)
0169 #define ADV7511_PACKET_ENABLE_SPARE2        BIT(1)
0170 #define ADV7511_PACKET_ENABLE_SPARE1        BIT(0)
0171
0172 #define ADV7535_REG_POWER2_HPD_OVERRIDE     BIT(6)
0173 #define ADV7511_REG_POWER2_HPD_SRC_MASK     0xc0
0174 #define ADV7511_REG_POWER2_HPD_SRC_BOTH     0x00
0175 #define ADV7511_REG_POWER2_HPD_SRC_HPD      0x40
0176 #define ADV7511_REG_POWER2_HPD_SRC_CEC      0x80
0177 #define ADV7511_REG_POWER2_HPD_SRC_NONE     0xc0
0178 #define ADV7511_REG_POWER2_TDMS_ENABLE      BIT(4)
0179 #define ADV7511_REG_POWER2_GATE_INPUT_CLK   BIT(0)
0180
0181 #define ADV7511_LOW_REFRESH_RATE_NONE       0x0
0182 #define ADV7511_LOW_REFRESH_RATE_24HZ       0x1
0183 #define ADV7511_LOW_REFRESH_RATE_25HZ       0x2
0184 #define ADV7511_LOW_REFRESH_RATE_30HZ       0x3
0185
0186 #define ADV7511_AUDIO_CFG3_LEN_MASK     0x0f
0187 #define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK   0xf0
0188
0189 #define ADV7511_AUDIO_SOURCE_I2S        0
0190 #define ADV7511_AUDIO_SOURCE_SPDIF      1
0191
0192 #define ADV7511_I2S_FORMAT_I2S          0
0193 #define ADV7511_I2S_FORMAT_RIGHT_J      1
0194 #define ADV7511_I2S_FORMAT_LEFT_J       2
0195 #define ADV7511_I2S_IEC958_DIRECT       3
0196
0197 #define ADV7511_PACKET(p, x)        ((p) * 0x20 + (x))
0198 #define ADV7511_PACKET_SDP(x)       ADV7511_PACKET(0, x)
0199 #define ADV7511_PACKET_MPEG(x)      ADV7511_PACKET(1, x)
0200 #define ADV7511_PACKET_ACP(x)       ADV7511_PACKET(2, x)
0201 #define ADV7511_PACKET_ISRC1(x)     ADV7511_PACKET(3, x)
0202 #define ADV7511_PACKET_ISRC2(x)     ADV7511_PACKET(4, x)
0203 #define ADV7511_PACKET_GM(x)        ADV7511_PACKET(5, x)
0204 #define ADV7511_PACKET_SPARE(x)     ADV7511_PACKET(6, x)
0205
0206 #define ADV7511_REG_CEC_TX_FRAME_HDR    0x00
0207 #define ADV7511_REG_CEC_TX_FRAME_DATA0  0x01
0208 #define ADV7511_REG_CEC_TX_FRAME_LEN    0x10
0209 #define ADV7511_REG_CEC_TX_ENABLE   0x11
0210 #define ADV7511_REG_CEC_TX_RETRY    0x12
0211 #define ADV7511_REG_CEC_TX_LOW_DRV_CNT  0x14
0212 #define ADV7511_REG_CEC_RX1_FRAME_HDR   0x15
0213 #define ADV7511_REG_CEC_RX1_FRAME_DATA0 0x16
0214 #define ADV7511_REG_CEC_RX1_FRAME_LEN   0x25
0215 #define ADV7511_REG_CEC_RX_STATUS   0x26
0216 #define ADV7511_REG_CEC_RX2_FRAME_HDR   0x27
0217 #define ADV7511_REG_CEC_RX2_FRAME_DATA0 0x28
0218 #define ADV7511_REG_CEC_RX2_FRAME_LEN   0x37
0219 #define ADV7511_REG_CEC_RX3_FRAME_HDR   0x38
0220 #define ADV7511_REG_CEC_RX3_FRAME_DATA0 0x39
0221 #define ADV7511_REG_CEC_RX3_FRAME_LEN   0x48
0222 #define ADV7511_REG_CEC_RX_BUFFERS  0x4a
0223 #define ADV7511_REG_CEC_LOG_ADDR_MASK   0x4b
0224 #define ADV7511_REG_CEC_LOG_ADDR_0_1    0x4c
0225 #define ADV7511_REG_CEC_LOG_ADDR_2  0x4d
0226 #define ADV7511_REG_CEC_CLK_DIV     0x4e
0227 #define ADV7511_REG_CEC_SOFT_RESET  0x50
0228
0229 #define ADV7533_REG_CEC_OFFSET      0x70
0230
0231 enum adv7511_input_clock {
0232     ADV7511_INPUT_CLOCK_1X,
0233     ADV7511_INPUT_CLOCK_2X,
0234     ADV7511_INPUT_CLOCK_DDR,
0235 };
0236
0237 enum adv7511_input_justification {
0238     ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,
0239     ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,
0240     ADV7511_INPUT_JUSTIFICATION_LEFT = 2,
0241 };
0242
0243 enum adv7511_input_sync_pulse {
0244     ADV7511_INPUT_SYNC_PULSE_DE = 0,
0245     ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,
0246     ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,
0247     ADV7511_INPUT_SYNC_PULSE_NONE = 3,
0248 };
0249
0250 /**
0251  * enum adv7511_sync_polarity - Polarity for the input sync signals
0252  * @ADV7511_SYNC_POLARITY_PASSTHROUGH:  Sync polarity matches that of
0253  *                     the currently configured mode.
0254  * @ADV7511_SYNC_POLARITY_LOW:      Sync polarity is low
0255  * @ADV7511_SYNC_POLARITY_HIGH:     Sync polarity is high
0256  *
0257  * If the polarity is set to either LOW or HIGH the driver will configure the
0258  * ADV7511 to internally invert the sync signal if required to match the sync
0259  * polarity setting for the currently selected output mode.
0260  *
0261  * If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal
0262  * unchanged. This is used when the upstream graphics core already generates
0263  * the sync signals with the correct polarity.
0264  */
0265 enum adv7511_sync_polarity {
0266     ADV7511_SYNC_POLARITY_PASSTHROUGH,
0267     ADV7511_SYNC_POLARITY_LOW,
0268     ADV7511_SYNC_POLARITY_HIGH,
0269 };
0270
0271 /**
0272  * struct adv7511_link_config - Describes adv7511 hardware configuration
0273  * @input_color_depth:      Number of bits per color component (8, 10 or 12)
0274  * @input_colorspace:       The input colorspace (RGB, YUV444, YUV422)
0275  * @input_clock:        The input video clock style (1x, 2x, DDR)
0276  * @input_style:        The input component arrangement variant
0277  * @input_justification:    Video input format bit justification
0278  * @clock_delay:        Clock delay for the input clock (in ps)
0279  * @embedded_sync:      Video input uses BT.656-style embedded sync
0280  * @sync_pulse:         Select the sync pulse
0281  * @vsync_polarity:     vsync input signal configuration
0282  * @hsync_polarity:     hsync input signal configuration
0283  */
0284 struct adv7511_link_config {
0285     unsigned int input_color_depth;
0286     enum hdmi_colorspace input_colorspace;
0287     enum adv7511_input_clock input_clock;
0288     unsigned int input_style;
0289     enum adv7511_input_justification input_justification;
0290
0291     int clock_delay;
0292
0293     bool embedded_sync;
0294     enum adv7511_input_sync_pulse sync_pulse;
0295     enum adv7511_sync_polarity vsync_polarity;
0296     enum adv7511_sync_polarity hsync_polarity;
0297 };
0298
0299 /**
0300  * enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC
0301  * @ADV7511_CSC_SCALING_1: CSC results are not scaled
0302  * @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two
0303  * @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four
0304  */
0305 enum adv7511_csc_scaling {
0306     ADV7511_CSC_SCALING_1 = 0,
0307     ADV7511_CSC_SCALING_2 = 1,
0308     ADV7511_CSC_SCALING_4 = 2,
0309 };
0310
0311 /**
0312  * struct adv7511_video_config - Describes adv7511 hardware configuration
0313  * @csc_enable:         Whether to enable color space conversion
0314  * @csc_scaling_factor:     Color space conversion scaling factor
0315  * @csc_coefficents:        Color space conversion coefficents
0316  * @hdmi_mode:          Whether to use HDMI or DVI output mode
0317  * @avi_infoframe:      HDMI infoframe
0318  */
0319 struct adv7511_video_config {
0320     bool csc_enable;
0321     enum adv7511_csc_scaling csc_scaling_factor;
0322     const uint16_t *csc_coefficents;
0323
0324     bool hdmi_mode;
0325     struct hdmi_avi_infoframe avi_infoframe;
0326 };
0327
0328 enum adv7511_type {
0329     ADV7511,
0330     ADV7533,
0331     ADV7535,
0332 };
0333
0334 #define ADV7511_MAX_ADDRS 3
0335
0336 struct adv7511 {
0337     struct i2c_client *i2c_main;
0338     struct i2c_client *i2c_edid;
0339     struct i2c_client *i2c_packet;
0340     struct i2c_client *i2c_cec;
0341
0342     struct regmap *regmap;
0343     struct regmap *regmap_cec;
0344     unsigned int reg_cec_offset;
0345     enum drm_connector_status status;
0346     bool powered;
0347
0348     struct drm_display_mode curr_mode;
0349
0350     unsigned int f_tmds;
0351     unsigned int f_audio;
0352     unsigned int audio_source;
0353
0354     unsigned int current_edid_segment;
0355     uint8_t edid_buf[256];
0356     bool edid_read;
0357
0358     wait_queue_head_t wq;
0359     struct work_struct hpd_work;
0360
0361     struct drm_bridge bridge;
0362     struct drm_connector connector;
0363
0364     bool embedded_sync;
0365     enum adv7511_sync_polarity vsync_polarity;
0366     enum adv7511_sync_polarity hsync_polarity;
0367     bool rgb;
0368
0369     struct gpio_desc *gpio_pd;
0370
0371     struct regulator_bulk_data *supplies;
0372     unsigned int num_supplies;
0373
0374     /* ADV7533 DSI RX related params */
0375     struct device_node *host_node;
0376     struct mipi_dsi_device *dsi;
0377     u8 num_dsi_lanes;
0378     bool use_timing_gen;
0379
0380     enum adv7511_type type;
0381     struct platform_device *audio_pdev;
0382
0383     struct cec_adapter *cec_adap;
0384     u8   cec_addr[ADV7511_MAX_ADDRS];
0385     u8   cec_valid_addrs;
0386     bool cec_enabled_adap;
0387     struct clk *cec_clk;
0388     u32 cec_clk_freq;
0389 };
0390
0391 #ifdef CONFIG_DRM_I2C_ADV7511_CEC
0392 int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);
0393 void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
0394 #else
0395 static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
0396 {
0397     unsigned int offset = adv7511->type == ADV7533 ?
0398                         ADV7533_REG_CEC_OFFSET : 0;
0399
0400     regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
0401              ADV7511_CEC_CTRL_POWER_DOWN);
0402     return 0;
0403 }
0404 #endif
0405
0406 void adv7533_dsi_power_on(struct adv7511 *adv);
0407 void adv7533_dsi_power_off(struct adv7511 *adv);
0408 void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode);
0409 int adv7533_patch_registers(struct adv7511 *adv);
0410 int adv7533_patch_cec_registers(struct adv7511 *adv);
0411 int adv7533_attach_dsi(struct adv7511 *adv);
0412 int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
0413
0414 #ifdef CONFIG_DRM_I2C_ADV7511_AUDIO
0415 int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511);
0416 void adv7511_audio_exit(struct adv7511 *adv7511);
0417 #else /*CONFIG_DRM_I2C_ADV7511_AUDIO */
0418 static inline int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511)
0419 {
0420     return 0;
0421 }
0422 static inline void adv7511_audio_exit(struct adv7511 *adv7511)
0423 {
0424 }
0425 #endif /* CONFIG_DRM_I2C_ADV7511_AUDIO */
0426
0427 #endif /* __DRM_I2C_ADV7511_H__ */