drm/atmel-hlcdc/atmel_hlcdc_dc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Traphandler
0004  * Copyright (C) 2014 Free Electrons
0005  * Copyright (C) 2014 Atmel
0006  *
0007  * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
0008  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
0009  */
0010
0011 #ifndef DRM_ATMEL_HLCDC_H
0012 #define DRM_ATMEL_HLCDC_H
0013
0014 #include <linux/regmap.h>
0015
0016 #include <drm/drm_plane.h>
0017
0018 #define ATMEL_HLCDC_LAYER_CHER          0x0
0019 #define ATMEL_HLCDC_LAYER_CHDR          0x4
0020 #define ATMEL_HLCDC_LAYER_CHSR          0x8
0021 #define ATMEL_HLCDC_LAYER_EN            BIT(0)
0022 #define ATMEL_HLCDC_LAYER_UPDATE        BIT(1)
0023 #define ATMEL_HLCDC_LAYER_A2Q           BIT(2)
0024 #define ATMEL_HLCDC_LAYER_RST           BIT(8)
0025
0026 #define ATMEL_HLCDC_LAYER_IER           0xc
0027 #define ATMEL_HLCDC_LAYER_IDR           0x10
0028 #define ATMEL_HLCDC_LAYER_IMR           0x14
0029 #define ATMEL_HLCDC_LAYER_ISR           0x18
0030 #define ATMEL_HLCDC_LAYER_DFETCH        BIT(0)
0031 #define ATMEL_HLCDC_LAYER_LFETCH        BIT(1)
0032 #define ATMEL_HLCDC_LAYER_DMA_IRQ(p)        BIT(2 + (8 * (p)))
0033 #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p)       BIT(3 + (8 * (p)))
0034 #define ATMEL_HLCDC_LAYER_ADD_IRQ(p)        BIT(4 + (8 * (p)))
0035 #define ATMEL_HLCDC_LAYER_DONE_IRQ(p)       BIT(5 + (8 * (p)))
0036 #define ATMEL_HLCDC_LAYER_OVR_IRQ(p)        BIT(6 + (8 * (p)))
0037
0038 #define ATMEL_HLCDC_LAYER_PLANE_HEAD(p)     (((p) * 0x10) + 0x1c)
0039 #define ATMEL_HLCDC_LAYER_PLANE_ADDR(p)     (((p) * 0x10) + 0x20)
0040 #define ATMEL_HLCDC_LAYER_PLANE_CTRL(p)     (((p) * 0x10) + 0x24)
0041 #define ATMEL_HLCDC_LAYER_PLANE_NEXT(p)     (((p) * 0x10) + 0x28)
0042
0043 #define ATMEL_HLCDC_LAYER_DMA_CFG       0
0044 #define ATMEL_HLCDC_LAYER_DMA_SIF       BIT(0)
0045 #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK     GENMASK(5, 4)
0046 #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE   (0 << 4)
0047 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4    (1 << 4)
0048 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8    (2 << 4)
0049 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16   (3 << 4)
0050 #define ATMEL_HLCDC_LAYER_DMA_DLBO      BIT(8)
0051 #define ATMEL_HLCDC_LAYER_DMA_ROTDIS        BIT(12)
0052 #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS       BIT(13)
0053
0054 #define ATMEL_HLCDC_LAYER_FORMAT_CFG        1
0055 #define ATMEL_HLCDC_LAYER_RGB           (0 << 0)
0056 #define ATMEL_HLCDC_LAYER_CLUT          (1 << 0)
0057 #define ATMEL_HLCDC_LAYER_YUV           (2 << 0)
0058 #define ATMEL_HLCDC_RGB_MODE(m)         \
0059     (ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))
0060 #define ATMEL_HLCDC_CLUT_MODE(m)        \
0061     (ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))
0062 #define ATMEL_HLCDC_YUV_MODE(m)         \
0063     (ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))
0064 #define ATMEL_HLCDC_YUV422ROT           BIT(16)
0065 #define ATMEL_HLCDC_YUV422SWP           BIT(17)
0066 #define ATMEL_HLCDC_DSCALEOPT           BIT(20)
0067
0068 #define ATMEL_HLCDC_C1_MODE         ATMEL_HLCDC_CLUT_MODE(0)
0069 #define ATMEL_HLCDC_C2_MODE         ATMEL_HLCDC_CLUT_MODE(1)
0070 #define ATMEL_HLCDC_C4_MODE         ATMEL_HLCDC_CLUT_MODE(2)
0071 #define ATMEL_HLCDC_C8_MODE         ATMEL_HLCDC_CLUT_MODE(3)
0072
0073 #define ATMEL_HLCDC_XRGB4444_MODE       ATMEL_HLCDC_RGB_MODE(0)
0074 #define ATMEL_HLCDC_ARGB4444_MODE       ATMEL_HLCDC_RGB_MODE(1)
0075 #define ATMEL_HLCDC_RGBA4444_MODE       ATMEL_HLCDC_RGB_MODE(2)
0076 #define ATMEL_HLCDC_RGB565_MODE         ATMEL_HLCDC_RGB_MODE(3)
0077 #define ATMEL_HLCDC_ARGB1555_MODE       ATMEL_HLCDC_RGB_MODE(4)
0078 #define ATMEL_HLCDC_XRGB8888_MODE       ATMEL_HLCDC_RGB_MODE(9)
0079 #define ATMEL_HLCDC_RGB888_MODE         ATMEL_HLCDC_RGB_MODE(10)
0080 #define ATMEL_HLCDC_ARGB8888_MODE       ATMEL_HLCDC_RGB_MODE(12)
0081 #define ATMEL_HLCDC_RGBA8888_MODE       ATMEL_HLCDC_RGB_MODE(13)
0082
0083 #define ATMEL_HLCDC_AYUV_MODE           ATMEL_HLCDC_YUV_MODE(0)
0084 #define ATMEL_HLCDC_YUYV_MODE           ATMEL_HLCDC_YUV_MODE(1)
0085 #define ATMEL_HLCDC_UYVY_MODE           ATMEL_HLCDC_YUV_MODE(2)
0086 #define ATMEL_HLCDC_YVYU_MODE           ATMEL_HLCDC_YUV_MODE(3)
0087 #define ATMEL_HLCDC_VYUY_MODE           ATMEL_HLCDC_YUV_MODE(4)
0088 #define ATMEL_HLCDC_NV61_MODE           ATMEL_HLCDC_YUV_MODE(5)
0089 #define ATMEL_HLCDC_YUV422_MODE         ATMEL_HLCDC_YUV_MODE(6)
0090 #define ATMEL_HLCDC_NV21_MODE           ATMEL_HLCDC_YUV_MODE(7)
0091 #define ATMEL_HLCDC_YUV420_MODE         ATMEL_HLCDC_YUV_MODE(8)
0092
0093 #define ATMEL_HLCDC_LAYER_POS(x, y)     ((x) | ((y) << 16))
0094 #define ATMEL_HLCDC_LAYER_SIZE(w, h)        (((w) - 1) | (((h) - 1) << 16))
0095
0096 #define ATMEL_HLCDC_LAYER_CRKEY         BIT(0)
0097 #define ATMEL_HLCDC_LAYER_INV           BIT(1)
0098 #define ATMEL_HLCDC_LAYER_ITER2BL       BIT(2)
0099 #define ATMEL_HLCDC_LAYER_ITER          BIT(3)
0100 #define ATMEL_HLCDC_LAYER_REVALPHA      BIT(4)
0101 #define ATMEL_HLCDC_LAYER_GAEN          BIT(5)
0102 #define ATMEL_HLCDC_LAYER_LAEN          BIT(6)
0103 #define ATMEL_HLCDC_LAYER_OVR           BIT(7)
0104 #define ATMEL_HLCDC_LAYER_DMA           BIT(8)
0105 #define ATMEL_HLCDC_LAYER_REP           BIT(9)
0106 #define ATMEL_HLCDC_LAYER_DSTKEY        BIT(10)
0107 #define ATMEL_HLCDC_LAYER_DISCEN        BIT(11)
0108 #define ATMEL_HLCDC_LAYER_GA_SHIFT      16
0109 #define ATMEL_HLCDC_LAYER_GA_MASK       \
0110     GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
0111 #define ATMEL_HLCDC_LAYER_GA(x)         \
0112     ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
0113
0114 #define ATMEL_HLCDC_LAYER_DISC_POS(x, y)    ((x) | ((y) << 16))
0115 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h)   (((w) - 1) | (((h) - 1) << 16))
0116
0117 #define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y)  ((x) | ((y) << 16))
0118 #define ATMEL_HLCDC_LAYER_SCALER_ENABLE     BIT(31)
0119
0120 #define ATMEL_HLCDC_LAYER_MAX_PLANES        3
0121
0122 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED   BIT(0)
0123 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
0124 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE   BIT(2)
0125 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN    BIT(3)
0126
0127 #define ATMEL_HLCDC_CLUT_SIZE           256
0128
0129 #define ATMEL_HLCDC_MAX_LAYERS          6
0130
0131 /**
0132  * Atmel HLCDC Layer registers layout structure
0133  *
0134  * Each HLCDC layer has its own register organization and a given register
0135  * can be placed differently on 2 different layers depending on its
0136  * capabilities.
0137  * This structure stores common registers layout for a given layer and is
0138  * used by HLCDC layer code to choose the appropriate register to write to
0139  * or to read from.
0140  *
0141  * For all fields, a value of zero means "unsupported".
0142  *
0143  * See Atmel's datasheet for a detailled description of these registers.
0144  *
0145  * @xstride: xstride registers
0146  * @pstride: pstride registers
0147  * @pos: position register
0148  * @size: displayed size register
0149  * @memsize: memory size register
0150  * @default_color: default color register
0151  * @chroma_key: chroma key register
0152  * @chroma_key_mask: chroma key mask register
0153  * @general_config: general layer config register
0154  * @sacler_config: scaler factors register
0155  * @phicoeffs: X/Y PHI coefficient registers
0156  * @disc_pos: discard area position register
0157  * @disc_size: discard area size register
0158  * @csc: color space conversion register
0159  */
0160 struct atmel_hlcdc_layer_cfg_layout {
0161     int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
0162     int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
0163     int pos;
0164     int size;
0165     int memsize;
0166     int default_color;
0167     int chroma_key;
0168     int chroma_key_mask;
0169     int general_config;
0170     int scaler_config;
0171     struct {
0172         int x;
0173         int y;
0174     } phicoeffs;
0175     int disc_pos;
0176     int disc_size;
0177     int csc;
0178 };
0179
0180 /**
0181  * Atmel HLCDC DMA descriptor structure
0182  *
0183  * This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
0184  *
0185  * The structure fields must remain in this specific order, because they're
0186  * used by the HLCDC DMA engine, which expect them in this order.
0187  * HLCDC DMA descriptors must be aligned on 64 bits.
0188  *
0189  * @addr: buffer DMA address
0190  * @ctrl: DMA transfer options
0191  * @next: next DMA descriptor to fetch
0192  * @self: descriptor DMA address
0193  */
0194 struct atmel_hlcdc_dma_channel_dscr {
0195     dma_addr_t addr;
0196     u32 ctrl;
0197     dma_addr_t next;
0198     dma_addr_t self;
0199 } __aligned(sizeof(u64));
0200
0201 /**
0202  * Atmel HLCDC layer types
0203  */
0204 enum atmel_hlcdc_layer_type {
0205     ATMEL_HLCDC_NO_LAYER,
0206     ATMEL_HLCDC_BASE_LAYER,
0207     ATMEL_HLCDC_OVERLAY_LAYER,
0208     ATMEL_HLCDC_CURSOR_LAYER,
0209     ATMEL_HLCDC_PP_LAYER,
0210 };
0211
0212 /**
0213  * Atmel HLCDC Supported formats structure
0214  *
0215  * This structure list all the formats supported by a given layer.
0216  *
0217  * @nformats: number of supported formats
0218  * @formats: supported formats
0219  */
0220 struct atmel_hlcdc_formats {
0221     int nformats;
0222     u32 *formats;
0223 };
0224
0225 /**
0226  * Atmel HLCDC Layer description structure
0227  *
0228  * This structure describes the capabilities provided by a given layer.
0229  *
0230  * @name: layer name
0231  * @type: layer type
0232  * @id: layer id
0233  * @regs_offset: offset of the layer registers from the HLCDC registers base
0234  * @cfgs_offset: CFGX registers offset from the layer registers base
0235  * @formats: supported formats
0236  * @layout: config registers layout
0237  * @max_width: maximum width supported by this layer (0 means unlimited)
0238  * @max_height: maximum height supported by this layer (0 means unlimited)
0239  */
0240 struct atmel_hlcdc_layer_desc {
0241     const char *name;
0242     enum atmel_hlcdc_layer_type type;
0243     int id;
0244     int regs_offset;
0245     int cfgs_offset;
0246     int clut_offset;
0247     struct atmel_hlcdc_formats *formats;
0248     struct atmel_hlcdc_layer_cfg_layout layout;
0249     int max_width;
0250     int max_height;
0251 };
0252
0253 /**
0254  * Atmel HLCDC Layer.
0255  *
0256  * A layer can be a DRM plane of a post processing layer used to render
0257  * HLCDC composition into memory.
0258  *
0259  * @desc: layer description
0260  * @regmap: pointer to the HLCDC regmap
0261  */
0262 struct atmel_hlcdc_layer {
0263     const struct atmel_hlcdc_layer_desc *desc;
0264     struct regmap *regmap;
0265 };
0266
0267 /**
0268  * Atmel HLCDC Plane.
0269  *
0270  * @base: base DRM plane structure
0271  * @layer: HLCDC layer structure
0272  * @properties: pointer to the property definitions structure
0273  */
0274 struct atmel_hlcdc_plane {
0275     struct drm_plane base;
0276     struct atmel_hlcdc_layer layer;
0277 };
0278
0279 static inline struct atmel_hlcdc_plane *
0280 drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
0281 {
0282     return container_of(p, struct atmel_hlcdc_plane, base);
0283 }
0284
0285 static inline struct atmel_hlcdc_plane *
0286 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
0287 {
0288     return container_of(layer, struct atmel_hlcdc_plane, layer);
0289 }
0290
0291 /**
0292  * Atmel HLCDC Display Controller description structure.
0293  *
0294  * This structure describes the HLCDC IP capabilities and depends on the
0295  * HLCDC IP version (or Atmel SoC family).
0296  *
0297  * @min_width: minimum width supported by the Display Controller
0298  * @min_height: minimum height supported by the Display Controller
0299  * @max_width: maximum width supported by the Display Controller
0300  * @max_height: maximum height supported by the Display Controller
0301  * @max_spw: maximum vertical/horizontal pulse width
0302  * @max_vpw: maximum vertical back/front porch width
0303  * @max_hpw: maximum horizontal back/front porch width
0304  * @conflicting_output_formats: true if RGBXXX output formats conflict with
0305  *              each other.
0306  * @fixed_clksrc: true if clock source is fixed
0307  * @layers: a layer description table describing available layers
0308  * @nlayers: layer description table size
0309  */
0310 struct atmel_hlcdc_dc_desc {
0311     int min_width;
0312     int min_height;
0313     int max_width;
0314     int max_height;
0315     int max_spw;
0316     int max_vpw;
0317     int max_hpw;
0318     bool conflicting_output_formats;
0319     bool fixed_clksrc;
0320     const struct atmel_hlcdc_layer_desc *layers;
0321     int nlayers;
0322 };
0323
0324 /**
0325  * Atmel HLCDC Display Controller.
0326  *
0327  * @desc: HLCDC Display Controller description
0328  * @dscrpool: DMA coherent pool used to allocate DMA descriptors
0329  * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
0330  * @fbdev: framebuffer device attached to the Display Controller
0331  * @crtc: CRTC provided by the display controller
0332  * @planes: instantiated planes
0333  * @layers: active HLCDC layers
0334  * @suspend: used to store the HLCDC state when entering suspend
0335  */
0336 struct atmel_hlcdc_dc {
0337     const struct atmel_hlcdc_dc_desc *desc;
0338     struct dma_pool *dscrpool;
0339     struct atmel_hlcdc *hlcdc;
0340     struct drm_crtc *crtc;
0341     struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
0342     struct {
0343         u32 imr;
0344         struct drm_atomic_state *state;
0345     } suspend;
0346 };
0347
0348 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
0349 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
0350
0351 static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
0352                            unsigned int reg, u32 val)
0353 {
0354     regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
0355 }
0356
0357 static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
0358                          unsigned int reg)
0359 {
0360     u32 val;
0361
0362     regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);
0363
0364     return val;
0365 }
0366
0367 static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
0368                            unsigned int cfgid, u32 val)
0369 {
0370     atmel_hlcdc_layer_write_reg(layer,
0371                     layer->desc->cfgs_offset +
0372                     (cfgid * sizeof(u32)), val);
0373 }
0374
0375 static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
0376                          unsigned int cfgid)
0377 {
0378     return atmel_hlcdc_layer_read_reg(layer,
0379                       layer->desc->cfgs_offset +
0380                       (cfgid * sizeof(u32)));
0381 }
0382
0383 static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer,
0384                         unsigned int c, u32 val)
0385 {
0386     regmap_write(layer->regmap,
0387              layer->desc->clut_offset + c * sizeof(u32),
0388              val);
0389 }
0390
0391 static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
0392                 const struct atmel_hlcdc_layer_desc *desc,
0393                 struct regmap *regmap)
0394 {
0395     layer->desc = desc;
0396     layer->regmap = regmap;
0397 }
0398
0399 enum drm_mode_status
0400 atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
0401               const struct drm_display_mode *mode);
0402
0403 int atmel_hlcdc_create_planes(struct drm_device *dev);
0404 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
0405
0406 int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
0407 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
0408
0409 void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
0410
0411 int atmel_hlcdc_crtc_create(struct drm_device *dev);
0412
0413 int atmel_hlcdc_create_outputs(struct drm_device *dev);
0414 int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder);
0415
0416 #endif /* DRM_ATMEL_HLCDC_H */