drm/ast/ast_main.c

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the
0006  * "Software"), to deal in the Software without restriction, including
0007  * without limitation the rights to use, copy, modify, merge, publish,
0008  * distribute, sub license, and/or sell copies of the Software, and to
0009  * permit persons to whom the Software is furnished to do so, subject to
0010  * the following conditions:
0011  *
0012  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0013  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0014  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0015  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0016  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0017  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0018  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0019  *
0020  * The above copyright notice and this permission notice (including the
0021  * next paragraph) shall be included in all copies or substantial portions
0022  * of the Software.
0023  *
0024  */
0025 /*
0026  * Authors: Dave Airlie <airlied@redhat.com>
0027  */
0028
0029 #include <linux/pci.h>
0030
0031 #include <drm/drm_atomic_helper.h>
0032 #include <drm/drm_crtc_helper.h>
0033 #include <drm/drm_drv.h>
0034 #include <drm/drm_gem.h>
0035 #include <drm/drm_gem_vram_helper.h>
0036 #include <drm/drm_managed.h>
0037
0038 #include "ast_drv.h"
0039
0040 void ast_set_index_reg_mask(struct ast_private *ast,
0041                 uint32_t base, uint8_t index,
0042                 uint8_t mask, uint8_t val)
0043 {
0044     u8 tmp;
0045     ast_io_write8(ast, base, index);
0046     tmp = (ast_io_read8(ast, base + 1) & mask) | val;
0047     ast_set_index_reg(ast, base, index, tmp);
0048 }
0049
0050 uint8_t ast_get_index_reg(struct ast_private *ast,
0051               uint32_t base, uint8_t index)
0052 {
0053     uint8_t ret;
0054     ast_io_write8(ast, base, index);
0055     ret = ast_io_read8(ast, base + 1);
0056     return ret;
0057 }
0058
0059 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
0060                    uint32_t base, uint8_t index, uint8_t mask)
0061 {
0062     uint8_t ret;
0063     ast_io_write8(ast, base, index);
0064     ret = ast_io_read8(ast, base + 1) & mask;
0065     return ret;
0066 }
0067
0068 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
0069 {
0070     struct device_node *np = dev->dev->of_node;
0071     struct ast_private *ast = to_ast_private(dev);
0072     struct pci_dev *pdev = to_pci_dev(dev->dev);
0073     uint32_t data, jregd0, jregd1;
0074
0075     /* Defaults */
0076     ast->config_mode = ast_use_defaults;
0077     *scu_rev = 0xffffffff;
0078
0079     /* Check if we have device-tree properties */
0080     if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
0081                     scu_rev)) {
0082         /* We do, disable P2A access */
0083         ast->config_mode = ast_use_dt;
0084         drm_info(dev, "Using device-tree for configuration\n");
0085         return;
0086     }
0087
0088     /* Not all families have a P2A bridge */
0089     if (pdev->device != PCI_CHIP_AST2000)
0090         return;
0091
0092     /*
0093      * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
0094      * is disabled. We force using P2A if VGA only mode bit
0095      * is set D[7]
0096      */
0097     jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
0098     jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
0099     if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
0100         /* Patch AST2500 */
0101         if (((pdev->revision & 0xF0) == 0x40)
0102             && ((jregd0 & AST_VRAM_INIT_STATUS_MASK) == 0))
0103             ast_patch_ahb_2500(ast);
0104
0105         /* Double check it's actually working */
0106         data = ast_read32(ast, 0xf004);
0107         if ((data != 0xFFFFFFFF) && (data != 0x00)) {
0108             /* P2A works, grab silicon revision */
0109             ast->config_mode = ast_use_p2a;
0110
0111             drm_info(dev, "Using P2A bridge for configuration\n");
0112
0113             /* Read SCU7c (silicon revision register) */
0114             ast_write32(ast, 0xf004, 0x1e6e0000);
0115             ast_write32(ast, 0xf000, 0x1);
0116             *scu_rev = ast_read32(ast, 0x1207c);
0117             return;
0118         }
0119     }
0120
0121     /* We have a P2A bridge but it's disabled */
0122     drm_info(dev, "P2A bridge disabled, using default configuration\n");
0123 }
0124
0125 static int ast_detect_chip(struct drm_device *dev, bool *need_post)
0126 {
0127     struct ast_private *ast = to_ast_private(dev);
0128     struct pci_dev *pdev = to_pci_dev(dev->dev);
0129     uint32_t jreg, scu_rev;
0130
0131     /*
0132      * If VGA isn't enabled, we need to enable now or subsequent
0133      * access to the scratch registers will fail. We also inform
0134      * our caller that it needs to POST the chip
0135      * (Assumption: VGA not enabled -> need to POST)
0136      */
0137     if (!ast_is_vga_enabled(dev)) {
0138         ast_enable_vga(dev);
0139         drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
0140         *need_post = true;
0141     } else
0142         *need_post = false;
0143
0144
0145     /* Enable extended register access */
0146     ast_open_key(ast);
0147     ast_enable_mmio(dev);
0148
0149     /* Find out whether P2A works or whether to use device-tree */
0150     ast_detect_config_mode(dev, &scu_rev);
0151
0152     /* Identify chipset */
0153     if (pdev->revision >= 0x50) {
0154         ast->chip = AST2600;
0155         drm_info(dev, "AST 2600 detected\n");
0156     } else if (pdev->revision >= 0x40) {
0157         ast->chip = AST2500;
0158         drm_info(dev, "AST 2500 detected\n");
0159     } else if (pdev->revision >= 0x30) {
0160         ast->chip = AST2400;
0161         drm_info(dev, "AST 2400 detected\n");
0162     } else if (pdev->revision >= 0x20) {
0163         ast->chip = AST2300;
0164         drm_info(dev, "AST 2300 detected\n");
0165     } else if (pdev->revision >= 0x10) {
0166         switch (scu_rev & 0x0300) {
0167         case 0x0200:
0168             ast->chip = AST1100;
0169             drm_info(dev, "AST 1100 detected\n");
0170             break;
0171         case 0x0100:
0172             ast->chip = AST2200;
0173             drm_info(dev, "AST 2200 detected\n");
0174             break;
0175         case 0x0000:
0176             ast->chip = AST2150;
0177             drm_info(dev, "AST 2150 detected\n");
0178             break;
0179         default:
0180             ast->chip = AST2100;
0181             drm_info(dev, "AST 2100 detected\n");
0182             break;
0183         }
0184         ast->vga2_clone = false;
0185     } else {
0186         ast->chip = AST2000;
0187         drm_info(dev, "AST 2000 detected\n");
0188     }
0189
0190     /* Check if we support wide screen */
0191     switch (ast->chip) {
0192     case AST2000:
0193         ast->support_wide_screen = false;
0194         break;
0195     default:
0196         jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
0197         if (!(jreg & 0x80))
0198             ast->support_wide_screen = true;
0199         else if (jreg & 0x01)
0200             ast->support_wide_screen = true;
0201         else {
0202             ast->support_wide_screen = false;
0203             if (ast->chip == AST2300 &&
0204                 (scu_rev & 0x300) == 0x0) /* ast1300 */
0205                 ast->support_wide_screen = true;
0206             if (ast->chip == AST2400 &&
0207                 (scu_rev & 0x300) == 0x100) /* ast1400 */
0208                 ast->support_wide_screen = true;
0209             if (ast->chip == AST2500 &&
0210                 scu_rev == 0x100)           /* ast2510 */
0211                 ast->support_wide_screen = true;
0212             if (ast->chip == AST2600)       /* ast2600 */
0213                 ast->support_wide_screen = true;
0214         }
0215         break;
0216     }
0217
0218     /* Check 3rd Tx option (digital output afaik) */
0219     ast->tx_chip_types |= AST_TX_NONE_BIT;
0220
0221     /*
0222      * VGACRA3 Enhanced Color Mode Register, check if DVO is already
0223      * enabled, in that case, assume we have a SIL164 TMDS transmitter
0224      *
0225      * Don't make that assumption if we the chip wasn't enabled and
0226      * is at power-on reset, otherwise we'll incorrectly "detect" a
0227      * SIL164 when there is none.
0228      */
0229     if (!*need_post) {
0230         jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
0231         if (jreg & 0x80)
0232             ast->tx_chip_types = AST_TX_SIL164_BIT;
0233     }
0234
0235     if ((ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST2500)) {
0236         /*
0237          * On AST2300 and 2400, look the configuration set by the SoC in
0238          * the SOC scratch register #1 bits 11:8 (interestingly marked
0239          * as "reserved" in the spec)
0240          */
0241         jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
0242         switch (jreg) {
0243         case 0x04:
0244             ast->tx_chip_types = AST_TX_SIL164_BIT;
0245             break;
0246         case 0x08:
0247             ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
0248             if (ast->dp501_fw_addr) {
0249                 /* backup firmware */
0250                 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
0251                     drmm_kfree(dev, ast->dp501_fw_addr);
0252                     ast->dp501_fw_addr = NULL;
0253                 }
0254             }
0255             fallthrough;
0256         case 0x0c:
0257             ast->tx_chip_types = AST_TX_DP501_BIT;
0258         }
0259     } else if (ast->chip == AST2600)
0260         ast_dp_launch(&ast->base, 0);
0261
0262     /* Print stuff for diagnostic purposes */
0263     if (ast->tx_chip_types & AST_TX_NONE_BIT)
0264         drm_info(dev, "Using analog VGA\n");
0265     if (ast->tx_chip_types & AST_TX_SIL164_BIT)
0266         drm_info(dev, "Using Sil164 TMDS transmitter\n");
0267     if (ast->tx_chip_types & AST_TX_DP501_BIT)
0268         drm_info(dev, "Using DP501 DisplayPort transmitter\n");
0269
0270     return 0;
0271 }
0272
0273 static int ast_get_dram_info(struct drm_device *dev)
0274 {
0275     struct device_node *np = dev->dev->of_node;
0276     struct ast_private *ast = to_ast_private(dev);
0277     uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
0278     uint32_t denum, num, div, ref_pll, dsel;
0279
0280     switch (ast->config_mode) {
0281     case ast_use_dt:
0282         /*
0283          * If some properties are missing, use reasonable
0284          * defaults for AST2400
0285          */
0286         if (of_property_read_u32(np, "aspeed,mcr-configuration",
0287                      &mcr_cfg))
0288             mcr_cfg = 0x00000577;
0289         if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
0290                      &mcr_scu_mpll))
0291             mcr_scu_mpll = 0x000050C0;
0292         if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
0293                      &mcr_scu_strap))
0294             mcr_scu_strap = 0;
0295         break;
0296     case ast_use_p2a:
0297         ast_write32(ast, 0xf004, 0x1e6e0000);
0298         ast_write32(ast, 0xf000, 0x1);
0299         mcr_cfg = ast_read32(ast, 0x10004);
0300         mcr_scu_mpll = ast_read32(ast, 0x10120);
0301         mcr_scu_strap = ast_read32(ast, 0x10170);
0302         break;
0303     case ast_use_defaults:
0304     default:
0305         ast->dram_bus_width = 16;
0306         ast->dram_type = AST_DRAM_1Gx16;
0307         if (ast->chip == AST2500)
0308             ast->mclk = 800;
0309         else
0310             ast->mclk = 396;
0311         return 0;
0312     }
0313
0314     if (mcr_cfg & 0x40)
0315         ast->dram_bus_width = 16;
0316     else
0317         ast->dram_bus_width = 32;
0318
0319     if (ast->chip == AST2500) {
0320         switch (mcr_cfg & 0x03) {
0321         case 0:
0322             ast->dram_type = AST_DRAM_1Gx16;
0323             break;
0324         default:
0325         case 1:
0326             ast->dram_type = AST_DRAM_2Gx16;
0327             break;
0328         case 2:
0329             ast->dram_type = AST_DRAM_4Gx16;
0330             break;
0331         case 3:
0332             ast->dram_type = AST_DRAM_8Gx16;
0333             break;
0334         }
0335     } else if (ast->chip == AST2300 || ast->chip == AST2400) {
0336         switch (mcr_cfg & 0x03) {
0337         case 0:
0338             ast->dram_type = AST_DRAM_512Mx16;
0339             break;
0340         default:
0341         case 1:
0342             ast->dram_type = AST_DRAM_1Gx16;
0343             break;
0344         case 2:
0345             ast->dram_type = AST_DRAM_2Gx16;
0346             break;
0347         case 3:
0348             ast->dram_type = AST_DRAM_4Gx16;
0349             break;
0350         }
0351     } else {
0352         switch (mcr_cfg & 0x0c) {
0353         case 0:
0354         case 4:
0355             ast->dram_type = AST_DRAM_512Mx16;
0356             break;
0357         case 8:
0358             if (mcr_cfg & 0x40)
0359                 ast->dram_type = AST_DRAM_1Gx16;
0360             else
0361                 ast->dram_type = AST_DRAM_512Mx32;
0362             break;
0363         case 0xc:
0364             ast->dram_type = AST_DRAM_1Gx32;
0365             break;
0366         }
0367     }
0368
0369     if (mcr_scu_strap & 0x2000)
0370         ref_pll = 14318;
0371     else
0372         ref_pll = 12000;
0373
0374     denum = mcr_scu_mpll & 0x1f;
0375     num = (mcr_scu_mpll & 0x3fe0) >> 5;
0376     dsel = (mcr_scu_mpll & 0xc000) >> 14;
0377     switch (dsel) {
0378     case 3:
0379         div = 0x4;
0380         break;
0381     case 2:
0382     case 1:
0383         div = 0x2;
0384         break;
0385     default:
0386         div = 0x1;
0387         break;
0388     }
0389     ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
0390     return 0;
0391 }
0392
0393 /*
0394  * Run this function as part of the HW device cleanup; not
0395  * when the DRM device gets released.
0396  */
0397 static void ast_device_release(void *data)
0398 {
0399     struct ast_private *ast = data;
0400
0401     /* enable standard VGA decode */
0402     ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
0403 }
0404
0405 struct ast_private *ast_device_create(const struct drm_driver *drv,
0406                       struct pci_dev *pdev,
0407                       unsigned long flags)
0408 {
0409     struct drm_device *dev;
0410     struct ast_private *ast;
0411     bool need_post;
0412     int ret = 0;
0413
0414     ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base);
0415     if (IS_ERR(ast))
0416         return ast;
0417     dev = &ast->base;
0418
0419     pci_set_drvdata(pdev, dev);
0420
0421     ret = drmm_mutex_init(dev, &ast->ioregs_lock);
0422     if (ret)
0423         return ERR_PTR(ret);
0424
0425     ast->regs = pcim_iomap(pdev, 1, 0);
0426     if (!ast->regs)
0427         return ERR_PTR(-EIO);
0428
0429     /*
0430      * If we don't have IO space at all, use MMIO now and
0431      * assume the chip has MMIO enabled by default (rev 0x20
0432      * and higher).
0433      */
0434     if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
0435         drm_info(dev, "platform has no IO space, trying MMIO\n");
0436         ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
0437     }
0438
0439     /* "map" IO regs if the above hasn't done so already */
0440     if (!ast->ioregs) {
0441         ast->ioregs = pcim_iomap(pdev, 2, 0);
0442         if (!ast->ioregs)
0443             return ERR_PTR(-EIO);
0444     }
0445
0446     ast_detect_chip(dev, &need_post);
0447
0448     ret = ast_get_dram_info(dev);
0449     if (ret)
0450         return ERR_PTR(ret);
0451
0452     drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
0453          ast->mclk, ast->dram_type, ast->dram_bus_width);
0454
0455     if (need_post)
0456         ast_post_gpu(dev);
0457
0458     ret = ast_mm_init(ast);
0459     if (ret)
0460         return ERR_PTR(ret);
0461
0462     /* map reserved buffer */
0463     ast->dp501_fw_buf = NULL;
0464     if (dev->vram_mm->vram_size < pci_resource_len(pdev, 0)) {
0465         ast->dp501_fw_buf = pci_iomap_range(pdev, 0, dev->vram_mm->vram_size, 0);
0466         if (!ast->dp501_fw_buf)
0467             drm_info(dev, "failed to map reserved buffer!\n");
0468     }
0469
0470     ret = ast_mode_config_init(ast);
0471     if (ret)
0472         return ERR_PTR(ret);
0473
0474     ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
0475     if (ret)
0476         return ERR_PTR(ret);
0477
0478     return ast;
0479 }