drm/ast/ast_drv.h

0001 /*
0002  * Copyright 2012 Red Hat Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the
0006  * "Software"), to deal in the Software without restriction, including
0007  * without limitation the rights to use, copy, modify, merge, publish,
0008  * distribute, sub license, and/or sell copies of the Software, and to
0009  * permit persons to whom the Software is furnished to do so, subject to
0010  * the following conditions:
0011  *
0012  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0013  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0014  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0015  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0016  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0017  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0018  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0019  *
0020  * The above copyright notice and this permission notice (including the
0021  * next paragraph) shall be included in all copies or substantial portions
0022  * of the Software.
0023  *
0024  */
0025 /*
0026  * Authors: Dave Airlie <airlied@redhat.com>
0027  */
0028 #ifndef __AST_DRV_H__
0029 #define __AST_DRV_H__
0030
0031 #include <linux/i2c.h>
0032 #include <linux/i2c-algo-bit.h>
0033 #include <linux/io.h>
0034 #include <linux/types.h>
0035
0036 #include <drm/drm_connector.h>
0037 #include <drm/drm_crtc.h>
0038 #include <drm/drm_encoder.h>
0039 #include <drm/drm_mode.h>
0040 #include <drm/drm_framebuffer.h>
0041 #include <drm/drm_fb_helper.h>
0042
0043 #define DRIVER_AUTHOR       "Dave Airlie"
0044
0045 #define DRIVER_NAME     "ast"
0046 #define DRIVER_DESC     "AST"
0047 #define DRIVER_DATE     "20120228"
0048
0049 #define DRIVER_MAJOR        0
0050 #define DRIVER_MINOR        1
0051 #define DRIVER_PATCHLEVEL   0
0052
0053 #define PCI_CHIP_AST2000 0x2000
0054 #define PCI_CHIP_AST2100 0x2010
0055
0056
0057 enum ast_chip {
0058     AST2000,
0059     AST2100,
0060     AST1100,
0061     AST2200,
0062     AST2150,
0063     AST2300,
0064     AST2400,
0065     AST2500,
0066     AST2600,
0067 };
0068
0069 enum ast_tx_chip {
0070     AST_TX_NONE,
0071     AST_TX_SIL164,
0072     AST_TX_DP501,
0073     AST_TX_ASTDP,
0074 };
0075
0076 #define AST_TX_NONE_BIT     BIT(AST_TX_NONE)
0077 #define AST_TX_SIL164_BIT   BIT(AST_TX_SIL164)
0078 #define AST_TX_DP501_BIT    BIT(AST_TX_DP501)
0079 #define AST_TX_ASTDP_BIT    BIT(AST_TX_ASTDP)
0080
0081 #define AST_DRAM_512Mx16 0
0082 #define AST_DRAM_1Gx16   1
0083 #define AST_DRAM_512Mx32 2
0084 #define AST_DRAM_1Gx32   3
0085 #define AST_DRAM_2Gx16   6
0086 #define AST_DRAM_4Gx16   7
0087 #define AST_DRAM_8Gx16   8
0088
0089 /*
0090  * Cursor plane
0091  */
0092
0093 #define AST_MAX_HWC_WIDTH   64
0094 #define AST_MAX_HWC_HEIGHT  64
0095
0096 #define AST_HWC_SIZE        (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
0097 #define AST_HWC_SIGNATURE_SIZE  32
0098
0099 #define AST_DEFAULT_HWC_NUM 2
0100
0101 /* define for signature structure */
0102 #define AST_HWC_SIGNATURE_CHECKSUM  0x00
0103 #define AST_HWC_SIGNATURE_SizeX     0x04
0104 #define AST_HWC_SIGNATURE_SizeY     0x08
0105 #define AST_HWC_SIGNATURE_X     0x0C
0106 #define AST_HWC_SIGNATURE_Y     0x10
0107 #define AST_HWC_SIGNATURE_HOTSPOTX  0x14
0108 #define AST_HWC_SIGNATURE_HOTSPOTY  0x18
0109
0110 struct ast_cursor_plane {
0111     struct drm_plane base;
0112
0113     struct {
0114         struct drm_gem_vram_object *gbo;
0115         struct iosys_map map;
0116         u64 off;
0117     } hwc[AST_DEFAULT_HWC_NUM];
0118
0119     unsigned int next_hwc_index;
0120 };
0121
0122 static inline struct ast_cursor_plane *
0123 to_ast_cursor_plane(struct drm_plane *plane)
0124 {
0125     return container_of(plane, struct ast_cursor_plane, base);
0126 }
0127
0128 /*
0129  * Connector with i2c channel
0130  */
0131
0132 struct ast_i2c_chan {
0133     struct i2c_adapter adapter;
0134     struct drm_device *dev;
0135     struct i2c_algo_bit_data bit;
0136 };
0137
0138 struct ast_vga_connector {
0139     struct drm_connector base;
0140     struct ast_i2c_chan *i2c;
0141 };
0142
0143 static inline struct ast_vga_connector *
0144 to_ast_vga_connector(struct drm_connector *connector)
0145 {
0146     return container_of(connector, struct ast_vga_connector, base);
0147 }
0148
0149 struct ast_sil164_connector {
0150     struct drm_connector base;
0151     struct ast_i2c_chan *i2c;
0152 };
0153
0154 static inline struct ast_sil164_connector *
0155 to_ast_sil164_connector(struct drm_connector *connector)
0156 {
0157     return container_of(connector, struct ast_sil164_connector, base);
0158 }
0159
0160 /*
0161  * Device
0162  */
0163
0164 struct ast_private {
0165     struct drm_device base;
0166
0167     struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */
0168     void __iomem *regs;
0169     void __iomem *ioregs;
0170     void __iomem *dp501_fw_buf;
0171
0172     enum ast_chip chip;
0173     bool vga2_clone;
0174     uint32_t dram_bus_width;
0175     uint32_t dram_type;
0176     uint32_t mclk;
0177
0178     struct drm_plane primary_plane;
0179     struct ast_cursor_plane cursor_plane;
0180     struct drm_crtc crtc;
0181     struct {
0182         struct {
0183             struct drm_encoder encoder;
0184             struct ast_vga_connector vga_connector;
0185         } vga;
0186         struct {
0187             struct drm_encoder encoder;
0188             struct ast_sil164_connector sil164_connector;
0189         } sil164;
0190         struct {
0191             struct drm_encoder encoder;
0192             struct drm_connector connector;
0193         } dp501;
0194         struct {
0195             struct drm_encoder encoder;
0196             struct drm_connector connector;
0197         } astdp;
0198     } output;
0199
0200     bool support_wide_screen;
0201     enum {
0202         ast_use_p2a,
0203         ast_use_dt,
0204         ast_use_defaults
0205     } config_mode;
0206
0207     unsigned long tx_chip_types;        /* bitfield of enum ast_chip_type */
0208     u8 *dp501_fw_addr;
0209     const struct firmware *dp501_fw;    /* dp501 fw */
0210 };
0211
0212 static inline struct ast_private *to_ast_private(struct drm_device *dev)
0213 {
0214     return container_of(dev, struct ast_private, base);
0215 }
0216
0217 struct ast_private *ast_device_create(const struct drm_driver *drv,
0218                       struct pci_dev *pdev,
0219                       unsigned long flags);
0220
0221 #define AST_IO_AR_PORT_WRITE        (0x40)
0222 #define AST_IO_MISC_PORT_WRITE      (0x42)
0223 #define AST_IO_VGA_ENABLE_PORT      (0x43)
0224 #define AST_IO_SEQ_PORT         (0x44)
0225 #define AST_IO_DAC_INDEX_READ       (0x47)
0226 #define AST_IO_DAC_INDEX_WRITE      (0x48)
0227 #define AST_IO_DAC_DATA             (0x49)
0228 #define AST_IO_GR_PORT          (0x4E)
0229 #define AST_IO_CRTC_PORT        (0x54)
0230 #define AST_IO_INPUT_STATUS1_READ   (0x5A)
0231 #define AST_IO_MISC_PORT_READ       (0x4C)
0232
0233 #define AST_IO_MM_OFFSET        (0x380)
0234
0235 #define AST_IO_VGAIR1_VREFRESH      BIT(3)
0236
0237 #define AST_IO_VGACRCB_HWC_ENABLED     BIT(1)
0238 #define AST_IO_VGACRCB_HWC_16BPP       BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
0239
0240 #define __ast_read(x) \
0241 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
0242 u##x val = 0;\
0243 val = ioread##x(ast->regs + reg); \
0244 return val;\
0245 }
0246
0247 __ast_read(8);
0248 __ast_read(16);
0249 __ast_read(32)
0250
0251 #define __ast_io_read(x) \
0252 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
0253 u##x val = 0;\
0254 val = ioread##x(ast->ioregs + reg); \
0255 return val;\
0256 }
0257
0258 __ast_io_read(8);
0259 __ast_io_read(16);
0260 __ast_io_read(32);
0261
0262 #define __ast_write(x) \
0263 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
0264     iowrite##x(val, ast->regs + reg);\
0265     }
0266
0267 __ast_write(8);
0268 __ast_write(16);
0269 __ast_write(32);
0270
0271 #define __ast_io_write(x) \
0272 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
0273     iowrite##x(val, ast->ioregs + reg);\
0274     }
0275
0276 __ast_io_write(8);
0277 __ast_io_write(16);
0278 #undef __ast_io_write
0279
0280 static inline void ast_set_index_reg(struct ast_private *ast,
0281                      uint32_t base, uint8_t index,
0282                      uint8_t val)
0283 {
0284     ast_io_write16(ast, base, ((u16)val << 8) | index);
0285 }
0286
0287 void ast_set_index_reg_mask(struct ast_private *ast,
0288                 uint32_t base, uint8_t index,
0289                 uint8_t mask, uint8_t val);
0290 uint8_t ast_get_index_reg(struct ast_private *ast,
0291               uint32_t base, uint8_t index);
0292 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
0293                    uint32_t base, uint8_t index, uint8_t mask);
0294
0295 static inline void ast_open_key(struct ast_private *ast)
0296 {
0297     ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
0298 }
0299
0300 #define AST_VIDMEM_SIZE_8M    0x00800000
0301 #define AST_VIDMEM_SIZE_16M   0x01000000
0302 #define AST_VIDMEM_SIZE_32M   0x02000000
0303 #define AST_VIDMEM_SIZE_64M   0x04000000
0304 #define AST_VIDMEM_SIZE_128M  0x08000000
0305
0306 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
0307
0308 struct ast_vbios_stdtable {
0309     u8 misc;
0310     u8 seq[4];
0311     u8 crtc[25];
0312     u8 ar[20];
0313     u8 gr[9];
0314 };
0315
0316 struct ast_vbios_enhtable {
0317     u32 ht;
0318     u32 hde;
0319     u32 hfp;
0320     u32 hsync;
0321     u32 vt;
0322     u32 vde;
0323     u32 vfp;
0324     u32 vsync;
0325     u32 dclk_index;
0326     u32 flags;
0327     u32 refresh_rate;
0328     u32 refresh_rate_index;
0329     u32 mode_id;
0330 };
0331
0332 struct ast_vbios_dclk_info {
0333     u8 param1;
0334     u8 param2;
0335     u8 param3;
0336 };
0337
0338 struct ast_vbios_mode_info {
0339     const struct ast_vbios_stdtable *std_table;
0340     const struct ast_vbios_enhtable *enh_table;
0341 };
0342
0343 struct ast_crtc_state {
0344     struct drm_crtc_state base;
0345
0346     /* Last known format of primary plane */
0347     const struct drm_format_info *format;
0348
0349     struct ast_vbios_mode_info vbios_mode_info;
0350 };
0351
0352 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
0353
0354 int ast_mode_config_init(struct ast_private *ast);
0355
0356 #define AST_MM_ALIGN_SHIFT 4
0357 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
0358
0359 #define AST_DP501_FW_VERSION_MASK   GENMASK(7, 4)
0360 #define AST_DP501_FW_VERSION_1      BIT(4)
0361 #define AST_DP501_PNP_CONNECTED     BIT(1)
0362
0363 #define AST_DP501_DEFAULT_DCLK  65
0364
0365 #define AST_DP501_GBL_VERSION   0xf000
0366 #define AST_DP501_PNPMONITOR    0xf010
0367 #define AST_DP501_LINKRATE  0xf014
0368 #define AST_DP501_EDID_DATA 0xf020
0369
0370 /* Define for Soc scratched reg */
0371 #define COPROCESSOR_LAUNCH          BIT(5)
0372
0373 /*
0374  * Display Transmitter Type:
0375  */
0376 #define TX_TYPE_MASK                GENMASK(3, 1)
0377 #define NO_TX                       (0 << 1)
0378 #define ITE66121_VBIOS_TX           (1 << 1)
0379 #define SI164_VBIOS_TX              (2 << 1)
0380 #define CH7003_VBIOS_TX         (3 << 1)
0381 #define DP501_VBIOS_TX              (4 << 1)
0382 #define ANX9807_VBIOS_TX            (5 << 1)
0383 #define TX_FW_EMBEDDED_FW_TX        (6 << 1)
0384 #define ASTDP_DPMCU_TX              (7 << 1)
0385
0386 #define AST_VRAM_INIT_STATUS_MASK   GENMASK(7, 6)
0387 //#define AST_VRAM_INIT_BY_BMC      BIT(7)
0388 //#define AST_VRAM_INIT_READY       BIT(6)
0389
0390 /* Define for Soc scratched reg used on ASTDP */
0391 #define AST_DP_PHY_SLEEP            BIT(4)
0392 #define AST_DP_VIDEO_ENABLE     BIT(0)
0393
0394 #define AST_DP_POWER_ON         true
0395 #define AST_DP_POWER_OFF            false
0396
0397 /*
0398  * CRD1[b5]: DP MCU FW is executing
0399  * CRDC[b0]: DP link success
0400  * CRDF[b0]: DP HPD
0401  * CRE5[b0]: Host reading EDID process is done
0402  */
0403 #define ASTDP_MCU_FW_EXECUTING          BIT(5)
0404 #define ASTDP_LINK_SUCCESS              BIT(0)
0405 #define ASTDP_HPD                       BIT(0)
0406 #define ASTDP_HOST_EDID_READ_DONE       BIT(0)
0407 #define ASTDP_HOST_EDID_READ_DONE_MASK  GENMASK(0, 0)
0408
0409 /*
0410  * CRB8[b1]: Enable VSYNC off
0411  * CRB8[b0]: Enable HSYNC off
0412  */
0413 #define AST_DPMS_VSYNC_OFF              BIT(1)
0414 #define AST_DPMS_HSYNC_OFF              BIT(0)
0415
0416 /*
0417  * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
0418  * Precondition:    A. ~AST_DP_PHY_SLEEP  &&
0419  *          B. DP_HPD &&
0420  *          C. DP_LINK_SUCCESS
0421  */
0422 #define ASTDP_MIRROR_VIDEO_ENABLE       BIT(4)
0423
0424 #define ASTDP_EDID_READ_POINTER_MASK    GENMASK(7, 0)
0425 #define ASTDP_EDID_VALID_FLAG_MASK      GENMASK(0, 0)
0426 #define ASTDP_EDID_READ_DATA_MASK       GENMASK(7, 0)
0427
0428 /*
0429  * ASTDP setmode registers:
0430  * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
0431  * CRE1[7:0]: MISC1 (default: 0x00)
0432  * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
0433  */
0434 #define ASTDP_MISC0_24bpp           BIT(5)
0435 #define ASTDP_MISC1             0
0436 #define ASTDP_AND_CLEAR_MASK        0x00
0437
0438 /*
0439  * ASTDP resoultion table:
0440  * EX:  ASTDP_A_B_C:
0441  *      A: Resolution
0442  *      B: Refresh Rate
0443  *      C: Misc information, such as CVT, Reduce Blanked
0444  */
0445 #define ASTDP_640x480_60        0x00
0446 #define ASTDP_640x480_72        0x01
0447 #define ASTDP_640x480_75        0x02
0448 #define ASTDP_640x480_85        0x03
0449 #define ASTDP_800x600_56        0x04
0450 #define ASTDP_800x600_60        0x05
0451 #define ASTDP_800x600_72        0x06
0452 #define ASTDP_800x600_75        0x07
0453 #define ASTDP_800x600_85        0x08
0454 #define ASTDP_1024x768_60       0x09
0455 #define ASTDP_1024x768_70       0x0A
0456 #define ASTDP_1024x768_75       0x0B
0457 #define ASTDP_1024x768_85       0x0C
0458 #define ASTDP_1280x1024_60      0x0D
0459 #define ASTDP_1280x1024_75      0x0E
0460 #define ASTDP_1280x1024_85      0x0F
0461 #define ASTDP_1600x1200_60      0x10
0462 #define ASTDP_320x240_60        0x11
0463 #define ASTDP_400x300_60        0x12
0464 #define ASTDP_512x384_60        0x13
0465 #define ASTDP_1920x1200_60      0x14
0466 #define ASTDP_1920x1080_60      0x15
0467 #define ASTDP_1280x800_60       0x16
0468 #define ASTDP_1280x800_60_RB    0x17
0469 #define ASTDP_1440x900_60       0x18
0470 #define ASTDP_1440x900_60_RB    0x19
0471 #define ASTDP_1680x1050_60      0x1A
0472 #define ASTDP_1680x1050_60_RB   0x1B
0473 #define ASTDP_1600x900_60       0x1C
0474 #define ASTDP_1600x900_60_RB    0x1D
0475 #define ASTDP_1366x768_60       0x1E
0476 #define ASTDP_1152x864_75       0x1F
0477
0478 int ast_mm_init(struct ast_private *ast);
0479
0480 /* ast post */
0481 void ast_enable_vga(struct drm_device *dev);
0482 void ast_enable_mmio(struct drm_device *dev);
0483 bool ast_is_vga_enabled(struct drm_device *dev);
0484 void ast_post_gpu(struct drm_device *dev);
0485 u32 ast_mindwm(struct ast_private *ast, u32 r);
0486 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
0487 void ast_patch_ahb_2500(struct ast_private *ast);
0488 /* ast dp501 */
0489 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
0490 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
0491 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
0492 u8 ast_get_dp501_max_clk(struct drm_device *dev);
0493 void ast_init_3rdtx(struct drm_device *dev);
0494
0495 /* ast_i2c.c */
0496 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
0497
0498 /* aspeed DP */
0499 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata);
0500 void ast_dp_launch(struct drm_device *dev, u8 bPower);
0501 void ast_dp_power_on_off(struct drm_device *dev, bool no);
0502 void ast_dp_set_on_off(struct drm_device *dev, bool no);
0503 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode);
0504
0505 #endif