drm/ast/ast_dram_tables.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef AST_DRAM_TABLES_H
0003 #define AST_DRAM_TABLES_H
0004
0005 /* DRAM timing tables */
0006 struct ast_dramstruct {
0007     u16 index;
0008     u32 data;
0009 };
0010
0011 static const struct ast_dramstruct ast2000_dram_table_data[] = {
0012     { 0x0108, 0x00000000 },
0013     { 0x0120, 0x00004a21 },
0014     { 0xFF00, 0x00000043 },
0015     { 0x0000, 0xFFFFFFFF },
0016     { 0x0004, 0x00000089 },
0017     { 0x0008, 0x22331353 },
0018     { 0x000C, 0x0d07000b },
0019     { 0x0010, 0x11113333 },
0020     { 0x0020, 0x00110350 },
0021     { 0x0028, 0x1e0828f0 },
0022     { 0x0024, 0x00000001 },
0023     { 0x001C, 0x00000000 },
0024     { 0x0014, 0x00000003 },
0025     { 0xFF00, 0x00000043 },
0026     { 0x0018, 0x00000131 },
0027     { 0x0014, 0x00000001 },
0028     { 0xFF00, 0x00000043 },
0029     { 0x0018, 0x00000031 },
0030     { 0x0014, 0x00000001 },
0031     { 0xFF00, 0x00000043 },
0032     { 0x0028, 0x1e0828f1 },
0033     { 0x0024, 0x00000003 },
0034     { 0x002C, 0x1f0f28fb },
0035     { 0x0030, 0xFFFFFE01 },
0036     { 0xFFFF, 0xFFFFFFFF }
0037 };
0038
0039 static const struct ast_dramstruct ast1100_dram_table_data[] = {
0040     { 0x2000, 0x1688a8a8 },
0041     { 0x2020, 0x000041f0 },
0042     { 0xFF00, 0x00000043 },
0043     { 0x0000, 0xfc600309 },
0044     { 0x006C, 0x00909090 },
0045     { 0x0064, 0x00050000 },
0046     { 0x0004, 0x00000585 },
0047     { 0x0008, 0x0011030f },
0048     { 0x0010, 0x22201724 },
0049     { 0x0018, 0x1e29011a },
0050     { 0x0020, 0x00c82222 },
0051     { 0x0014, 0x01001523 },
0052     { 0x001C, 0x1024010d },
0053     { 0x0024, 0x00cb2522 },
0054     { 0x0038, 0xffffff82 },
0055     { 0x003C, 0x00000000 },
0056     { 0x0040, 0x00000000 },
0057     { 0x0044, 0x00000000 },
0058     { 0x0048, 0x00000000 },
0059     { 0x004C, 0x00000000 },
0060     { 0x0050, 0x00000000 },
0061     { 0x0054, 0x00000000 },
0062     { 0x0058, 0x00000000 },
0063     { 0x005C, 0x00000000 },
0064     { 0x0060, 0x032aa02a },
0065     { 0x0064, 0x002d3000 },
0066     { 0x0068, 0x00000000 },
0067     { 0x0070, 0x00000000 },
0068     { 0x0074, 0x00000000 },
0069     { 0x0078, 0x00000000 },
0070     { 0x007C, 0x00000000 },
0071     { 0x0034, 0x00000001 },
0072     { 0xFF00, 0x00000043 },
0073     { 0x002C, 0x00000732 },
0074     { 0x0030, 0x00000040 },
0075     { 0x0028, 0x00000005 },
0076     { 0x0028, 0x00000007 },
0077     { 0x0028, 0x00000003 },
0078     { 0x0028, 0x00000001 },
0079     { 0x000C, 0x00005a08 },
0080     { 0x002C, 0x00000632 },
0081     { 0x0028, 0x00000001 },
0082     { 0x0030, 0x000003c0 },
0083     { 0x0028, 0x00000003 },
0084     { 0x0030, 0x00000040 },
0085     { 0x0028, 0x00000003 },
0086     { 0x000C, 0x00005a21 },
0087     { 0x0034, 0x00007c03 },
0088     { 0x0120, 0x00004c41 },
0089     { 0xffff, 0xffffffff },
0090 };
0091
0092 static const struct ast_dramstruct ast2100_dram_table_data[] = {
0093     { 0x2000, 0x1688a8a8 },
0094     { 0x2020, 0x00004120 },
0095     { 0xFF00, 0x00000043 },
0096     { 0x0000, 0xfc600309 },
0097     { 0x006C, 0x00909090 },
0098     { 0x0064, 0x00070000 },
0099     { 0x0004, 0x00000489 },
0100     { 0x0008, 0x0011030f },
0101     { 0x0010, 0x32302926 },
0102     { 0x0018, 0x274c0122 },
0103     { 0x0020, 0x00ce2222 },
0104     { 0x0014, 0x01001523 },
0105     { 0x001C, 0x1024010d },
0106     { 0x0024, 0x00cb2522 },
0107     { 0x0038, 0xffffff82 },
0108     { 0x003C, 0x00000000 },
0109     { 0x0040, 0x00000000 },
0110     { 0x0044, 0x00000000 },
0111     { 0x0048, 0x00000000 },
0112     { 0x004C, 0x00000000 },
0113     { 0x0050, 0x00000000 },
0114     { 0x0054, 0x00000000 },
0115     { 0x0058, 0x00000000 },
0116     { 0x005C, 0x00000000 },
0117     { 0x0060, 0x0f2aa02a },
0118     { 0x0064, 0x003f3005 },
0119     { 0x0068, 0x02020202 },
0120     { 0x0070, 0x00000000 },
0121     { 0x0074, 0x00000000 },
0122     { 0x0078, 0x00000000 },
0123     { 0x007C, 0x00000000 },
0124     { 0x0034, 0x00000001 },
0125     { 0xFF00, 0x00000043 },
0126     { 0x002C, 0x00000942 },
0127     { 0x0030, 0x00000040 },
0128     { 0x0028, 0x00000005 },
0129     { 0x0028, 0x00000007 },
0130     { 0x0028, 0x00000003 },
0131     { 0x0028, 0x00000001 },
0132     { 0x000C, 0x00005a08 },
0133     { 0x002C, 0x00000842 },
0134     { 0x0028, 0x00000001 },
0135     { 0x0030, 0x000003c0 },
0136     { 0x0028, 0x00000003 },
0137     { 0x0030, 0x00000040 },
0138     { 0x0028, 0x00000003 },
0139     { 0x000C, 0x00005a21 },
0140     { 0x0034, 0x00007c03 },
0141     { 0x0120, 0x00005061 },
0142     { 0xffff, 0xffffffff },
0143 };
0144
0145 /*
0146  * AST2500 DRAM settings modules
0147  */
0148 #define REGTBL_NUM           17
0149 #define REGIDX_010           0
0150 #define REGIDX_014           1
0151 #define REGIDX_018           2
0152 #define REGIDX_020           3
0153 #define REGIDX_024           4
0154 #define REGIDX_02C           5
0155 #define REGIDX_030           6
0156 #define REGIDX_214           7
0157 #define REGIDX_2E0           8
0158 #define REGIDX_2E4           9
0159 #define REGIDX_2E8           10
0160 #define REGIDX_2EC           11
0161 #define REGIDX_2F0           12
0162 #define REGIDX_2F4           13
0163 #define REGIDX_2F8           14
0164 #define REGIDX_RFC           15
0165 #define REGIDX_PLL           16
0166
0167 static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
0168     0x64604D38,          /* 0x010 */
0169     0x29690599,          /* 0x014 */
0170     0x00000300,          /* 0x018 */
0171     0x00000000,          /* 0x020 */
0172     0x00000000,          /* 0x024 */
0173     0x02181E70,          /* 0x02C */
0174     0x00000040,          /* 0x030 */
0175     0x00000024,          /* 0x214 */
0176     0x02001300,          /* 0x2E0 */
0177     0x0E0000A0,          /* 0x2E4 */
0178     0x000E001B,          /* 0x2E8 */
0179     0x35B8C105,          /* 0x2EC */
0180     0x08090408,          /* 0x2F0 */
0181     0x9B000800,          /* 0x2F4 */
0182     0x0E400A00,          /* 0x2F8 */
0183     0x9971452F,          /* tRFC  */
0184     0x000071C1           /* PLL   */
0185 };
0186
0187 static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
0188     0x63604E37,          /* 0x010 */
0189     0xE97AFA99,          /* 0x014 */
0190     0x00019000,          /* 0x018 */
0191     0x08000000,          /* 0x020 */
0192     0x00000400,          /* 0x024 */
0193     0x00000410,          /* 0x02C */
0194     0x00000101,          /* 0x030 */
0195     0x00000024,          /* 0x214 */
0196     0x03002900,          /* 0x2E0 */
0197     0x0E0000A0,          /* 0x2E4 */
0198     0x000E001C,          /* 0x2E8 */
0199     0x35B8C106,          /* 0x2EC */
0200     0x08080607,          /* 0x2F0 */
0201     0x9B000900,          /* 0x2F4 */
0202     0x0E400A00,          /* 0x2F8 */
0203     0x99714545,          /* tRFC  */
0204     0x000071C1           /* PLL   */
0205 };
0206
0207 #endif