drm/ast/ast_dp501.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 #include <linux/delay.h>
0004 #include <linux/firmware.h>
0005 #include <linux/module.h>
0006
0007 #include "ast_drv.h"
0008
0009 MODULE_FIRMWARE("ast_dp501_fw.bin");
0010
0011 static void ast_release_firmware(void *data)
0012 {
0013     struct ast_private *ast = data;
0014
0015     release_firmware(ast->dp501_fw);
0016     ast->dp501_fw = NULL;
0017 }
0018
0019 static int ast_load_dp501_microcode(struct drm_device *dev)
0020 {
0021     struct ast_private *ast = to_ast_private(dev);
0022     int ret;
0023
0024     ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev);
0025     if (ret)
0026         return ret;
0027
0028     return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast);
0029 }
0030
0031 static void send_ack(struct ast_private *ast)
0032 {
0033     u8 sendack;
0034     sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
0035     sendack |= 0x80;
0036     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
0037 }
0038
0039 static void send_nack(struct ast_private *ast)
0040 {
0041     u8 sendack;
0042     sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
0043     sendack &= ~0x80;
0044     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
0045 }
0046
0047 static bool wait_ack(struct ast_private *ast)
0048 {
0049     u8 waitack;
0050     u32 retry = 0;
0051     do {
0052         waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
0053         waitack &= 0x80;
0054         udelay(100);
0055     } while ((!waitack) && (retry++ < 1000));
0056
0057     if (retry < 1000)
0058         return true;
0059     else
0060         return false;
0061 }
0062
0063 static bool wait_nack(struct ast_private *ast)
0064 {
0065     u8 waitack;
0066     u32 retry = 0;
0067     do {
0068         waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
0069         waitack &= 0x80;
0070         udelay(100);
0071     } while ((waitack) && (retry++ < 1000));
0072
0073     if (retry < 1000)
0074         return true;
0075     else
0076         return false;
0077 }
0078
0079 static void set_cmd_trigger(struct ast_private *ast)
0080 {
0081     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
0082 }
0083
0084 static void clear_cmd_trigger(struct ast_private *ast)
0085 {
0086     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
0087 }
0088
0089 #if 0
0090 static bool wait_fw_ready(struct ast_private *ast)
0091 {
0092     u8 waitready;
0093     u32 retry = 0;
0094     do {
0095         waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
0096         waitready &= 0x40;
0097         udelay(100);
0098     } while ((!waitready) && (retry++ < 1000));
0099
0100     if (retry < 1000)
0101         return true;
0102     else
0103         return false;
0104 }
0105 #endif
0106
0107 static bool ast_write_cmd(struct drm_device *dev, u8 data)
0108 {
0109     struct ast_private *ast = to_ast_private(dev);
0110     int retry = 0;
0111     if (wait_nack(ast)) {
0112         send_nack(ast);
0113         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
0114         send_ack(ast);
0115         set_cmd_trigger(ast);
0116         do {
0117             if (wait_ack(ast)) {
0118                 clear_cmd_trigger(ast);
0119                 send_nack(ast);
0120                 return true;
0121             }
0122         } while (retry++ < 100);
0123     }
0124     clear_cmd_trigger(ast);
0125     send_nack(ast);
0126     return false;
0127 }
0128
0129 static bool ast_write_data(struct drm_device *dev, u8 data)
0130 {
0131     struct ast_private *ast = to_ast_private(dev);
0132
0133     if (wait_nack(ast)) {
0134         send_nack(ast);
0135         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
0136         send_ack(ast);
0137         if (wait_ack(ast)) {
0138             send_nack(ast);
0139             return true;
0140         }
0141     }
0142     send_nack(ast);
0143     return false;
0144 }
0145
0146 #if 0
0147 static bool ast_read_data(struct drm_device *dev, u8 *data)
0148 {
0149     struct ast_private *ast = to_ast_private(dev);
0150     u8 tmp;
0151
0152     *data = 0;
0153
0154     if (wait_ack(ast) == false)
0155         return false;
0156     tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
0157     *data = tmp;
0158     if (wait_nack(ast) == false) {
0159         send_nack(ast);
0160         return false;
0161     }
0162     send_nack(ast);
0163     return true;
0164 }
0165
0166 static void clear_cmd(struct ast_private *ast)
0167 {
0168     send_nack(ast);
0169     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
0170 }
0171 #endif
0172
0173 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
0174 {
0175     ast_write_cmd(dev, 0x40);
0176     ast_write_data(dev, mode);
0177
0178     msleep(10);
0179 }
0180
0181 static u32 get_fw_base(struct ast_private *ast)
0182 {
0183     return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
0184 }
0185
0186 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
0187 {
0188     struct ast_private *ast = to_ast_private(dev);
0189     u32 i, data;
0190     u32 boot_address;
0191
0192     if (ast->config_mode != ast_use_p2a)
0193         return false;
0194
0195     data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
0196     if (data) {
0197         boot_address = get_fw_base(ast);
0198         for (i = 0; i < size; i += 4)
0199             *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
0200         return true;
0201     }
0202     return false;
0203 }
0204
0205 static bool ast_launch_m68k(struct drm_device *dev)
0206 {
0207     struct ast_private *ast = to_ast_private(dev);
0208     u32 i, data, len = 0;
0209     u32 boot_address;
0210     u8 *fw_addr = NULL;
0211     u8 jreg;
0212
0213     if (ast->config_mode != ast_use_p2a)
0214         return false;
0215
0216     data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
0217     if (!data) {
0218
0219         if (ast->dp501_fw_addr) {
0220             fw_addr = ast->dp501_fw_addr;
0221             len = 32*1024;
0222         } else {
0223             if (!ast->dp501_fw &&
0224                 ast_load_dp501_microcode(dev) < 0)
0225                 return false;
0226
0227             fw_addr = (u8 *)ast->dp501_fw->data;
0228             len = ast->dp501_fw->size;
0229         }
0230         /* Get BootAddress */
0231         ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
0232         data = ast_mindwm(ast, 0x1e6e0004);
0233         switch (data & 0x03) {
0234         case 0:
0235             boot_address = 0x44000000;
0236             break;
0237         default:
0238         case 1:
0239             boot_address = 0x48000000;
0240             break;
0241         case 2:
0242             boot_address = 0x50000000;
0243             break;
0244         case 3:
0245             boot_address = 0x60000000;
0246             break;
0247         }
0248         boot_address -= 0x200000; /* -2MB */
0249
0250         /* copy image to buffer */
0251         for (i = 0; i < len; i += 4) {
0252             data = *(u32 *)(fw_addr + i);
0253             ast_moutdwm(ast, boot_address + i, data);
0254         }
0255
0256         /* Init SCU */
0257         ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
0258
0259         /* Launch FW */
0260         ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
0261         ast_moutdwm(ast, 0x1e6e2100, 1);
0262
0263         /* Update Scratch */
0264         data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff;        /* D[11:9] = 100b: UEFI handling */
0265         data |= 0x800;
0266         ast_moutdwm(ast, 0x1e6e2040, data);
0267
0268         jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
0269         jreg |= 0x02;
0270         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
0271     }
0272     return true;
0273 }
0274
0275 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
0276 {
0277     struct ast_private *ast = to_ast_private(dev);
0278     u32 i, boot_address, offset, data;
0279     u32 *pEDIDidx;
0280
0281     if (ast->config_mode == ast_use_p2a) {
0282         boot_address = get_fw_base(ast);
0283
0284         /* validate FW version */
0285         offset = AST_DP501_GBL_VERSION;
0286         data = ast_mindwm(ast, boot_address + offset);
0287         if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1)
0288             return false;
0289
0290         /* validate PnP Monitor */
0291         offset = AST_DP501_PNPMONITOR;
0292         data = ast_mindwm(ast, boot_address + offset);
0293         if (!(data & AST_DP501_PNP_CONNECTED))
0294             return false;
0295
0296         /* Read EDID */
0297         offset = AST_DP501_EDID_DATA;
0298         for (i = 0; i < 128; i += 4) {
0299             data = ast_mindwm(ast, boot_address + offset + i);
0300             pEDIDidx = (u32 *)(ediddata + i);
0301             *pEDIDidx = data;
0302         }
0303     } else {
0304         if (!ast->dp501_fw_buf)
0305             return false;
0306
0307         /* dummy read */
0308         offset = 0x0000;
0309         data = readl(ast->dp501_fw_buf + offset);
0310
0311         /* validate FW version */
0312         offset = AST_DP501_GBL_VERSION;
0313         data = readl(ast->dp501_fw_buf + offset);
0314         if ((data & AST_DP501_FW_VERSION_MASK) != AST_DP501_FW_VERSION_1)
0315             return false;
0316
0317         /* validate PnP Monitor */
0318         offset = AST_DP501_PNPMONITOR;
0319         data = readl(ast->dp501_fw_buf + offset);
0320         if (!(data & AST_DP501_PNP_CONNECTED))
0321             return false;
0322
0323         /* Read EDID */
0324         offset = AST_DP501_EDID_DATA;
0325         for (i = 0; i < 128; i += 4) {
0326             data = readl(ast->dp501_fw_buf + offset + i);
0327             pEDIDidx = (u32 *)(ediddata + i);
0328             *pEDIDidx = data;
0329         }
0330     }
0331
0332     return true;
0333 }
0334
0335 static bool ast_init_dvo(struct drm_device *dev)
0336 {
0337     struct ast_private *ast = to_ast_private(dev);
0338     u8 jreg;
0339     u32 data;
0340     ast_write32(ast, 0xf004, 0x1e6e0000);
0341     ast_write32(ast, 0xf000, 0x1);
0342     ast_write32(ast, 0x12000, 0x1688a8a8);
0343
0344     jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
0345     if (!(jreg & 0x80)) {
0346         /* Init SCU DVO Settings */
0347         data = ast_read32(ast, 0x12008);
0348         /* delay phase */
0349         data &= 0xfffff8ff;
0350         data |= 0x00000500;
0351         ast_write32(ast, 0x12008, data);
0352
0353         if (ast->chip == AST2300) {
0354             data = ast_read32(ast, 0x12084);
0355             /* multi-pins for DVO single-edge */
0356             data |= 0xfffe0000;
0357             ast_write32(ast, 0x12084, data);
0358
0359             data = ast_read32(ast, 0x12088);
0360             /* multi-pins for DVO single-edge */
0361             data |= 0x000fffff;
0362             ast_write32(ast, 0x12088, data);
0363
0364             data = ast_read32(ast, 0x12090);
0365             /* multi-pins for DVO single-edge */
0366             data &= 0xffffffcf;
0367             data |= 0x00000020;
0368             ast_write32(ast, 0x12090, data);
0369         } else { /* AST2400 */
0370             data = ast_read32(ast, 0x12088);
0371             /* multi-pins for DVO single-edge */
0372             data |= 0x30000000;
0373             ast_write32(ast, 0x12088, data);
0374
0375             data = ast_read32(ast, 0x1208c);
0376             /* multi-pins for DVO single-edge */
0377             data |= 0x000000cf;
0378             ast_write32(ast, 0x1208c, data);
0379
0380             data = ast_read32(ast, 0x120a4);
0381             /* multi-pins for DVO single-edge */
0382             data |= 0xffff0000;
0383             ast_write32(ast, 0x120a4, data);
0384
0385             data = ast_read32(ast, 0x120a8);
0386             /* multi-pins for DVO single-edge */
0387             data |= 0x0000000f;
0388             ast_write32(ast, 0x120a8, data);
0389
0390             data = ast_read32(ast, 0x12094);
0391             /* multi-pins for DVO single-edge */
0392             data |= 0x00000002;
0393             ast_write32(ast, 0x12094, data);
0394         }
0395     }
0396
0397     /* Force to DVO */
0398     data = ast_read32(ast, 0x1202c);
0399     data &= 0xfffbffff;
0400     ast_write32(ast, 0x1202c, data);
0401
0402     /* Init VGA DVO Settings */
0403     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
0404     return true;
0405 }
0406
0407
0408 static void ast_init_analog(struct drm_device *dev)
0409 {
0410     struct ast_private *ast = to_ast_private(dev);
0411     u32 data;
0412
0413     /*
0414      * Set DAC source to VGA mode in SCU2C via the P2A
0415      * bridge. First configure the P2U to target the SCU
0416      * in case it isn't at this stage.
0417      */
0418     ast_write32(ast, 0xf004, 0x1e6e0000);
0419     ast_write32(ast, 0xf000, 0x1);
0420
0421     /* Then unlock the SCU with the magic password */
0422     ast_write32(ast, 0x12000, 0x1688a8a8);
0423     ast_write32(ast, 0x12000, 0x1688a8a8);
0424     ast_write32(ast, 0x12000, 0x1688a8a8);
0425
0426     /* Finally, clear bits [17:16] of SCU2c */
0427     data = ast_read32(ast, 0x1202c);
0428     data &= 0xfffcffff;
0429     ast_write32(ast, 0, data);
0430
0431     /* Disable DVO */
0432     ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
0433 }
0434
0435 void ast_init_3rdtx(struct drm_device *dev)
0436 {
0437     struct ast_private *ast = to_ast_private(dev);
0438     u8 jreg;
0439
0440     if (ast->chip == AST2300 || ast->chip == AST2400) {
0441         jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
0442         switch (jreg & 0x0e) {
0443         case 0x04:
0444             ast_init_dvo(dev);
0445             break;
0446         case 0x08:
0447             ast_launch_m68k(dev);
0448             break;
0449         case 0x0c:
0450             ast_init_dvo(dev);
0451             break;
0452         default:
0453             if (ast->tx_chip_types & BIT(AST_TX_SIL164))
0454                 ast_init_dvo(dev);
0455             else
0456                 ast_init_analog(dev);
0457         }
0458     }
0459 }