drm/armada/armada_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 Russell King
0004  *  Rewritten from the dovefb driver, and Armada510 manuals.
0005  */
0006 #ifndef ARMADA_HW_H
0007 #define ARMADA_HW_H
0008
0009 /*
0010  * Note: the following registers are written from IRQ context:
0011  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
0012  *  LCD_SPU_DMA_START_ADDR_[YUV][01], LCD_SPU_DMA_PITCH_YC,
0013  *  LCD_SPU_DMA_PITCH_UV, LCD_SPU_DMA_OVSA_HPXL_VLN,
0014  *  LCD_SPU_DMA_HPXL_VLN, LCD_SPU_DZM_HPXL_VLN, LCD_SPU_DMA_CTRL0
0015  */
0016 enum {
0017     LCD_SPU_ADV_REG         = 0x0084,   /* Armada 510 */
0018     LCD_SPU_DMA_START_ADDR_Y0   = 0x00c0,
0019     LCD_SPU_DMA_START_ADDR_U0   = 0x00c4,
0020     LCD_SPU_DMA_START_ADDR_V0   = 0x00c8,
0021     LCD_CFG_DMA_START_ADDR_0    = 0x00cc,
0022     LCD_SPU_DMA_START_ADDR_Y1   = 0x00d0,
0023     LCD_SPU_DMA_START_ADDR_U1   = 0x00d4,
0024     LCD_SPU_DMA_START_ADDR_V1   = 0x00d8,
0025     LCD_CFG_DMA_START_ADDR_1    = 0x00dc,
0026     LCD_SPU_DMA_PITCH_YC        = 0x00e0,
0027     LCD_SPU_DMA_PITCH_UV        = 0x00e4,
0028     LCD_SPU_DMA_OVSA_HPXL_VLN   = 0x00e8,
0029     LCD_SPU_DMA_HPXL_VLN        = 0x00ec,
0030     LCD_SPU_DZM_HPXL_VLN        = 0x00f0,
0031     LCD_CFG_GRA_START_ADDR0     = 0x00f4,
0032     LCD_CFG_GRA_START_ADDR1     = 0x00f8,
0033     LCD_CFG_GRA_PITCH       = 0x00fc,
0034     LCD_SPU_GRA_OVSA_HPXL_VLN   = 0x0100,
0035     LCD_SPU_GRA_HPXL_VLN        = 0x0104,
0036     LCD_SPU_GZM_HPXL_VLN        = 0x0108,
0037     LCD_SPU_HWC_OVSA_HPXL_VLN   = 0x010c,
0038     LCD_SPU_HWC_HPXL_VLN        = 0x0110,
0039     LCD_SPUT_V_H_TOTAL      = 0x0114,
0040     LCD_SPU_V_H_ACTIVE      = 0x0118,
0041     LCD_SPU_H_PORCH         = 0x011c,
0042     LCD_SPU_V_PORCH         = 0x0120,
0043     LCD_SPU_BLANKCOLOR      = 0x0124,
0044     LCD_SPU_ALPHA_COLOR1        = 0x0128,
0045     LCD_SPU_ALPHA_COLOR2        = 0x012c,
0046     LCD_SPU_COLORKEY_Y      = 0x0130,
0047     LCD_SPU_COLORKEY_U      = 0x0134,
0048     LCD_SPU_COLORKEY_V      = 0x0138,
0049     LCD_CFG_RDREG4F         = 0x013c,   /* Armada 510 */
0050     LCD_SPU_SPI_RXDATA      = 0x0140,
0051     LCD_SPU_ISA_RXDATA      = 0x0144,
0052     LCD_SPU_HWC_RDDAT       = 0x0158,
0053     LCD_SPU_GAMMA_RDDAT     = 0x015c,
0054     LCD_SPU_PALETTE_RDDAT       = 0x0160,
0055     LCD_SPU_IOPAD_IN        = 0x0178,
0056     LCD_CFG_RDREG5F         = 0x017c,
0057     LCD_SPU_SPI_CTRL        = 0x0180,
0058     LCD_SPU_SPI_TXDATA      = 0x0184,
0059     LCD_SPU_SMPN_CTRL       = 0x0188,
0060     LCD_SPU_DMA_CTRL0       = 0x0190,
0061     LCD_SPU_DMA_CTRL1       = 0x0194,
0062     LCD_SPU_SRAM_CTRL       = 0x0198,
0063     LCD_SPU_SRAM_WRDAT      = 0x019c,
0064     LCD_SPU_SRAM_PARA0      = 0x01a0,   /* Armada 510 */
0065     LCD_SPU_SRAM_PARA1      = 0x01a4,
0066     LCD_CFG_SCLK_DIV        = 0x01a8,
0067     LCD_SPU_CONTRAST        = 0x01ac,
0068     LCD_SPU_SATURATION      = 0x01b0,
0069     LCD_SPU_CBSH_HUE        = 0x01b4,
0070     LCD_SPU_DUMB_CTRL       = 0x01b8,
0071     LCD_SPU_IOPAD_CONTROL       = 0x01bc,
0072     LCD_SPU_IRQ_ENA         = 0x01c0,
0073     LCD_SPU_IRQ_ISR         = 0x01c4,
0074 };
0075
0076 /* For LCD_SPU_ADV_REG */
0077 enum {
0078     ADV_VSYNC_L_OFF = 0xfff << 20,
0079     ADV_GRACOLORKEY = 1 << 19,
0080     ADV_VIDCOLORKEY = 1 << 18,
0081     ADV_HWC32BLEND  = 1 << 15,
0082     ADV_HWC32ARGB   = 1 << 14,
0083     ADV_HWC32ENABLE = 1 << 13,
0084     ADV_VSYNCOFFEN  = 1 << 12,
0085     ADV_VSYNC_H_OFF = 0xfff << 0,
0086 };
0087
0088 /* LCD_CFG_RDREG4F - Armada 510 only */
0089 enum {
0090     CFG_SRAM_WAIT   = BIT(11),
0091     CFG_SMPN_FASTTX = BIT(10),
0092     CFG_DMA_ARB = BIT(9),
0093     CFG_DMA_WM_EN   = BIT(8),
0094     CFG_DMA_WM_MASK = 0xff,
0095 #define CFG_DMA_WM(x)   ((x) & CFG_DMA_WM_MASK)
0096 };
0097
0098 enum {
0099     CFG_565     = 0,
0100     CFG_1555    = 1,
0101     CFG_888PACK = 2,
0102     CFG_X888    = 3,
0103     CFG_8888    = 4,
0104     CFG_422PACK = 5,
0105     CFG_422     = 6,
0106     CFG_420     = 7,
0107     CFG_PSEUDO4 = 9,
0108     CFG_PSEUDO8 = 10,
0109     CFG_SWAPRB  = 1 << 4,
0110     CFG_SWAPUV  = 1 << 3,
0111     CFG_SWAPYU  = 1 << 2,
0112     CFG_YUV2RGB = 1 << 1,
0113 };
0114
0115 /* For LCD_SPU_DMA_CTRL0 */
0116 enum {
0117     CFG_NOBLENDING  = 1 << 31,
0118     CFG_GAMMA_ENA   = 1 << 30,
0119     CFG_CBSH_ENA    = 1 << 29,
0120     CFG_PALETTE_ENA = 1 << 28,
0121     CFG_ARBFAST_ENA = 1 << 27,
0122     CFG_HWC_1BITMOD = 1 << 26,
0123     CFG_HWC_1BITENA = 1 << 25,
0124     CFG_HWC_ENA = 1 << 24,
0125     CFG_DMAFORMAT   = 0xf << 20,
0126 #define CFG_DMA_FMT(x)  ((x) << 20)
0127     CFG_GRAFORMAT   = 0xf << 16,
0128 #define CFG_GRA_FMT(x)  ((x) << 16)
0129 #define CFG_GRA_MOD(x)  ((x) << 8)
0130     CFG_GRA_FTOGGLE = 1 << 15,
0131     CFG_GRA_HSMOOTH = 1 << 14,
0132     CFG_GRA_TSTMODE = 1 << 13,
0133     CFG_GRA_ENA = 1 << 8,
0134 #define CFG_DMA_MOD(x)  ((x) << 0)
0135     CFG_DMA_FTOGGLE = 1 << 7,
0136     CFG_DMA_HSMOOTH = 1 << 6,
0137     CFG_DMA_TSTMODE = 1 << 5,
0138     CFG_DMA_ENA = 1 << 0,
0139 };
0140
0141 enum {
0142     CKMODE_DISABLE  = 0,
0143     CKMODE_Y    = 1,
0144     CKMODE_U    = 2,
0145     CKMODE_RGB  = 3,
0146     CKMODE_V    = 4,
0147     CKMODE_R    = 5,
0148     CKMODE_G    = 6,
0149     CKMODE_B    = 7,
0150 };
0151
0152 /* For LCD_SPU_DMA_CTRL1 */
0153 enum {
0154     CFG_FRAME_TRIG      = 1 << 31,
0155     CFG_VSYNC_INV       = 1 << 27,
0156     CFG_CKMODE_MASK     = 0x7 << 24,
0157 #define CFG_CKMODE(x)       ((x) << 24)
0158     CFG_CARRY       = 1 << 23,
0159     CFG_GATED_CLK       = 1 << 21,
0160     CFG_PWRDN_ENA       = 1 << 20,
0161     CFG_DSCALE_MASK     = 0x3 << 18,
0162     CFG_DSCALE_NONE     = 0x0 << 18,
0163     CFG_DSCALE_HALF     = 0x1 << 18,
0164     CFG_DSCALE_QUAR     = 0x2 << 18,
0165     CFG_ALPHAM_MASK     = 0x3 << 16,
0166     CFG_ALPHAM_VIDEO    = 0x0 << 16,
0167     CFG_ALPHAM_GRA      = 0x1 << 16,
0168     CFG_ALPHAM_CFG      = 0x2 << 16,
0169     CFG_ALPHA_MASK      = 0xff << 8,
0170 #define CFG_ALPHA(x)        ((x) << 8)
0171     CFG_PIXCMD_MASK     = 0xff,
0172 };
0173
0174 /* For LCD_SPU_SRAM_CTRL */
0175 enum {
0176     SRAM_READ   = 0 << 14,
0177     SRAM_WRITE  = 2 << 14,
0178     SRAM_INIT   = 3 << 14,
0179     SRAM_GAMMA_YR   = 0x0 << 8,
0180     SRAM_GAMMA_UG   = 0x1 << 8,
0181     SRAM_GAMMA_VB   = 0x2 << 8,
0182     SRAM_PALETTE    = 0x3 << 8,
0183     SRAM_HWC32_RAM1 = 0xc << 8,
0184     SRAM_HWC32_RAM2 = 0xd << 8,
0185     SRAM_HWC32_RAMR = SRAM_HWC32_RAM1,
0186     SRAM_HWC32_RAMG = SRAM_HWC32_RAM2,
0187     SRAM_HWC32_RAMB = 0xe << 8,
0188     SRAM_HWC32_TRAN = 0xf << 8,
0189     SRAM_HWC    = 0xf << 8,
0190 };
0191
0192 /* For LCD_SPU_SRAM_PARA1 */
0193 enum {
0194     CFG_CSB_256x32  = 1 << 15,  /* cursor */
0195     CFG_CSB_256x24  = 1 << 14,  /* palette */
0196     CFG_CSB_256x8   = 1 << 13,  /* gamma */
0197     CFG_PDWN1920x32 = 1 << 8,   /* Armada 510: power down vscale ram */
0198     CFG_PDWN256x32  = 1 << 7,   /* power down cursor */
0199     CFG_PDWN256x24  = 1 << 6,   /* power down palette */
0200     CFG_PDWN256x8   = 1 << 5,   /* power down gamma */
0201     CFG_PDWNHWC = 1 << 4,   /* Armada 510: power down all hwc ram */
0202     CFG_PDWN32x32   = 1 << 3,   /* power down slave->smart ram */
0203     CFG_PDWN16x66   = 1 << 2,   /* power down UV fifo */
0204     CFG_PDWN32x66   = 1 << 1,   /* power down Y fifo */
0205     CFG_PDWN64x66   = 1 << 0,   /* power down graphic fifo */
0206 };
0207
0208 /* For LCD_CFG_SCLK_DIV */
0209 enum {
0210     /* Armada 510 */
0211     SCLK_510_AXI        = 0x0 << 30,
0212     SCLK_510_EXTCLK0    = 0x1 << 30,
0213     SCLK_510_PLL        = 0x2 << 30,
0214     SCLK_510_EXTCLK1    = 0x3 << 30,
0215     SCLK_510_DIV_CHANGE = 1 << 29,
0216     SCLK_510_FRAC_DIV_MASK  = 0xfff << 16,
0217     SCLK_510_INT_DIV_MASK   = 0xffff << 0,
0218
0219     /* Armada 16x */
0220     SCLK_16X_AHB        = 0x0 << 28,
0221     SCLK_16X_PCLK       = 0x1 << 28,
0222     SCLK_16X_AXI        = 0x4 << 28,
0223     SCLK_16X_PLL        = 0x8 << 28,
0224     SCLK_16X_FRAC_DIV_MASK  = 0xfff << 16,
0225     SCLK_16X_INT_DIV_MASK   = 0xffff << 0,
0226 };
0227
0228 /* For LCD_SPU_DUMB_CTRL */
0229 enum {
0230     DUMB16_RGB565_0 = 0x0 << 28,
0231     DUMB16_RGB565_1 = 0x1 << 28,
0232     DUMB18_RGB666_0 = 0x2 << 28,
0233     DUMB18_RGB666_1 = 0x3 << 28,
0234     DUMB12_RGB444_0 = 0x4 << 28,
0235     DUMB12_RGB444_1 = 0x5 << 28,
0236     DUMB24_RGB888_0 = 0x6 << 28,
0237     DUMB_BLANK  = 0x7 << 28,
0238     DUMB_MASK   = 0xf << 28,
0239     CFG_BIAS_OUT    = 1 << 8,
0240     CFG_REV_RGB = 1 << 7,
0241     CFG_INV_CBLANK  = 1 << 6,
0242     CFG_INV_CSYNC   = 1 << 5,   /* Normally active high */
0243     CFG_INV_HENA    = 1 << 4,
0244     CFG_INV_VSYNC   = 1 << 3,   /* Normally active high */
0245     CFG_INV_HSYNC   = 1 << 2,   /* Normally active high */
0246     CFG_INV_PCLK    = 1 << 1,
0247     CFG_DUMB_ENA    = 1 << 0,
0248 };
0249
0250 /* For LCD_SPU_IOPAD_CONTROL */
0251 enum {
0252     CFG_VSCALE_LN_EN    = 3 << 18,
0253     CFG_GRA_VM_ENA      = 1 << 15,
0254     CFG_DMA_VM_ENA      = 1 << 13,
0255     CFG_CMD_VM_ENA      = 1 << 11,
0256     CFG_CSC_MASK        = 3 << 8,
0257     CFG_CSC_YUV_CCIR709 = 1 << 9,
0258     CFG_CSC_YUV_CCIR601 = 0 << 9,
0259     CFG_CSC_RGB_STUDIO  = 1 << 8,
0260     CFG_CSC_RGB_COMPUTER    = 0 << 8,
0261     CFG_IOPAD_MASK      = 0xf << 0,
0262     CFG_IOPAD_DUMB24    = 0x0 << 0,
0263     CFG_IOPAD_DUMB18SPI = 0x1 << 0,
0264     CFG_IOPAD_DUMB18GPIO    = 0x2 << 0,
0265     CFG_IOPAD_DUMB16SPI = 0x3 << 0,
0266     CFG_IOPAD_DUMB16GPIO    = 0x4 << 0,
0267     CFG_IOPAD_DUMB12GPIO    = 0x5 << 0,
0268     CFG_IOPAD_SMART18   = 0x6 << 0,
0269     CFG_IOPAD_SMART16   = 0x7 << 0,
0270     CFG_IOPAD_SMART8    = 0x8 << 0,
0271 };
0272
0273 #define IOPAD_DUMB24                0x0
0274
0275 /* For LCD_SPU_IRQ_ENA */
0276 enum {
0277     DMA_FRAME_IRQ0_ENA  = 1 << 31,
0278     DMA_FRAME_IRQ1_ENA  = 1 << 30,
0279     DMA_FRAME_IRQ_ENA   = DMA_FRAME_IRQ0_ENA | DMA_FRAME_IRQ1_ENA,
0280     DMA_FF_UNDERFLOW_ENA    = 1 << 29,
0281     GRA_FRAME_IRQ0_ENA  = 1 << 27,
0282     GRA_FRAME_IRQ1_ENA  = 1 << 26,
0283     GRA_FRAME_IRQ_ENA   = GRA_FRAME_IRQ0_ENA | GRA_FRAME_IRQ1_ENA,
0284     GRA_FF_UNDERFLOW_ENA    = 1 << 25,
0285     VSYNC_IRQ_ENA       = 1 << 23,
0286     DUMB_FRAMEDONE_ENA  = 1 << 22,
0287     TWC_FRAMEDONE_ENA   = 1 << 21,
0288     HWC_FRAMEDONE_ENA   = 1 << 20,
0289     SLV_IRQ_ENA     = 1 << 19,
0290     SPI_IRQ_ENA     = 1 << 18,
0291     PWRDN_IRQ_ENA       = 1 << 17,
0292     ERR_IRQ_ENA     = 1 << 16,
0293     CLEAN_SPU_IRQ_ISR   = 0xffff,
0294 };
0295
0296 /* For LCD_SPU_IRQ_ISR */
0297 enum {
0298     DMA_FRAME_IRQ0      = 1 << 31,
0299     DMA_FRAME_IRQ1      = 1 << 30,
0300     DMA_FRAME_IRQ       = DMA_FRAME_IRQ0 | DMA_FRAME_IRQ1,
0301     DMA_FF_UNDERFLOW    = 1 << 29,
0302     GRA_FRAME_IRQ0      = 1 << 27,
0303     GRA_FRAME_IRQ1      = 1 << 26,
0304     GRA_FRAME_IRQ       = GRA_FRAME_IRQ0 | GRA_FRAME_IRQ1,
0305     GRA_FF_UNDERFLOW    = 1 << 25,
0306     VSYNC_IRQ       = 1 << 23,
0307     DUMB_FRAMEDONE      = 1 << 22,
0308     TWC_FRAMEDONE       = 1 << 21,
0309     HWC_FRAMEDONE       = 1 << 20,
0310     SLV_IRQ         = 1 << 19,
0311     SPI_IRQ         = 1 << 18,
0312     PWRDN_IRQ       = 1 << 17,
0313     ERR_IRQ         = 1 << 16,
0314     DMA_FRAME_IRQ0_LEVEL    = 1 << 15,
0315     DMA_FRAME_IRQ1_LEVEL    = 1 << 14,
0316     DMA_FRAME_CNT_ISR   = 3 << 12,
0317     GRA_FRAME_IRQ0_LEVEL    = 1 << 11,
0318     GRA_FRAME_IRQ1_LEVEL    = 1 << 10,
0319     GRA_FRAME_CNT_ISR   = 3 << 8,
0320     VSYNC_IRQ_LEVEL     = 1 << 7,
0321     DUMB_FRAMEDONE_LEVEL    = 1 << 6,
0322     TWC_FRAMEDONE_LEVEL = 1 << 5,
0323     HWC_FRAMEDONE_LEVEL = 1 << 4,
0324     SLV_FF_EMPTY        = 1 << 3,
0325     DMA_FF_ALLEMPTY     = 1 << 2,
0326     GRA_FF_ALLEMPTY     = 1 << 1,
0327     PWRDN_IRQ_LEVEL     = 1 << 0,
0328 };
0329
0330 #endif