drm/armada/armada_crtc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 Russell King
0004  */
0005 #ifndef ARMADA_CRTC_H
0006 #define ARMADA_CRTC_H
0007
0008 #include <drm/drm_crtc.h>
0009
0010 struct armada_gem_object;
0011
0012 struct armada_regs {
0013     uint32_t offset;
0014     uint32_t mask;
0015     uint32_t val;
0016 };
0017
0018 #define armada_reg_queue_mod(_r, _i, _v, _m, _o)    \
0019     do {                    \
0020         struct armada_regs *__reg = _r; \
0021         __reg[_i].offset = _o;      \
0022         __reg[_i].mask = ~(_m);     \
0023         __reg[_i].val = _v;     \
0024         _i++;               \
0025     } while (0)
0026
0027 #define armada_reg_queue_set(_r, _i, _v, _o)    \
0028     armada_reg_queue_mod(_r, _i, _v, ~0, _o)
0029
0030 #define armada_reg_queue_end(_r, _i)        \
0031     armada_reg_queue_mod(_r, _i, 0, 0, ~0)
0032
0033 struct armada_crtc;
0034 struct armada_variant;
0035
0036 struct armada_crtc {
0037     struct drm_crtc     crtc;
0038     const struct armada_variant *variant;
0039     void            *variant_data;
0040     unsigned        num;
0041     void __iomem        *base;
0042     struct clk      *clk;
0043     struct {
0044         uint32_t    spu_v_h_total;
0045         uint32_t    spu_v_porch;
0046         uint32_t    spu_adv_reg;
0047     } v[2];
0048     bool            interlaced;
0049     bool            cursor_update;
0050
0051     struct armada_gem_object    *cursor_obj;
0052     int         cursor_x;
0053     int         cursor_y;
0054     uint32_t        cursor_hw_pos;
0055     uint32_t        cursor_hw_sz;
0056     uint32_t        cursor_w;
0057     uint32_t        cursor_h;
0058
0059     uint32_t        cfg_dumb_ctrl;
0060     uint32_t        spu_iopad_ctrl;
0061
0062     spinlock_t      irq_lock;
0063     uint32_t        irq_ena;
0064
0065     bool            update_pending;
0066     struct drm_pending_vblank_event *event;
0067     struct armada_regs  atomic_regs[32];
0068     struct armada_regs  *regs;
0069     unsigned int        regs_idx;
0070 };
0071 #define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc)
0072
0073 void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *);
0074
0075 struct armada_clocking_params {
0076     unsigned long permillage_min;
0077     unsigned long permillage_max;
0078     u32 settable;
0079     u32 div_max;
0080 };
0081
0082 struct armada_clk_result {
0083     unsigned long desired_clk_hz;
0084     struct clk *clk;
0085     u32 div;
0086 };
0087
0088 int armada_crtc_select_clock(struct armada_crtc *dcrtc,
0089                  struct armada_clk_result *res,
0090                  const struct armada_clocking_params *params,
0091                  struct clk *clks[], size_t num_clks,
0092                  unsigned long desired_khz);
0093
0094 extern struct platform_driver armada_lcd_platform_driver;
0095
0096 #endif