drm/armada/armada_510.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 Russell King
0004  *
0005  * Armada 510 (aka Dove) variant support
0006  */
0007 #include <linux/clk.h>
0008 #include <linux/io.h>
0009 #include <linux/of.h>
0010 #include <drm/drm_probe_helper.h>
0011 #include "armada_crtc.h"
0012 #include "armada_drm.h"
0013 #include "armada_hw.h"
0014
0015 struct armada510_variant_data {
0016     struct clk *clks[4];
0017     struct clk *sel_clk;
0018 };
0019
0020 static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
0021 {
0022     struct armada510_variant_data *v;
0023     struct clk *clk;
0024     int idx;
0025
0026     v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL);
0027     if (!v)
0028         return -ENOMEM;
0029
0030     dcrtc->variant_data = v;
0031
0032     if (dev->of_node) {
0033         struct property *prop;
0034         const char *s;
0035
0036         of_property_for_each_string(dev->of_node, "clock-names", prop,
0037                         s) {
0038             if (!strcmp(s, "ext_ref_clk0"))
0039                 idx = 0;
0040             else if (!strcmp(s, "ext_ref_clk1"))
0041                 idx = 1;
0042             else if (!strcmp(s, "plldivider"))
0043                 idx = 2;
0044             else if (!strcmp(s, "axibus"))
0045                 idx = 3;
0046             else
0047                 continue;
0048
0049             clk = devm_clk_get(dev, s);
0050             if (IS_ERR(clk))
0051                 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
0052                     PTR_ERR(clk);
0053             v->clks[idx] = clk;
0054         }
0055     } else {
0056         clk = devm_clk_get(dev, "ext_ref_clk1");
0057         if (IS_ERR(clk))
0058             return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
0059                 PTR_ERR(clk);
0060
0061         v->clks[1] = clk;
0062     }
0063
0064     /*
0065      * Lower the watermark so to eliminate jitter at higher bandwidths.
0066      * Disable SRAM read wait state to avoid system hang with external
0067      * clock.
0068      */
0069     armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,
0070                dcrtc->base + LCD_CFG_RDREG4F);
0071
0072     /* Initialise SPU register */
0073     writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
0074                dcrtc->base + LCD_SPU_ADV_REG);
0075
0076     return 0;
0077 }
0078
0079 static const u32 armada510_clk_sels[] = {
0080     SCLK_510_EXTCLK0,
0081     SCLK_510_EXTCLK1,
0082     SCLK_510_PLL,
0083     SCLK_510_AXI,
0084 };
0085
0086 static const struct armada_clocking_params armada510_clocking = {
0087     /* HDMI requires -0.6%..+0.5% */
0088     .permillage_min = 994,
0089     .permillage_max = 1005,
0090     .settable = BIT(0) | BIT(1),
0091     .div_max = SCLK_510_INT_DIV_MASK,
0092 };
0093
0094 /*
0095  * Armada510 specific SCLK register selection.
0096  * This gets called with sclk = NULL to test whether the mode is
0097  * supportable, and again with sclk != NULL to set the clocks up for
0098  * that.  The former can return an error, but the latter is expected
0099  * not to.
0100  */
0101 static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
0102     const struct drm_display_mode *mode, uint32_t *sclk)
0103 {
0104     struct armada510_variant_data *v = dcrtc->variant_data;
0105     unsigned long desired_khz = mode->crtc_clock;
0106     struct armada_clk_result res;
0107     int ret, idx;
0108
0109     idx = armada_crtc_select_clock(dcrtc, &res, &armada510_clocking,
0110                        v->clks, ARRAY_SIZE(v->clks),
0111                        desired_khz);
0112     if (idx < 0)
0113         return idx;
0114
0115     ret = clk_prepare_enable(res.clk);
0116     if (ret)
0117         return ret;
0118
0119     if (sclk) {
0120         clk_set_rate(res.clk, res.desired_clk_hz);
0121
0122         *sclk = res.div | armada510_clk_sels[idx];
0123
0124         /* We are now using this clock */
0125         v->sel_clk = res.clk;
0126         swap(dcrtc->clk, res.clk);
0127     }
0128
0129     clk_disable_unprepare(res.clk);
0130
0131     return 0;
0132 }
0133
0134 static void armada510_crtc_disable(struct armada_crtc *dcrtc)
0135 {
0136     if (dcrtc->clk) {
0137         clk_disable_unprepare(dcrtc->clk);
0138         dcrtc->clk = NULL;
0139     }
0140 }
0141
0142 static void armada510_crtc_enable(struct armada_crtc *dcrtc,
0143     const struct drm_display_mode *mode)
0144 {
0145     struct armada510_variant_data *v = dcrtc->variant_data;
0146
0147     if (!dcrtc->clk && v->sel_clk) {
0148         if (!WARN_ON(clk_prepare_enable(v->sel_clk)))
0149             dcrtc->clk = v->sel_clk;
0150     }
0151 }
0152
0153 const struct armada_variant armada510_ops = {
0154     .has_spu_adv_reg = true,
0155     .init = armada510_crtc_init,
0156     .compute_clock = armada510_crtc_compute_clock,
0157     .disable = armada510_crtc_disable,
0158     .enable = armada510_crtc_enable,
0159 };