drm/arm/hdlcd_regs.h

0001 /*
0002  * Copyright (C) 2013,2014 ARM Limited
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file COPYING in the main directory of this archive
0006  * for more details.
0007  *
0008  *  ARM HDLCD Controller register definition
0009  */
0010
0011 #ifndef __HDLCD_REGS_H__
0012 #define __HDLCD_REGS_H__
0013
0014 /* register offsets */
0015 #define HDLCD_REG_VERSION       0x0000  /* ro */
0016 #define HDLCD_REG_INT_RAWSTAT       0x0010  /* rw */
0017 #define HDLCD_REG_INT_CLEAR     0x0014  /* wo */
0018 #define HDLCD_REG_INT_MASK      0x0018  /* rw */
0019 #define HDLCD_REG_INT_STATUS        0x001c  /* ro */
0020 #define HDLCD_REG_FB_BASE       0x0100  /* rw */
0021 #define HDLCD_REG_FB_LINE_LENGTH    0x0104  /* rw */
0022 #define HDLCD_REG_FB_LINE_COUNT     0x0108  /* rw */
0023 #define HDLCD_REG_FB_LINE_PITCH     0x010c  /* rw */
0024 #define HDLCD_REG_BUS_OPTIONS       0x0110  /* rw */
0025 #define HDLCD_REG_V_SYNC        0x0200  /* rw */
0026 #define HDLCD_REG_V_BACK_PORCH      0x0204  /* rw */
0027 #define HDLCD_REG_V_DATA        0x0208  /* rw */
0028 #define HDLCD_REG_V_FRONT_PORCH     0x020c  /* rw */
0029 #define HDLCD_REG_H_SYNC        0x0210  /* rw */
0030 #define HDLCD_REG_H_BACK_PORCH      0x0214  /* rw */
0031 #define HDLCD_REG_H_DATA        0x0218  /* rw */
0032 #define HDLCD_REG_H_FRONT_PORCH     0x021c  /* rw */
0033 #define HDLCD_REG_POLARITIES        0x0220  /* rw */
0034 #define HDLCD_REG_COMMAND       0x0230  /* rw */
0035 #define HDLCD_REG_PIXEL_FORMAT      0x0240  /* rw */
0036 #define HDLCD_REG_RED_SELECT        0x0244  /* rw */
0037 #define HDLCD_REG_GREEN_SELECT      0x0248  /* rw */
0038 #define HDLCD_REG_BLUE_SELECT       0x024c  /* rw */
0039
0040 /* version */
0041 #define HDLCD_PRODUCT_ID        0x1CDC0000
0042 #define HDLCD_PRODUCT_MASK      0xFFFF0000
0043 #define HDLCD_VERSION_MAJOR_MASK    0x0000FF00
0044 #define HDLCD_VERSION_MINOR_MASK    0x000000FF
0045
0046 /* interrupts */
0047 #define HDLCD_INTERRUPT_DMA_END     (1 << 0)
0048 #define HDLCD_INTERRUPT_BUS_ERROR   (1 << 1)
0049 #define HDLCD_INTERRUPT_VSYNC       (1 << 2)
0050 #define HDLCD_INTERRUPT_UNDERRUN    (1 << 3)
0051 #define HDLCD_DEBUG_INT_MASK        (HDLCD_INTERRUPT_DMA_END |  \
0052                     HDLCD_INTERRUPT_BUS_ERROR | \
0053                     HDLCD_INTERRUPT_UNDERRUN)
0054
0055 /* polarities */
0056 #define HDLCD_POLARITY_VSYNC        (1 << 0)
0057 #define HDLCD_POLARITY_HSYNC        (1 << 1)
0058 #define HDLCD_POLARITY_DATAEN       (1 << 2)
0059 #define HDLCD_POLARITY_DATA     (1 << 3)
0060 #define HDLCD_POLARITY_PIXELCLK     (1 << 4)
0061
0062 /* commands */
0063 #define HDLCD_COMMAND_DISABLE       (0 << 0)
0064 #define HDLCD_COMMAND_ENABLE        (1 << 0)
0065
0066 /* pixel format */
0067 #define HDLCD_PIXEL_FMT_LITTLE_ENDIAN   (0 << 31)
0068 #define HDLCD_PIXEL_FMT_BIG_ENDIAN  (1 << 31)
0069 #define HDLCD_BYTES_PER_PIXEL_MASK  (3 << 3)
0070
0071 /* bus options */
0072 #define HDLCD_BUS_BURST_MASK        0x01f
0073 #define HDLCD_BUS_MAX_OUTSTAND      0xf00
0074 #define HDLCD_BUS_BURST_NONE        (0 << 0)
0075 #define HDLCD_BUS_BURST_1       (1 << 0)
0076 #define HDLCD_BUS_BURST_2       (1 << 1)
0077 #define HDLCD_BUS_BURST_4       (1 << 2)
0078 #define HDLCD_BUS_BURST_8       (1 << 3)
0079 #define HDLCD_BUS_BURST_16      (1 << 4)
0080
0081 /* Max resolution supported is 4096x4096, 32bpp */
0082 #define HDLCD_MAX_XRES          4096
0083 #define HDLCD_MAX_YRES          4096
0084
0085 #define NR_PALETTE          256
0086
0087 #endif /* __HDLCD_REGS_H__ */